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axi_ad9265: Added CDC and reset constraints

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Adrian Costina 2015-04-23 10:27:29 +03:00
parent 08f19d489f
commit a6cb6b7672
2 changed files with 48 additions and 0 deletions
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44
library/axi_ad9265/axi_ad9265_constr.xdc Normal file
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@ -0,0 +1,44 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad9265_clk [get_clocks -of_objects [get_ports adc_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad9265_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

4
library/axi_ad9265/axi_ad9265_ip.tcl
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@ -22,8 +22,12 @@ adi_ip_files axi_ad9265 [list \
"axi_ad9265_pnmon.v" \ "axi_ad9265_pnmon.v" \
"axi_ad9265_if.v" \ "axi_ad9265_if.v" \
"axi_ad9265_channel.v" \ "axi_ad9265_channel.v" \
"axi_ad9265_constr.xdc" \
"axi_ad9265.v"] "axi_ad9265.v"]
adi_ip_properties axi_ad9265 adi_ip_properties axi_ad9265
adi_ip_constraints axi_ad9265 [list \
"axi_ad9265_constr.xdc" ]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]