motcon2_fmc: Remove project

main
Adrian Costina 2019-07-22 13:23:43 +01:00
parent 6a721c0bf0
commit a6cff0f804
7 changed files with 0 additions and 861 deletions

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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# motor control
# port definition
# position detection interface
create_bd_port -dir I -from 2 -to 0 position_m1_i
create_bd_port -dir I -from 2 -to 0 position_m2_i
# current monitor interface
# clock
create_bd_port -dir O adc_clk_o
# data motor 1
create_bd_port -dir I adc_m1_ia_dat_i
create_bd_port -dir I adc_m1_ib_dat_i
create_bd_port -dir I adc_m1_vbus_dat_i
# data motor 2
create_bd_port -dir I adc_m2_ia_dat_i
create_bd_port -dir I adc_m2_ib_dat_i
create_bd_port -dir I adc_m2_vbus_dat_i
# motor control interface
create_bd_port -dir o -from 3 -to 0 gpo_o
# motor 1
create_bd_port -dir O fmc_m1_en_o
create_bd_port -dir O pwm_m1_al_o
create_bd_port -dir O pwm_m1_ah_o
create_bd_port -dir O pwm_m1_cl_o
create_bd_port -dir O pwm_m1_ch_o
create_bd_port -dir O pwm_m1_bl_o
create_bd_port -dir O pwm_m1_bh_o
# motor 2
create_bd_port -dir O fmc_m2_en_o
create_bd_port -dir O pwm_m2_al_o
create_bd_port -dir O pwm_m2_ah_o
create_bd_port -dir O pwm_m2_cl_o
create_bd_port -dir O pwm_m2_ch_o
create_bd_port -dir O pwm_m2_bl_o
create_bd_port -dir O pwm_m2_bh_o
# Ethernet
# phy 1
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii
# phy 2
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth2_rgmii
#common mdio interface
create_bd_port -dir O eth_mdio_mdc
create_bd_port -dir O eth_mdio_o
create_bd_port -dir O eth_mdio_t
create_bd_port -dir I eth_mdio_i
#common reset
create_bd_port -dir O eth_phy_rst_n
# reference clock for the delay interface used for the gmii to rgmii conversion
# iic
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ee2
# xadc interface
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vaux0
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vaux8
# core instantiation and configuration
# additions to default configuration
# Enable additional peripherals from the PS7 block
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 1
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO EMIO
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO EMIO
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_GRP_MDIO_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_GRP_MDIO_IO EMIO
# Add additional clocks to be used by gmii to rgmii modules and current monitoring modules
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT2_USED true
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT3_USED true
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT4_USED true
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT5_USED true
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT2_REQUESTED_OUT_FREQ 125
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT3_REQUESTED_OUT_FREQ 25
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT4_REQUESTED_OUT_FREQ 20
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT5_REQUESTED_OUT_FREQ 20
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT2_DRIVES No_buffer
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT3_DRIVES No_buffer
ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT4_DRIVES No_buffer
# speed detectors
# speed detector core motor 1
ad_ip_instance axi_mc_speed speed_detector_m1
# dma motor 1
ad_ip_instance axi_dmac speed_detector_m1_dma
ad_ip_parameter speed_detector_m1_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter speed_detector_m1_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter speed_detector_m1_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter speed_detector_m1_dma CONFIG.CYCLIC 0
ad_ip_parameter speed_detector_m1_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_parameter speed_detector_m1_dma CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter speed_detector_m1_dma CONFIG.DMA_AXI_PROTOCOL_DEST 0
ad_ip_parameter speed_detector_m1_dma CONFIG.AXI_SLICE_SRC 1
# speed detector core motor 2
ad_ip_instance axi_mc_speed speed_detector_m2
# dma motor 2
ad_ip_instance axi_dmac speed_detector_m2_dma
ad_ip_parameter speed_detector_m2_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter speed_detector_m2_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter speed_detector_m2_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter speed_detector_m2_dma CONFIG.CYCLIC 0
ad_ip_parameter speed_detector_m2_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_parameter speed_detector_m2_dma CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter speed_detector_m2_dma CONFIG.DMA_AXI_PROTOCOL_DEST 0
ad_ip_parameter speed_detector_m2_dma CONFIG.AXI_SLICE_SRC 1
# current monitor peripherals
# current monitor core motor 1
ad_ip_instance axi_mc_current_monitor current_monitor_m1
# dma motor 1
ad_ip_instance axi_dmac current_monitor_m1_dma
ad_ip_parameter current_monitor_m1_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter current_monitor_m1_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter current_monitor_m1_dma CONFIG.CYCLIC 0
ad_ip_parameter current_monitor_m1_dma CONFIG.DMA_AXI_PROTOCOL_DEST 0
ad_ip_parameter current_monitor_m1_dma CONFIG.SYNC_TRANSFER_START true
# data packer motor 1
#
ad_ip_instance util_cpack2 current_monitor_m1_pack { \
NUM_OF_CHANNELS 3 \
SAMPLE_DATA_WIDTH 16 \
}
# current monitor core motor 2
ad_ip_instance axi_mc_current_monitor current_monitor_m2
# dma motor 2
ad_ip_instance axi_dmac current_monitor_m2_dma
ad_ip_parameter current_monitor_m2_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter current_monitor_m2_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter current_monitor_m2_dma CONFIG.CYCLIC 0
ad_ip_parameter current_monitor_m2_dma CONFIG.DMA_AXI_PROTOCOL_DEST 0
ad_ip_parameter current_monitor_m2_dma CONFIG.SYNC_TRANSFER_START true
# data packer motor 2
ad_ip_instance util_cpack2 current_monitor_m2_pack { \
NUM_OF_CHANNELS 3 \
SAMPLE_DATA_WIDTH 16 \
}
#controller
# controller core motor 1
ad_ip_instance axi_mc_controller controller_m1
# controller core motor 2
ad_ip_instance axi_mc_controller controller_m2
#ethernet gmii to rgmii converters
# phy 1
ad_ip_instance util_gmii_to_rgmii gmii_to_rgmii_eth1
ad_ip_parameter gmii_to_rgmii_eth1 CONFIG.PHY_AD "00000"
ad_ip_parameter gmii_to_rgmii_eth1 CONFIG.IODELAY_CTRL 1
# phy 2
ad_ip_instance util_gmii_to_rgmii gmii_to_rgmii_eth2
ad_ip_parameter gmii_to_rgmii_eth2 CONFIG.PHY_AD "00001"
# iic
ad_ip_instance axi_iic iic_ee2
# xadc
ad_ip_instance xadc_wiz xadc_core
ad_ip_parameter xadc_core CONFIG.XADC_STARUP_SELECTION simultaneous_sampling
ad_ip_parameter xadc_core CONFIG.ENABLE_EXTERNAL_MUX true
ad_ip_parameter xadc_core CONFIG.EXTERNAL_MUX_CHANNEL VAUXP0_VAUXN0
ad_ip_parameter xadc_core CONFIG.CHANNEL_ENABLE_VP_VN false
ad_ip_parameter xadc_core CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 true
ad_ip_parameter xadc_core CONFIG.CHANNEL_ENABLE_VAUXP8_VAUXN8 true
ad_ip_parameter xadc_core CONFIG.OT_ALARM false
ad_ip_parameter xadc_core CONFIG.USER_TEMP_ALARM false
ad_ip_parameter xadc_core CONFIG.VCCAUX_ALARM false
ad_ip_parameter xadc_core CONFIG.VCCINT_ALARM false
# connections
# speed detector
# motor 1
ad_connect $sys_cpu_clk speed_detector_m1/ref_clk
ad_connect $sys_cpu_clk speed_detector_m1_dma/fifo_wr_clk
ad_connect position_m1_i speed_detector_m1/position_i
ad_connect speed_detector_m1/new_speed_o speed_detector_m1_dma/fifo_wr_en
ad_connect speed_detector_m1/speed_o speed_detector_m1_dma/fifo_wr_din
# motor 2
ad_connect $sys_cpu_clk speed_detector_m2/ref_clk
ad_connect $sys_cpu_clk speed_detector_m2_dma/fifo_wr_clk
ad_connect position_m2_i speed_detector_m2/position_i
ad_connect speed_detector_m2/new_speed_o speed_detector_m2_dma/fifo_wr_en
ad_connect speed_detector_m2/speed_o speed_detector_m2_dma/fifo_wr_din
# current monitor
ad_connect adc_clk_o current_monitor_m1/adc_clk_o
# motor 1
ad_connect $sys_cpu_clk current_monitor_m1/ref_clk
ad_connect $sys_cpu_clk current_monitor_m1_dma/fifo_wr_clk
ad_connect current_monitor_m1/adc_clk_i sys_audio_clkgen/clk_out5
ad_connect adc_m1_ia_dat_i current_monitor_m1/adc_ia_dat_i
ad_connect adc_m1_ib_dat_i current_monitor_m1/adc_ib_dat_i
ad_connect adc_m1_vbus_dat_i current_monitor_m1/adc_vbus_dat_i
ad_connect $sys_cpu_clk current_monitor_m1_pack/clk
ad_connect $sys_cpu_reset current_monitor_m1_pack/reset
ad_connect current_monitor_m1/adc_enable_ia current_monitor_m1_pack/enable_0
ad_connect current_monitor_m1/adc_enable_ib current_monitor_m1_pack/enable_1
ad_connect current_monitor_m1/adc_enable_vbus current_monitor_m1_pack/enable_2
ad_connect current_monitor_m1/i_ready_o current_monitor_m1_pack/fifo_wr_en
ad_connect current_monitor_m1/ia_o current_monitor_m1_pack/fifo_wr_data_0
ad_connect current_monitor_m1/ib_o current_monitor_m1_pack/fifo_wr_data_1
ad_connect current_monitor_m1/vbus_o current_monitor_m1_pack/fifo_wr_data_2
ad_connect current_monitor_m1_pack/packed_fifo_wr current_monitor_m1_dma/fifo_wr
# motor 2
ad_connect $sys_cpu_clk current_monitor_m2/ref_clk
ad_connect $sys_cpu_clk current_monitor_m2_dma/fifo_wr_clk
ad_connect current_monitor_m2/adc_clk_i sys_audio_clkgen/clk_out5
ad_connect adc_m2_ia_dat_i current_monitor_m2/adc_ia_dat_i
ad_connect adc_m2_ib_dat_i current_monitor_m2/adc_ib_dat_i
ad_connect adc_m2_vbus_dat_i current_monitor_m2/adc_vbus_dat_i
ad_connect $sys_cpu_clk current_monitor_m2_pack/clk
ad_connect $sys_cpu_reset current_monitor_m2_pack/reset
ad_connect current_monitor_m2/adc_enable_ia current_monitor_m2_pack/enable_0
ad_connect current_monitor_m2/adc_enable_ib current_monitor_m2_pack/enable_1
ad_connect current_monitor_m2/adc_enable_vbus current_monitor_m2_pack/enable_2
ad_connect current_monitor_m2/i_ready_o current_monitor_m2_pack/fifo_wr_en
ad_connect current_monitor_m2/ia_o current_monitor_m2_pack/fifo_wr_data_0
ad_connect current_monitor_m2/ib_o current_monitor_m2_pack/fifo_wr_data_1
ad_connect current_monitor_m2/vbus_o current_monitor_m2_pack/fifo_wr_data_2
ad_connect current_monitor_m2_pack/packed_fifo_wr current_monitor_m2_dma/fifo_wr
#controller
# motor 1
ad_connect $sys_cpu_clk controller_m1/ref_clk
ad_connect controller_m1/ctrl_data_clk sys_audio_clkgen/clk_out5
ad_connect fmc_m1_en_o controller_m1/fmc_en_o
ad_connect pwm_m1_al_o controller_m1/pwm_al_o
ad_connect pwm_m1_ah_o controller_m1/pwm_ah_o
ad_connect pwm_m1_bl_o controller_m1/pwm_bl_o
ad_connect pwm_m1_bh_o controller_m1/pwm_bh_o
ad_connect pwm_m1_cl_o controller_m1/pwm_cl_o
ad_connect pwm_m1_ch_o controller_m1/pwm_ch_o
ad_connect controller_m1/sensors_o speed_detector_m1/hall_bemf_i
ad_connect controller_m1/position_i speed_detector_m1/position_o
ad_connect controller_m1/gpo_o gpo_o
ad_connect controller_m1/pwm_a_i GND
ad_connect controller_m1/pwm_b_i GND
ad_connect controller_m1/pwm_c_i GND
ad_connect controller_m2/pwm_a_i GND
ad_connect controller_m2/pwm_b_i GND
ad_connect controller_m2/pwm_c_i GND
# motor 2
ad_connect $sys_cpu_clk controller_m2/ref_clk
ad_connect controller_m2/ctrl_data_clk sys_audio_clkgen/clk_out5
ad_connect fmc_m2_en_o controller_m2/fmc_en_o
ad_connect pwm_m2_al_o controller_m2/pwm_al_o
ad_connect pwm_m2_ah_o controller_m2/pwm_ah_o
ad_connect pwm_m2_bl_o controller_m2/pwm_bl_o
ad_connect pwm_m2_bh_o controller_m2/pwm_bh_o
ad_connect pwm_m2_cl_o controller_m2/pwm_cl_o
ad_connect pwm_m2_ch_o controller_m2/pwm_ch_o
ad_connect controller_m2/sensors_o speed_detector_m2/hall_bemf_i
ad_connect controller_m2/position_i speed_detector_m2/position_o
# ethernet
ad_connect $sys_cpu_resetn eth_phy_rst_n
ad_connect sys_ps7/ENET0_MDIO_MDC eth_mdio_mdc
ad_connect sys_ps7/ENET0_MDIO_O eth_mdio_o
ad_connect sys_ps7/ENET0_MDIO_T eth_mdio_t
ad_connect sys_ps7/ENET0_MDIO_I eth_mdio_i
# phy 1
ad_connect $sys_dma_clk gmii_to_rgmii_eth1/idelayctrl_clk
ad_connect gmii_to_rgmii_eth1/gmii sys_ps7/GMII_ETHERNET_0
ad_connect eth1_rgmii gmii_to_rgmii_eth1/rgmii
ad_connect gmii_to_rgmii_eth1/reset sys_rstgen/peripheral_reset
ad_connect gmii_to_rgmii_eth1/clk_20m sys_audio_clkgen/clk_out4
ad_connect gmii_to_rgmii_eth1/clk_25m sys_audio_clkgen/clk_out3
ad_connect gmii_to_rgmii_eth1/clk_125m sys_audio_clkgen/clk_out2
ad_connect eth_mdio_mdc gmii_to_rgmii_eth1/mdio_mdc
ad_connect eth_mdio_o gmii_to_rgmii_eth1/mdio_in_w
ad_connect eth_mdio_i gmii_to_rgmii_eth1/mdio_in_r
# phy 2
ad_connect gmii_to_rgmii_eth2/gmii sys_ps7/GMII_ETHERNET_1
ad_connect eth2_rgmii gmii_to_rgmii_eth2/rgmii
ad_connect gmii_to_rgmii_eth2/reset sys_rstgen/peripheral_reset
ad_connect gmii_to_rgmii_eth2/clk_20m sys_audio_clkgen/clk_out4
ad_connect gmii_to_rgmii_eth2/clk_25m sys_audio_clkgen/clk_out3
ad_connect gmii_to_rgmii_eth2/clk_125m sys_audio_clkgen/clk_out2
ad_connect eth_mdio_mdc gmii_to_rgmii_eth2/mdio_mdc
ad_connect eth_mdio_o gmii_to_rgmii_eth2/mdio_in_w
ad_connect eth_mdio_i gmii_to_rgmii_eth2/mdio_in_r
# xadc
ad_connect xadc_core/Vaux0 vaux0
ad_connect xadc_core/Vaux8 vaux8
# iic
ad_connect iic_ee2/IIC iic_ee2
ad_connect $sys_cpu_resetn speed_detector_m1_dma/m_dest_axi_aresetn
ad_connect $sys_cpu_resetn speed_detector_m2_dma/m_dest_axi_aresetn
ad_connect $sys_cpu_resetn current_monitor_m1_dma/m_dest_axi_aresetn
ad_connect $sys_cpu_resetn current_monitor_m2_dma/m_dest_axi_aresetn
ad_connect $sys_cpu_resetn xadc_core/s_axi_aresetn
# address map
ad_cpu_interconnect 0x40410000 speed_detector_m1
ad_cpu_interconnect 0x40420000 current_monitor_m1
ad_cpu_interconnect 0x40430000 controller_m1
ad_cpu_interconnect 0x40440000 speed_detector_m2
ad_cpu_interconnect 0x40450000 current_monitor_m2
ad_cpu_interconnect 0x40460000 controller_m2
ad_cpu_interconnect 0x40510000 speed_detector_m1_dma
ad_cpu_interconnect 0x40520000 current_monitor_m1_dma
ad_cpu_interconnect 0x40540000 speed_detector_m2_dma
ad_cpu_interconnect 0x40550000 current_monitor_m2_dma
ad_cpu_interconnect 0x43200000 xadc_core
ad_cpu_interconnect 0x41510000 iic_ee2
ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_cpu_clk speed_detector_m1_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_cpu_clk speed_detector_m2_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_cpu_clk current_monitor_m1_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_cpu_clk current_monitor_m2_dma/m_dest_axi
ad_cpu_interrupt ps-7 mb-7 xadc_core/ip2intc_irpt
ad_cpu_interrupt ps-8 mb-8 current_monitor_m2_dma/irq
ad_cpu_interrupt ps-9 mb-9 speed_detector_m2_dma/irq
ad_cpu_interrupt ps-10 mb-10 current_monitor_m1_dma/irq
ad_cpu_interrupt ps-12 mb-12 iic_ee2/iic2intc_irpt
ad_cpu_interrupt ps-13 mb-13 speed_detector_m1_dma/irq

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := motcon2_fmc_zed
M_DEPS += ../common/motcon2_fmc_bd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_mc_controller
LIB_DEPS += axi_mc_current_monitor
LIB_DEPS += axi_mc_speed
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_gmii_to_rgmii
LIB_DEPS += util_i2c_mixer
LIB_DEPS += util_pack/util_cpack2
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/motcon2_fmc_bd.tcl

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# Motor Control
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[0]}]
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[1]}]
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[2]}]
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[0]}] ; #M2_SENSOR_A
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[1]}] ; #M2_SENSOR_B
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[2]}] ; #M2_SENSOR_C
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports vt_enable]
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports fmc_m1_en_o]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ah_o]
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports pwm_m1_al_o]
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bh_o]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bl_o]
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ch_o]
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports pwm_m1_cl_o]
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dh_o]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dl_o]
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports fmc_m2_en_o]
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ah_o]
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_al_o]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o]
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o]
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25 } [get_ports adc_clk_o]
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 } [get_ports adc_m1_vbus_dat_i]
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 } [get_ports adc_m2_vbus_dat_i]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ia_dat_i]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ib_dat_i]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ia_dat_i]
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ib_dat_i]
# GPO
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25 } [get_ports {gpo[0]}]
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25 } [get_ports {gpo[1]}]
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25 } [get_ports {gpo[2]}]
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}]
# GPI
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}]
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}]
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0]
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0]
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8]
# SPI
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sel1_rdc ]
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_miso ]
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_mosi ]
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sck ]
#FMC_SAMPLE_N
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports fmc_sample_n]
# IIC
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_scl_io]
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_sda_io]
# Ethernet common
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports eth_mdio_mdc]
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25 PULLUP true} [get_ports eth_mdio_p]
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports eth_phy_rst_n]
# Ethernet 1
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[0]}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}]
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}]
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_txc]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[3]}]
# Ethernet 2
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc]
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rx_ctl]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[0]}]
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}]
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}]
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_txc]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[3]}]
#create clocks
# Clock Period Constraints
create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc]
create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc]
create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC]
# Ethernet 1
#IDELAY
set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP if_delay_group [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP if_delay_group [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
# Ethernet 2
#IDELAY
set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP if_delay_group [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP if_delay_group [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]

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@ -1,15 +0,0 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project motcon2_fmc_zed
adi_project_files motcon2_fmc_zed [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
set_property strategy Performance_ExtraTimingOpt [get_runs impl_1]
adi_project_run motcon2_fmc_zed

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@ -1,329 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
input [3:0] eth1_rgmii_rd,
input eth1_rgmii_rx_ctl,
input eth1_rgmii_rxc,
output [3:0] eth1_rgmii_td,
output eth1_rgmii_tx_ctl,
output eth1_rgmii_txc,
input [3:0] eth2_rgmii_rd,
input eth2_rgmii_rx_ctl,
input eth2_rgmii_rxc,
output [3:0] eth2_rgmii_td,
output eth2_rgmii_tx_ctl,
output eth2_rgmii_txc,
inout eth_mdio_p,
output eth_mdio_mdc,
output eth_phy_rst_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
input [2:0] position_m1_i,
input [2:0] position_m2_i,
output adc_clk_o,
input adc_m1_ia_dat_i,
input adc_m1_ib_dat_i,
input adc_m1_vbus_dat_i,
output fmc_m1_en_o,
output fmc_m2_en_o,
input adc_m2_ia_dat_i,
input adc_m2_ib_dat_i,
input adc_m2_vbus_dat_i,
output pwm_m1_ah_o,
output pwm_m1_al_o,
output pwm_m1_bh_o,
output pwm_m1_bl_o,
output pwm_m1_ch_o,
output pwm_m1_cl_o,
output pwm_m1_dh_o,
output pwm_m1_dl_o,
output pwm_m2_ah_o,
output pwm_m2_al_o,
output pwm_m2_bh_o,
output pwm_m2_bl_o,
output pwm_m2_ch_o,
output pwm_m2_cl_o,
output pwm_m2_dh_o,
output pwm_m2_dl_o,
output vt_enable,
input vauxn0,
input vauxn8,
input vauxp0,
input vauxp8,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
inout iic_ee2_scl_io,
inout iic_ee2_sda_io,
output fmc_spi1_sel1_rdc,
input fmc_spi1_miso,
output fmc_spi1_mosi,
output fmc_spi1_sck,
output fmc_sample_n,
output [ 3:0] gpo,
input [ 1:0] gpi,
input otg_vbusoc);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire eth_mdio_o;
wire eth_mdio_i;
wire eth_mdio_t;
// assignments
assign fmc_sample_n = gpio_o[32];
assign gpio_i[34:33] = gpi[1:0];
assign vt_enable = 1'b1;
assign pwm_m1_dh_o = 1'b0;
assign pwm_m1_dl_o = 1'b0;
assign pwm_m2_dh_o = 1'b0;
assign pwm_m2_dl_o = 1'b0;
assign gpio_i[63:35] = gpio_o[63:35];
assign gpio_i[32] = gpio_o[32];
// instantiations
ad_iobuf #(
.DATA_WIDTH(32))
i_gpio_bd (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
ad_iobuf #(
.DATA_WIDTH(1))
i_mdio_p (
.dio_t(eth_mdio_t),
.dio_i(eth_mdio_o),
.dio_o(eth_mdio_i),
.dio_p(eth_mdio_p));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.eth1_rgmii_rd(eth1_rgmii_rd),
.eth1_rgmii_rx_ctl(eth1_rgmii_rx_ctl),
.eth1_rgmii_rxc(eth1_rgmii_rxc),
.eth1_rgmii_td(eth1_rgmii_td),
.eth1_rgmii_tx_ctl(eth1_rgmii_tx_ctl),
.eth1_rgmii_txc(eth1_rgmii_txc),
.eth2_rgmii_rd(eth2_rgmii_rd),
.eth2_rgmii_rx_ctl(eth2_rgmii_rx_ctl),
.eth2_rgmii_rxc(eth2_rgmii_rxc),
.eth2_rgmii_td(eth2_rgmii_td),
.eth2_rgmii_tx_ctl(eth2_rgmii_tx_ctl),
.eth2_rgmii_txc(eth2_rgmii_txc),
.eth_phy_rst_n(eth_phy_rst_n),
.eth_mdio_o(eth_mdio_o),
.eth_mdio_t(eth_mdio_t),
.eth_mdio_i(eth_mdio_i),
.eth_mdio_mdc(eth_mdio_mdc),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.position_m1_i(position_m1_i),
.position_m2_i(position_m2_i),
.adc_clk_o(adc_clk_o),
.fmc_m1_en_o(fmc_m1_en_o),
.adc_m1_ia_dat_i(adc_m1_ia_dat_i),
.adc_m1_ib_dat_i(adc_m1_ib_dat_i),
.adc_m1_vbus_dat_i(adc_m1_vbus_dat_i),
.fmc_m2_en_o(fmc_m2_en_o),
.adc_m2_ia_dat_i(adc_m2_ia_dat_i),
.adc_m2_ib_dat_i(adc_m2_ib_dat_i),
.adc_m2_vbus_dat_i(adc_m2_vbus_dat_i),
.gpo_o(gpo),
.pwm_m1_ah_o(pwm_m1_ah_o),
.pwm_m1_al_o(pwm_m1_al_o),
.pwm_m1_bh_o(pwm_m1_bh_o),
.pwm_m1_bl_o(pwm_m1_bl_o),
.pwm_m1_ch_o(pwm_m1_ch_o),
.pwm_m1_cl_o(pwm_m1_cl_o),
.pwm_m2_ah_o(pwm_m2_ah_o),
.pwm_m2_al_o(pwm_m2_al_o),
.pwm_m2_bh_o(pwm_m2_bh_o),
.pwm_m2_bl_o(pwm_m2_bl_o),
.pwm_m2_ch_o(pwm_m2_ch_o),
.pwm_m2_cl_o(pwm_m2_cl_o),
.vaux0_v_n(vauxn0),
.vaux0_v_p(vauxp0),
.vaux8_v_n(vauxn8),
.vaux8_v_p(vauxp8),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.iic_ee2_scl_io(iic_ee2_scl_io),
.iic_ee2_sda_io(iic_ee2_sda_io),
.spi0_clk_i (1'b0),
.spi0_clk_o (fmc_spi1_sck),
.spi0_csn_0_o (fmc_spi1_sel1_rdc),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (fmc_spi1_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (fmc_spi1_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************