diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl
index d08465902..8332b3431 100644
--- a/projects/daq3/zc706/system_bd.tcl
+++ b/projects/daq3/zc706/system_bd.tcl
@@ -23,3 +23,32 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
 
 source ../common/daq3_bd.tcl
 
+# ila 
+
+set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc]
+set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc
+set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
+set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
+
+set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
+set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
+set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
+set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
+set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_adc
+set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
+set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
+set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
+
+ad_connect  util_daq3_gt/rx_rst mfifo_adc/din_rst
+ad_connect  util_daq3_gt/rx_out_clk mfifo_adc/din_clk
+ad_connect  axi_ad9680_core/adc_valid_0 mfifo_adc/din_valid
+ad_connect  axi_ad9680_core/adc_data_0 mfifo_adc/din_data_0
+ad_connect  axi_ad9680_core/adc_data_1 mfifo_adc/din_data_1
+ad_connect  util_daq3_gt/rx_rst mfifo_adc/dout_rst
+ad_connect  util_daq3_gt/rx_out_clk mfifo_adc/dout_clk
+ad_connect  util_daq3_gt/rx_out_clk ila_adc/clk
+ad_connect  mfifo_adc/dout_valid ila_adc/probe0
+ad_connect  mfifo_adc/dout_data_0 ila_adc/probe1
+ad_connect  mfifo_adc/dout_data_1 ila_adc/probe2
+
+
diff --git a/projects/daq3/zc706/system_constr.xdc b/projects/daq3/zc706/system_constr.xdc
index 1589e4105..fd45dcf08 100644
--- a/projects/daq3/zc706/system_constr.xdc
+++ b/projects/daq3/zc706/system_constr.xdc
@@ -54,6 +54,6 @@ set_property  -dict {PACKAGE_PIN  AJ24  IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
 
 create_clock -name tx_ref_clk   -period  2.00 [get_ports tx_ref_clk_p]
 create_clock -name rx_ref_clk   -period  2.00 [get_ports rx_ref_clk_p]
-create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/TXOUTCLK]
-create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK]
+create_clock -name tx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
+create_clock -name rx_div_clk   -period  4.00 [get_pins i_system_wrapper/system_i/axi_daq3_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]