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axi_mc_controller: Removed channels, as no data needs to be streamed to DMA

main
Adrian Costina 2015-10-09 13:54:03 +03:00
parent 694dbd3259
commit a753d506c5
1 changed files with 3 additions and 496 deletions
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499
library/axi_mc_controller/axi_mc_controller.v
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@ -58,51 +58,12 @@ module axi_mc_controller
input pwm_a_i, input pwm_a_i,
input pwm_b_i, input pwm_b_i,
input pwm_c_i, input pwm_c_i,
input ctrl_data_valid_i,
input [31:0] ctrl_data0_i,
input [31:0] ctrl_data1_i,
input [31:0] ctrl_data2_i,
input [31:0] ctrl_data3_i,
input [31:0] ctrl_data4_i,
input [31:0] ctrl_data5_i,
input [31:0] ctrl_data6_i,
input [31:0] ctrl_data7_i,
// interconnection with other modules // interconnection with other modules
output[1:0] sensors_o, output[1:0] sensors_o,
input [2:0] position_i, input [2:0] position_i,
// channel interface
output adc_clk_o,
output adc_enable_c0,
output adc_enable_c1,
output adc_enable_c2,
output adc_enable_c3,
output adc_enable_c4,
output adc_enable_c5,
output adc_enable_c6,
output adc_enable_c7,
output adc_valid_c0,
output adc_valid_c1,
output adc_valid_c2,
output adc_valid_c3,
output adc_valid_c4,
output adc_valid_c5,
output adc_valid_c6,
output adc_valid_c7,
output [31:0] adc_data_c0,
output [31:0] adc_data_c1,
output [31:0] adc_data_c2,
output [31:0] adc_data_c3,
output [31:0] adc_data_c4,
output [31:0] adc_data_c5,
output [31:0] adc_data_c6,
output [31:0] adc_data_c7,
// axi interface // axi interface
input s_axi_aclk, input s_axi_aclk,
@ -152,36 +113,9 @@ wire up_wreq_s;
wire [13:0] up_raddr_s; wire [13:0] up_raddr_s;
wire [13:0] up_waddr_s; wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s; wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire [31:0] up_control_rdata_s; wire [31:0] up_control_rdata_s;
wire [31:0] rdata_c0_s;
wire [31:0] rdata_c1_s;
wire [31:0] rdata_c2_s;
wire [31:0] rdata_c3_s;
wire [31:0] rdata_c4_s;
wire [31:0] rdata_c5_s;
wire [31:0] rdata_c6_s;
wire [31:0] rdata_c7_s;
wire up_adc_common_wack_s;
wire up_adc_common_rack_s;
wire up_control_wack_s; wire up_control_wack_s;
wire up_control_rack_s; wire up_control_rack_s;
wire wack_c0_s;
wire rack_c0_s;
wire wack_c1_s;
wire rack_c1_s;
wire wack_c2_s;
wire rack_c2_s;
wire wack_c3_s;
wire rack_c3_s;
wire wack_c4_s;
wire rack_c4_s;
wire wack_c5_s;
wire rack_c5_s;
wire wack_c6_s;
wire rack_c6_s;
wire wack_c7_s;
wire rack_c7_s;
wire run_s; wire run_s;
wire star_delta_s; wire star_delta_s;
wire dir_s; wire dir_s;
@ -206,24 +140,6 @@ assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ctrl_data_clk; assign adc_clk_o = ctrl_data_clk;
assign adc_valid_c0 = ctrl_data_valid_i;
assign adc_valid_c1 = ctrl_data_valid_i;
assign adc_valid_c2 = ctrl_data_valid_i;
assign adc_valid_c3 = ctrl_data_valid_i;
assign adc_valid_c4 = ctrl_data_valid_i;
assign adc_valid_c5 = ctrl_data_valid_i;
assign adc_valid_c6 = ctrl_data_valid_i;
assign adc_valid_c7 = ctrl_data_valid_i;
assign adc_data_c0 = ctrl_data0_i;
assign adc_data_c1 = ctrl_data1_i;
assign adc_data_c2 = ctrl_data2_i;
assign adc_data_c3 = ctrl_data3_i;
assign adc_data_c4 = ctrl_data4_i;
assign adc_data_c5 = ctrl_data5_i;
assign adc_data_c6 = ctrl_data6_i;
assign adc_data_c7 = ctrl_data7_i;
assign ctrl_rst_o = !run_s; assign ctrl_rst_o = !run_s;
// monitor signals // monitor signals
@ -253,9 +169,9 @@ always @(negedge up_rstn or posedge up_clk) begin
up_wack <= 'd0; up_wack <= 'd0;
up_rack <= 'd0; up_rack <= 'd0;
end else begin end else begin
up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_c0_s | rdata_c1_s | rdata_c2_s | rdata_c3_s | rdata_c4_s | rdata_c5_s | rdata_c6_s | rdata_c7_s; up_rdata <= up_control_rdata_s ;
up_rack <= up_control_rack_s | up_adc_common_rack_s | rack_c0_s | rack_c1_s | rack_c2_s | rack_c3_s | rack_c4_s | rack_c5_s | rack_c6_s | rack_c7_s; up_rack <= up_control_rack_s ;
up_wack <= up_control_wack_s | up_adc_common_wack_s | wack_c0_s | wack_c1_s | wack_c2_s | wack_c3_s | wack_c4_s | wack_c5_s | wack_c6_s | wack_c7_s; up_wack <= up_control_wack_s ;
end end
end end
@ -309,415 +225,6 @@ control_registers control_reg_inst(
.calibrate_adcs_o(), .calibrate_adcs_o(),
.pwm_open_o(pwm_open_s)); .pwm_open_o(pwm_open_s));
up_adc_channel #(.ADC_CHANNEL_ID(0)) adc_channel0(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c0),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c0_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c0_s),
.up_rack (rack_c0_s));
up_adc_channel #(.ADC_CHANNEL_ID(1)) adc_channel1(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c1),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c1_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c1_s),
.up_rack (rack_c1_s));
up_adc_channel #(.ADC_CHANNEL_ID(2)) adc_channel2(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c2),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c2_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c2_s),
.up_rack (rack_c2_s));
up_adc_channel #(.ADC_CHANNEL_ID(3)) adc_channel3(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c3),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c3_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c3_s),
.up_rack (rack_c3_s));
up_adc_channel #(.ADC_CHANNEL_ID(4)) adc_channel4(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c4),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c4_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c4_s),
.up_rack (rack_c4_s));
up_adc_channel #(.ADC_CHANNEL_ID(5)) adc_channel5(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c5),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c5_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c5_s),
.up_rack (rack_c5_s));
up_adc_channel #(.ADC_CHANNEL_ID(6)) adc_channel6(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c6),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c6_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c6_s),
.up_rack (rack_c6_s));
up_adc_channel #(.ADC_CHANNEL_ID(7)) adc_channel7(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c7),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c7_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c7_s),
.up_rack (rack_c7_s));
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.up_drp_sel(),
.up_drp_wr(),
.up_drp_addr(),
.up_drp_wdata(),
.up_drp_rdata(16'd0),
.up_drp_ready(1'b0),
.up_drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd7),
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_adc_common_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_adc_common_rdata_s),
.up_rack (up_adc_common_rack_s));
// up bus interface // up bus interface
up_axi i_up_axi( up_axi i_up_axi(