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library/axi_ad9122,axi_ad9643: added

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Rejeesh Kutty 2014-03-11 12:13:25 -04:00
parent e1f23e7d49
commit a76d6c4686
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library/axi_ad9122/axi_ad9122.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122 (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
// master/slave
dac_enable_out,
dac_enable_in,
// dma interface
dac_div_clk,
dac_drd,
dac_ddata,
dac_ddata_64,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
// master/slave
output dac_enable_out;
input dac_enable_in;
// dma interface
output dac_div_clk;
output dac_drd;
input [127:0] dac_ddata;
input [63:0] dac_ddata_64;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire mmcm_rst;
wire drp_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire [127:0] dac_ddata_s;
wire dac_frame_i0_s;
wire [15:0] dac_data_i0_s;
wire dac_frame_i1_s;
wire [15:0] dac_data_i1_s;
wire dac_frame_i2_s;
wire [15:0] dac_data_i2_s;
wire dac_frame_i3_s;
wire [15:0] dac_data_i3_s;
wire dac_frame_q0_s;
wire [15:0] dac_data_q0_s;
wire dac_frame_q1_s;
wire [15:0] dac_data_q1_s;
wire dac_frame_q2_s;
wire [15:0] dac_data_q2_s;
wire dac_frame_q3_s;
wire [15:0] dac_data_q3_s;
wire dac_status_s;
wire drp_sel_s;
wire drp_wr_s;
wire [11:0] drp_addr_s;
wire [15:0] drp_wdata_s;
wire [15:0] drp_rdata_s;
wire drp_ready_s;
wire drp_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
// dac dma data - requires 128bits.
// however, it can be sourced either from a 128bit bus or a 64bit bus.
// 64bit interface is for low bandwidth designs.
// only one of the source can be used at a time and the other one must be tied to 0x0.
assign dac_ddata_s = dac_ddata | {{2{dac_ddata_64[63:32]}}, {2{dac_ddata_64[31:0]}}};
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// device interface
axi_ad9122_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_SERDES_DDR_N (PCORE_SERDES_DDR_N),
.PCORE_MMCM_BUFIO_N (PCORE_MMCM_BUFIO_N))
i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_rst (dac_rst),
.dac_clk (),
.dac_div_clk (dac_div_clk),
.dac_status (dac_status_s),
.dac_frame_i0 (dac_frame_i0_s),
.dac_data_i0 (dac_data_i0_s),
.dac_frame_i1 (dac_frame_i1_s),
.dac_data_i1 (dac_data_i1_s),
.dac_frame_i2 (dac_frame_i2_s),
.dac_data_i2 (dac_data_i2_s),
.dac_frame_i3 (dac_frame_i3_s),
.dac_data_i3 (dac_data_i3_s),
.dac_frame_q0 (dac_frame_q0_s),
.dac_data_q0 (dac_data_q0_s),
.dac_frame_q1 (dac_frame_q1_s),
.dac_data_q1 (dac_data_q1_s),
.dac_frame_q2 (dac_frame_q2_s),
.dac_data_q2 (dac_data_q2_s),
.dac_frame_q3 (dac_frame_q3_s),
.dac_data_q3 (dac_data_q3_s),
.mmcm_rst (mmcm_rst),
.drp_clk (up_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ready (drp_ready_s),
.drp_locked (drp_locked_s));
// core
axi_ad9122_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_frame_i0 (dac_frame_i0_s),
.dac_data_i0 (dac_data_i0_s),
.dac_frame_i1 (dac_frame_i1_s),
.dac_data_i1 (dac_data_i1_s),
.dac_frame_i2 (dac_frame_i2_s),
.dac_data_i2 (dac_data_i2_s),
.dac_frame_i3 (dac_frame_i3_s),
.dac_data_i3 (dac_data_i3_s),
.dac_frame_q0 (dac_frame_q0_s),
.dac_data_q0 (dac_data_q0_s),
.dac_frame_q1 (dac_frame_q1_s),
.dac_data_q1 (dac_data_q1_s),
.dac_frame_q2 (dac_frame_q2_s),
.dac_data_q2 (dac_data_q2_s),
.dac_frame_q3 (dac_frame_q3_s),
.dac_data_q3 (dac_data_q3_s),
.dac_status (dac_status_s),
.dac_enable_out (dac_enable_out),
.dac_enable_in (dac_enable_in),
.dac_drd (dac_drd),
.dac_ddata (dac_ddata_s),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.mmcm_rst (mmcm_rst),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ready (drp_ready_s),
.drp_locked (drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122_channel (
// dac interface
dac_div_clk,
dac_rst,
dac_dds_data_0,
dac_dds_data_1,
dac_dds_data_2,
dac_dds_data_3,
// processor interface
dac_dds_enable,
dac_dds_format,
dac_dds_pattenb,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
// dac interface
input dac_div_clk;
input dac_rst;
output [15:0] dac_dds_data_0;
output [15:0] dac_dds_data_1;
output [15:0] dac_dds_data_2;
output [15:0] dac_dds_data_3;
// processor interface
input dac_dds_enable;
input dac_dds_format;
input dac_dds_pattenb;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire [15:0] dac_dds_patt_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_patt_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_dds_scale_2_s;
// single channel dds
axi_ad9122_dds #(.DP_DISABLE(DP_DISABLE)) i_dds (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_data_0 (dac_dds_data_0),
.dac_dds_data_1 (dac_dds_data_1),
.dac_dds_data_2 (dac_dds_data_2),
.dac_dds_data_3 (dac_dds_data_3),
.dac_dds_enable (dac_dds_enable),
.dac_dds_format (dac_dds_format),
.dac_dds_pattenb (dac_dds_pattenb),
.dac_dds_patt_1 (dac_dds_patt_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_patt_2 (dac_dds_patt_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_dds_scale_2 (dac_dds_scale_2_s));
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_dds_patt_1 (dac_dds_patt_1_s),
.dac_dds_patt_2 (dac_dds_patt_2_s),
.dac_dds_sel (),
.dac_lb_enb (),
.dac_pn_enb (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122_core (
// dac interface
dac_div_clk,
dac_rst,
dac_frame_i0,
dac_data_i0,
dac_frame_i1,
dac_data_i1,
dac_frame_i2,
dac_data_i2,
dac_frame_i3,
dac_data_i3,
dac_frame_q0,
dac_data_q0,
dac_frame_q1,
dac_data_q1,
dac_frame_q2,
dac_data_q2,
dac_frame_q3,
dac_data_q3,
dac_status,
// master/slave
dac_enable_out,
dac_enable_in,
// dma interface
dac_drd,
dac_ddata,
dac_dovf,
dac_dunf,
// mmcm reset
mmcm_rst,
// drp interface
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
// dac interface
input dac_div_clk;
output dac_rst;
output dac_frame_i0;
output [15:0] dac_data_i0;
output dac_frame_i1;
output [15:0] dac_data_i1;
output dac_frame_i2;
output [15:0] dac_data_i2;
output dac_frame_i3;
output [15:0] dac_data_i3;
output dac_frame_q0;
output [15:0] dac_data_q0;
output dac_frame_q1;
output [15:0] dac_data_q1;
output dac_frame_q2;
output [15:0] dac_data_q2;
output dac_frame_q3;
output [15:0] dac_data_q3;
input dac_status;
// master/slave
output dac_enable_out;
input dac_enable_in;
// dma interface
output dac_drd;
input [127:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// mmcm reset
output mmcm_rst;
// drp interface
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg dac_enable = 'd0;
reg [15:0] dac_data_i0 = 'd0;
reg [15:0] dac_data_i1 = 'd0;
reg [15:0] dac_data_i2 = 'd0;
reg [15:0] dac_data_i3 = 'd0;
reg [15:0] dac_data_q0 = 'd0;
reg [15:0] dac_data_q1 = 'd0;
reg [15:0] dac_data_q2 = 'd0;
reg [15:0] dac_data_q3 = 'd0;
reg dac_frame_i0 = 'd0;
reg dac_frame_i1 = 'd0;
reg dac_frame_i2 = 'd0;
reg dac_frame_i3 = 'd0;
reg dac_frame_q0 = 'd0;
reg dac_frame_q1 = 'd0;
reg dac_frame_q2 = 'd0;
reg dac_frame_q3 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal signals
wire dac_enable_s;
wire dac_frame_s;
wire dac_datafmt_s;
wire [ 3:0] dac_datasel_s;
wire [15:0] dac_dds_data_0_0_s;
wire [15:0] dac_dds_data_0_1_s;
wire [15:0] dac_dds_data_0_2_s;
wire [15:0] dac_dds_data_0_3_s;
wire [15:0] dac_dds_data_1_0_s;
wire [15:0] dac_dds_data_1_1_s;
wire [15:0] dac_dds_data_1_2_s;
wire [15:0] dac_dds_data_1_3_s;
wire [31:0] up_rdata_0_s;
wire up_ack_0_s;
wire [31:0] up_rdata_1_s;
wire up_ack_1_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
// dac dma read
assign dac_drd = dac_enable;
// master/slave (clocks must be synchronous)
assign dac_enable_s = (PCORE_ID == 0) ? dac_enable_out : dac_enable_in;
always @(posedge dac_div_clk) begin
dac_enable <= dac_enable_s;
end
// dac outputs
always @(posedge dac_div_clk) begin
if (dac_datasel_s[3:1] == 3'd1) begin
dac_data_i0 <= dac_ddata[ 15: 0];
dac_data_i1 <= dac_ddata[ 47: 32];
dac_data_i2 <= dac_ddata[ 79: 64];
dac_data_i3 <= dac_ddata[111: 96];
dac_data_q0 <= dac_ddata[ 31: 16];
dac_data_q1 <= dac_ddata[ 63: 48];
dac_data_q2 <= dac_ddata[ 95: 80];
dac_data_q3 <= dac_ddata[127:112];
end else begin
dac_data_i0 <= dac_dds_data_0_0_s;
dac_data_i1 <= dac_dds_data_0_1_s;
dac_data_i2 <= dac_dds_data_0_2_s;
dac_data_i3 <= dac_dds_data_0_3_s;
dac_data_q0 <= dac_dds_data_1_0_s;
dac_data_q1 <= dac_dds_data_1_1_s;
dac_data_q2 <= dac_dds_data_1_2_s;
dac_data_q3 <= dac_dds_data_1_3_s;
end
if (dac_datasel_s[0] == 3'd1) begin
dac_frame_i0 <= 1'b1;
dac_frame_i1 <= 1'b0;
dac_frame_i2 <= 1'b1;
dac_frame_i3 <= 1'b0;
dac_frame_q0 <= 1'b1;
dac_frame_q1 <= 1'b0;
dac_frame_q2 <= 1'b1;
dac_frame_q3 <= 1'b0;
end else begin
dac_frame_i0 <= dac_frame_s;
dac_frame_i1 <= 1'b0;
dac_frame_i2 <= 1'b0;
dac_frame_i3 <= 1'b0;
dac_frame_q0 <= dac_frame_s;
dac_frame_q1 <= 1'b0;
dac_frame_q2 <= 1'b0;
dac_frame_q3 <= 1'b0;
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
up_ack <= up_ack_s | up_ack_0_s | up_ack_1_s;
end
end
// dac channel
axi_ad9122_channel #(
.CHID(0),
.DP_DISABLE(DP_DISABLE))
i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_data_0 (dac_dds_data_0_0_s),
.dac_dds_data_1 (dac_dds_data_0_1_s),
.dac_dds_data_2 (dac_dds_data_0_2_s),
.dac_dds_data_3 (dac_dds_data_0_3_s),
.dac_dds_enable (dac_enable),
.dac_dds_format (dac_datafmt_s),
.dac_dds_pattenb (dac_datasel_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_0_s),
.up_ack (up_ack_0_s));
// dac channel
axi_ad9122_channel #(
.CHID(1),
.DP_DISABLE(DP_DISABLE))
i_channel_1 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_data_0 (dac_dds_data_1_0_s),
.dac_dds_data_1 (dac_dds_data_1_1_s),
.dac_dds_data_2 (dac_dds_data_1_2_s),
.dac_dds_data_3 (dac_dds_data_1_3_s),
.dac_dds_enable (dac_enable),
.dac_dds_format (dac_datafmt_s),
.dac_dds_pattenb (dac_datasel_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_1_s),
.up_ack (up_ack_1_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
.mmcm_rst (mmcm_rst),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_out),
.dac_frame (dac_frame_s),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datasel (dac_datasel_s),
.dac_datarate (),
.dac_status (dac_status),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.drp_clk (up_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122_dds (
// dac interface
dac_div_clk,
dac_rst,
dac_dds_data_0,
dac_dds_data_1,
dac_dds_data_2,
dac_dds_data_3,
// processor interface
dac_dds_enable,
dac_dds_format,
dac_dds_pattenb,
dac_dds_patt_1,
dac_dds_init_1,
dac_dds_incr_1,
dac_dds_scale_1,
dac_dds_patt_2,
dac_dds_init_2,
dac_dds_incr_2,
dac_dds_scale_2);
// parameters
parameter DP_DISABLE = 0;
// dac interface
input dac_div_clk;
input dac_rst;
output [15:0] dac_dds_data_0;
output [15:0] dac_dds_data_1;
output [15:0] dac_dds_data_2;
output [15:0] dac_dds_data_3;
// processor interface
input dac_dds_enable;
input dac_dds_format;
input dac_dds_pattenb;
input [15:0] dac_dds_patt_1;
input [15:0] dac_dds_init_1;
input [15:0] dac_dds_incr_1;
input [15:0] dac_dds_scale_1;
input [15:0] dac_dds_patt_2;
input [15:0] dac_dds_init_2;
input [15:0] dac_dds_incr_2;
input [15:0] dac_dds_scale_2;
// internal registers
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
reg [15:0] dac_dds_phase_1_1 = 'd0;
reg [15:0] dac_dds_phase_2_0 = 'd0;
reg [15:0] dac_dds_phase_2_1 = 'd0;
reg [15:0] dac_dds_phase_3_0 = 'd0;
reg [15:0] dac_dds_phase_3_1 = 'd0;
reg [15:0] dac_dds_data_0 = 'd0;
reg [15:0] dac_dds_data_1 = 'd0;
reg [15:0] dac_dds_data_2 = 'd0;
reg [15:0] dac_dds_data_3 = 'd0;
// internal signals
wire [15:0] dac_dds_data_0_s;
wire [15:0] dac_dds_data_1_s;
wire [15:0] dac_dds_data_2_s;
wire [15:0] dac_dds_data_3_s;
// dds phase counters
always @(posedge dac_div_clk) begin
if (dac_dds_enable == 1'b0) begin
dac_dds_phase_0_0 <= dac_dds_init_1;
dac_dds_phase_0_1 <= dac_dds_init_2;
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1;
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2;
dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1;
dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2;
dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1;
dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2;
end else begin
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + {dac_dds_incr_1[13:0], 2'd0};
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + {dac_dds_incr_2[13:0], 2'd0};
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + {dac_dds_incr_1[13:0], 2'd0};
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + {dac_dds_incr_2[13:0], 2'd0};
dac_dds_phase_2_0 <= dac_dds_phase_2_0 + {dac_dds_incr_1[13:0], 2'd0};
dac_dds_phase_2_1 <= dac_dds_phase_2_1 + {dac_dds_incr_2[13:0], 2'd0};
dac_dds_phase_3_0 <= dac_dds_phase_3_0 + {dac_dds_incr_1[13:0], 2'd0};
dac_dds_phase_3_1 <= dac_dds_phase_3_1 + {dac_dds_incr_2[13:0], 2'd0};
end
end
// output is either 2's complement or offset binary.
always @(posedge dac_div_clk) begin
if (dac_dds_pattenb == 1'b1) begin
dac_dds_data_0 <= dac_dds_patt_1;
dac_dds_data_1 <= dac_dds_patt_2;
dac_dds_data_2 <= dac_dds_patt_1;
dac_dds_data_3 <= dac_dds_patt_2;
end else begin
dac_dds_data_0 <= dac_dds_data_0_s;
dac_dds_data_1 <= dac_dds_data_1_s;
dac_dds_data_2 <= dac_dds_data_2_s;
dac_dds_data_3 <= dac_dds_data_3_s;
end
end
// dds
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
.dds_scale_0 (dac_dds_scale_1),
.dds_phase_1 (dac_dds_phase_0_1),
.dds_scale_1 (dac_dds_scale_2),
.dds_data (dac_dds_data_0_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
.dds_scale_0 (dac_dds_scale_1),
.dds_phase_1 (dac_dds_phase_1_1),
.dds_scale_1 (dac_dds_scale_2),
.dds_data (dac_dds_data_1_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_2_0),
.dds_scale_0 (dac_dds_scale_1),
.dds_phase_1 (dac_dds_phase_2_1),
.dds_scale_1 (dac_dds_scale_2),
.dds_data (dac_dds_data_2_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_3_0),
.dds_scale_0 (dac_dds_scale_1),
.dds_phase_1 (dac_dds_phase_3_1),
.dds_scale_1 (dac_dds_scale_2),
.dds_data (dac_dds_data_3_s));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9122_if (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
// internal resets and clocks
dac_rst,
dac_clk,
dac_div_clk,
dac_status,
// data interface
dac_frame_i0,
dac_data_i0,
dac_frame_i1,
dac_data_i1,
dac_frame_i2,
dac_data_i2,
dac_frame_i3,
dac_data_i3,
dac_frame_q0,
dac_data_q0,
dac_frame_q1,
dac_data_q1,
dac_frame_q2,
dac_data_q2,
dac_frame_q3,
dac_data_q3,
// mmcm reset
mmcm_rst,
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked);
// parameters
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_IODELAY_GROUP = "dac_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
// internal resets and clocks
input dac_rst;
output dac_clk;
output dac_div_clk;
output dac_status;
// data interface
input dac_frame_i0;
input [15:0] dac_data_i0;
input dac_frame_i1;
input [15:0] dac_data_i1;
input dac_frame_i2;
input [15:0] dac_data_i2;
input dac_frame_i3;
input [15:0] dac_data_i3;
input dac_frame_q0;
input [15:0] dac_data_q0;
input dac_frame_q1;
input [15:0] dac_data_q1;
input dac_frame_q2;
input [15:0] dac_data_q2;
input dac_frame_q3;
input [15:0] dac_data_q3;
// mmcm reset
input mmcm_rst;
// drp interface
input drp_clk;
input drp_rst;
input drp_sel;
input drp_wr;
input [11:0] drp_addr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
output drp_locked;
// internal registers
reg dac_status_m1 = 'd0;
reg dac_status = 'd0;
// dac status
always @(posedge dac_div_clk) begin
if (dac_rst == 1'b1) begin
dac_status_m1 <= 1'd0;
dac_status <= 1'd0;
end else begin
dac_status_m1 <= drp_locked;
dac_status <= dac_status_m1;
end
end
// dac data output serdes(s) & buffers
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DATA_WIDTH(16))
i_serdes_out_data (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (dac_data_i0),
.data_s1 (dac_data_q0),
.data_s2 (dac_data_i1),
.data_s3 (dac_data_q1),
.data_s4 (dac_data_i2),
.data_s5 (dac_data_q2),
.data_s6 (dac_data_i3),
.data_s7 (dac_data_q3),
.data_out_p (dac_data_out_p),
.data_out_n (dac_data_out_n));
// dac frame output serdes & buffer
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DATA_WIDTH(1))
i_serdes_out_frame (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (dac_frame_i0),
.data_s1 (dac_frame_q0),
.data_s2 (dac_frame_i1),
.data_s3 (dac_frame_q1),
.data_s4 (dac_frame_i2),
.data_s5 (dac_frame_q2),
.data_s6 (dac_frame_i3),
.data_s7 (dac_frame_q3),
.data_out_p (dac_frame_out_p),
.data_out_n (dac_frame_out_n));
// dac clock output serdes & buffer
ad_serdes_out #(
.DEVICE_TYPE (PCORE_DEVICE_TYPE),
.SERDES(PCORE_SERDES_DDR_N),
.DATA_WIDTH(1))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),
.data_s3 (1'b0),
.data_s4 (1'b1),
.data_s5 (1'b0),
.data_s6 (1'b1),
.data_s7 (1'b0),
.data_out_p (dac_clk_out_p),
.data_out_n (dac_clk_out_n));
// dac clock input buffers
ad_serdes_clk #(
.SERDES (PCORE_SERDES_DDR_N),
.MMCM (PCORE_MMCM_BUFIO_N),
.MMCM_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (1.667),
.MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (8))
i_serdes_clk (
.mmcm_rst (mmcm_rst),
.clk_in_p (dac_clk_in_p),
.clk_in_n (dac_clk_in_n),
.clk (dac_clk),
.div_clk (dac_div_clk),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9122
adi_ip_files axi_ad9122 [list \
"$ad_hdl_dir/library/common/ad_mul_u16.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
"$ad_hdl_dir/library/common/ad_serdes_out.v" \
"$ad_hdl_dir/library/common/ad_serdes_clk.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"axi_ad9122_dds.v" \
"axi_ad9122_channel.v" \
"axi_ad9122_core.v" \
"axi_ad9122_if.v" \
"axi_ad9122.v" ]
adi_ip_properties axi_ad9122
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9643 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// master-slave interface
adc_start_out,
adc_start_in,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_dwr,
adc_dsync,
adc_ddata,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// debug signals
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// master-slave interface
output adc_start_out;
input adc_start_in;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_dwr;
output adc_dsync;
output [31:0] adc_ddata;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output adc_mon_valid;
output [28:0] adc_mon_data;
// internal registers
reg adc_start_out = 'd0;
reg adc_data_cnt = 'd0;
reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg up_adc_status_pn_err = 'd0;
reg up_adc_status_pn_oos = 'd0;
reg up_adc_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire adc_start_s;
wire [13:0] adc_data_a_s;
wire [13:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire [15:0] adc_dcfilter_data_a_s;
wire [15:0] adc_dcfilter_data_b_s;
wire [15:0] adc_channel_data_a_s;
wire [15:0] adc_channel_data_b_s;
wire adc_enable_a_s;
wire adc_enable_b_s;
wire up_adc_pn_err_a_s;
wire up_adc_pn_oos_a_s;
wire up_adc_or_a_s;
wire up_adc_pn_err_b_s;
wire up_adc_pn_oos_b_s;
wire up_adc_or_b_s;
wire adc_ddr_edgesel_s;
wire adc_pin_mode_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire [31:0] up_adc_channel_rdata_a_s;
wire up_adc_channel_ack_a_s;
wire [31:0] up_adc_channel_rdata_b_s;
wire up_adc_channel_ack_b_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// monitor signals
assign adc_mon_valid = 1'b1;
assign adc_mon_data[13: 0] = adc_data_a_s;
assign adc_mon_data[27:14] = adc_data_b_s;
// dma interface
assign adc_dwr = adc_valid;
assign adc_dsync = 1'b1;
assign adc_ddata = adc_data;
// multiple instances synchronization
assign adc_start_s = (PCORE_ID == 32'd0) ? adc_start_out : adc_start_in;
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_start_out <= 1'b0;
end else begin
adc_start_out <= 1'b1;
end
end
// adc channels - dma interface
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_b_s, adc_enable_a_s})
2'b11: begin // both I and Q
adc_valid <= adc_start_s;
adc_data <= {adc_channel_data_b_s, adc_channel_data_a_s};
end
2'b10: begin // Q only
adc_valid <= adc_data_cnt & adc_start_s;
adc_data <= {adc_channel_data_b_s, adc_data[31:16]};
end
2'b01: begin // I only
adc_valid <= adc_data_cnt & adc_start_s;
adc_data <= {adc_channel_data_a_s, adc_data[31:16]};
end
default: begin // no channels
adc_valid <= adc_start_s;
adc_data <= {2{16'hdead}};
end
endcase
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_status_pn_err <= 'd0;
up_adc_status_pn_oos <= 'd0;
up_adc_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_adc_status_pn_err <= up_adc_pn_err_a_s | up_adc_pn_err_b_s;
up_adc_status_pn_oos <= up_adc_pn_oos_a_s | up_adc_pn_oos_b_s;
up_adc_status_or <= up_adc_or_a_s | up_adc_or_b_s;
up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_a_s | up_adc_channel_rdata_b_s;
up_ack <= up_adc_common_ack_s | up_adc_channel_ack_a_s | up_adc_channel_ack_b_s;
end
end
// channel
axi_ad9643_channel #(
.IQSEL(0),
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dcfilter_data_out (adc_dcfilter_data_a_s),
.adc_dcfilter_data_in (adc_dcfilter_data_b_s),
.adc_iqcor_data (adc_channel_data_a_s),
.adc_enable (adc_enable_a_s),
.up_adc_pn_err (up_adc_pn_err_a_s),
.up_adc_pn_oos (up_adc_pn_oos_a_s),
.up_adc_or (up_adc_or_a_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_a_s),
.up_ack (up_adc_channel_ack_a_s));
// channel
axi_ad9643_channel #(
.IQSEL(1),
.CHID(1),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dcfilter_data_out (adc_dcfilter_data_b_s),
.adc_dcfilter_data_in (adc_dcfilter_data_a_s),
.adc_iqcor_data (adc_channel_data_b_s),
.adc_enable (adc_enable_b_s),
.up_adc_pn_err (up_adc_pn_err_b_s),
.up_adc_pn_oos (up_adc_pn_oos_b_s),
.up_adc_or (up_adc_or_b_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_b_s),
.up_ack (up_adc_channel_ack_b_s));
// main (device interface)
axi_ad9643_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.adc_status (adc_status_s),
.adc_status_pn_err (up_adc_status_pn_err),
.adc_status_pn_oos (up_adc_status_pn_oos),
.adc_status_or (up_adc_status_or),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9643_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dcfilter_data_out,
adc_dcfilter_data_in,
adc_iqcor_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [13:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
input [15:0] adc_dcfilter_data_in;
output [15:0] adc_iqcor_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire [15:0] adc_dfmt_data_s;
wire [15:0] adc_dcfilter_data_i_s;
wire [15:0] adc_dcfilter_data_q_s;
wire adc_iqcor_enb_s;
wire adc_dcfilt_enb_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire adc_pn_type_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire [15:0] adc_iqcor_coeff_1_s;
wire [15:0] adc_iqcor_coeff_2_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// iq correction inputs
assign adc_dcfilter_data_i_s = (IQSEL == 1) ? adc_dcfilter_data_in : adc_dcfilter_data_out;
assign adc_dcfilter_data_q_s = (IQSEL == 1) ? adc_dcfilter_data_out : adc_dcfilter_data_in;
axi_ad9643_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_type (adc_pn_type_s));
generate
if (DP_DISABLE == 1) begin
assign adc_dfmt_data_s = {2'd0, adc_data};
end else begin
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data),
.valid_out (),
.data_out (adc_dfmt_data_s),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (1'b1),
.data (adc_dfmt_data_s),
.valid_out (),
.data_out (adc_dcfilter_data_out),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_iqcor_data = (IQSEL == 1) ? adc_dcfilter_data_q_s : adc_dcfilter_data_i_s;
end else begin
ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor (
.clk (adc_clk),
.valid (1'b1),
.data_i (adc_dcfilter_data_i_s),
.data_q (adc_dcfilter_data_q_s),
.valid_out (),
.data_out (adc_iqcor_data),
.iqcor_enable (adc_iqcor_enb_s),
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (adc_iqcor_enb_s),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_pn_type (adc_pn_type_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
// Alternative is to concatenate sample value and or status for data.
`timescale 1ns/100ps
module axi_ad9643_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status,
// processor control signals
adc_ddr_edgesel,
adc_pin_mode,
// delay control signals
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
localparam PCORE_DEVICE_7SERIES = 0;
localparam PCORE_DEVICE_VIRTEX6 = 1;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [13:0] adc_data_a;
output [13:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// processor control signals
input adc_ddr_edgesel;
input adc_pin_mode;
// delay control signals
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [13:0] adc_data_p = 'd0;
reg [13:0] adc_data_n = 'd0;
reg [13:0] adc_data_n_d = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or_n_d = 'd0;
reg [13:0] adc_data_mux_a = 'd0;
reg [13:0] adc_data_mux_b = 'd0;
reg adc_or_mux_a = 'd0;
reg adc_or_mux_b = 'd0;
reg [13:0] adc_data_a = 'd0;
reg [13:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
reg [14:0] delay_ld = 'd0;
reg delay_ack_t = 'd0;
reg [ 4:0] delay_rdata = 'd0;
// internal signals
wire [ 4:0] delay_rdata_s[14:0];
wire [13:0] adc_data_ibuf_s;
wire [13:0] adc_data_idelay_s;
wire [13:0] adc_data_p_s;
wire [13:0] adc_data_n_s;
wire adc_or_ibuf_s;
wire adc_or_idelay_s;
wire adc_or_p_s;
wire adc_or_n_s;
wire adc_clk_ibuf_s;
// instantiation variables
genvar l_inst;
// The adc data is 14bits ddr, and here it is demuxed to 16bits.
// The samples may be selected to be either positive first, or negative first.
// Two data pin modes are supported- data can either be clock edge muxed (rising or falling edges),
// or within a clock edge, pin muxed (lower 7 bits and upper 7 bits)
always @(posedge adc_clk) begin
adc_status <= 1'b1;
adc_data_p <= adc_data_p_s;
adc_data_n <= adc_data_n_s;
adc_data_n_d <= adc_data_n;
adc_or_p <= adc_or_p_s;
adc_or_n <= adc_or_n_s;
adc_or_n_d <= adc_or_n;
if (adc_ddr_edgesel == 1'b1) begin
adc_data_mux_a <= adc_data_p;
adc_data_mux_b <= adc_data_n;
adc_or_mux_a <= adc_or_p;
adc_or_mux_b <= adc_or_n;
end else begin
adc_data_mux_a <= adc_data_n_d;
adc_data_mux_b <= adc_data_p;
adc_or_mux_a <= adc_or_n_d;
adc_or_mux_b <= adc_or_p;
end
if (adc_pin_mode == 1'b1) begin
adc_data_a <= adc_data_mux_a;
adc_data_b <= adc_data_mux_b;
adc_or_a <= adc_or_mux_a;
adc_or_b <= adc_or_mux_b;
end else begin
adc_data_a <= { adc_data_mux_b[13], adc_data_mux_a[13],
adc_data_mux_b[12], adc_data_mux_a[12],
adc_data_mux_b[11], adc_data_mux_a[11],
adc_data_mux_b[10], adc_data_mux_a[10],
adc_data_mux_b[ 9], adc_data_mux_a[ 9],
adc_data_mux_b[ 8], adc_data_mux_a[ 8],
adc_data_mux_b[ 7], adc_data_mux_a[ 7]};
adc_data_b <= { adc_data_mux_b[ 6], adc_data_mux_a[ 6],
adc_data_mux_b[ 5], adc_data_mux_a[ 5],
adc_data_mux_b[ 4], adc_data_mux_a[ 4],
adc_data_mux_b[ 3], adc_data_mux_a[ 3],
adc_data_mux_b[ 2], adc_data_mux_a[ 2],
adc_data_mux_b[ 1], adc_data_mux_a[ 1],
adc_data_mux_b[ 0], adc_data_mux_a[ 0]};
adc_or_a <= adc_or_mux_a;
adc_or_b <= adc_or_mux_b;
end
end
// The delay control interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no INC/DEC stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h0e: delay_ld <= 15'h4000;
8'h0d: delay_ld <= 15'h2000;
8'h0c: delay_ld <= 15'h1000;
8'h0b: delay_ld <= 15'h0800;
8'h0a: delay_ld <= 15'h0400;
8'h09: delay_ld <= 15'h0200;
8'h08: delay_ld <= 15'h0100;
8'h07: delay_ld <= 15'h0080;
8'h06: delay_ld <= 15'h0040;
8'h05: delay_ld <= 15'h0020;
8'h04: delay_ld <= 15'h0010;
8'h03: delay_ld <= 15'h0008;
8'h02: delay_ld <= 15'h0004;
8'h01: delay_ld <= 15'h0002;
8'h00: delay_ld <= 15'h0001;
default: delay_ld <= 15'h0000;
endcase
end else begin
delay_ld <= 15'h0000;
end
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
case (delay_addr)
8'h0e: delay_rdata <= delay_rdata_s[14];
8'h0d: delay_rdata <= delay_rdata_s[13];
8'h0c: delay_rdata <= delay_rdata_s[12];
8'h0b: delay_rdata <= delay_rdata_s[11];
8'h0a: delay_rdata <= delay_rdata_s[10];
8'h09: delay_rdata <= delay_rdata_s[ 9];
8'h08: delay_rdata <= delay_rdata_s[ 8];
8'h07: delay_rdata <= delay_rdata_s[ 7];
8'h06: delay_rdata <= delay_rdata_s[ 6];
8'h05: delay_rdata <= delay_rdata_s[ 5];
8'h04: delay_rdata <= delay_rdata_s[ 4];
8'h03: delay_rdata <= delay_rdata_s[ 3];
8'h02: delay_rdata <= delay_rdata_s[ 2];
8'h01: delay_rdata <= delay_rdata_s[ 1];
8'h00: delay_rdata <= delay_rdata_s[ 0];
default: delay_rdata <= 5'd0;
endcase
end
// The data interface, data signals goes through a LVDS input buffer, then
// a delay element (1/32th of a 200MHz clock) and finally an input DDR demux.
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
IBUFDS i_data_ibuf (
.I (adc_data_in_p[l_inst]),
.IB (adc_data_in_n[l_inst]),
.O (adc_data_ibuf_s[l_inst]));
if (PCORE_DEVICE_TYPE == PCORE_DEVICE_VIRTEX6) begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_data_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.IDATAIN (adc_data_ibuf_s[l_inst]),
.DATAOUT (adc_data_idelay_s[l_inst]),
.RST (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
end else begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_data_ibuf_s[l_inst]),
.DATAOUT (adc_data_idelay_s[l_inst]),
.LD (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
end
IDDR #(
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.SRTYPE ("ASYNC"))
i_data_ddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (adc_clk),
.D (adc_data_idelay_s[l_inst]),
.Q1 (adc_data_p_s[l_inst]),
.Q2 (adc_data_n_s[l_inst]));
end
endgenerate
// The over-range interface, it follows a similar path as the data signals.
IBUFDS i_or_ibuf (
.I (adc_or_in_p),
.IB (adc_or_in_n),
.O (adc_or_ibuf_s));
generate
if (PCORE_DEVICE_TYPE == PCORE_DEVICE_VIRTEX6) begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_or_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.IDATAIN (adc_or_ibuf_s),
.DATAOUT (adc_or_idelay_s),
.RST (delay_ld[14]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[14]));
end else begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_or_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_or_ibuf_s),
.DATAOUT (adc_or_idelay_s),
.LD (delay_ld[14]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[14]));
end
endgenerate
IDDR #(
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.SRTYPE ("ASYNC"))
i_or_ddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (adc_clk),
.D (adc_or_idelay_s),
.Q1 (adc_or_p_s),
.Q2 (adc_or_n_s));
// The clock path is a simple clock buffer after a LVDS input buffer.
// It is possible for this logic to be replaced with a OSERDES based data capture.
// The reason for such a simple interface here is because this reference design
// is used for various boards (native fmc and/or evaluation boards). The pinouts
// of the FPGA - ADC interface is probably do not allow a OSERDES placement.
IBUFGDS i_clk_ibuf (
.I (adc_clk_in_p),
.IB (adc_clk_in_n),
.O (adc_clk_ibuf_s));
generate
if (PCORE_DEVICE_TYPE == PCORE_DEVICE_VIRTEX6) begin
BUFR #(.BUFR_DIVIDE ("BYPASS")) i_clk_gbuf (
.CLR (1'b0),
.CE (1'b1),
.I (adc_clk_ibuf_s),
.O (adc_clk));
end else begin
BUFG i_clk_gbuf (
.I (adc_clk_ibuf_s),
.O (adc_clk));
end
endgenerate
// The delay controller. Refer to Xilinx doc. for details.
// The GROUP directive controls which delay elements this is associated with.
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9643
adi_ip_files axi_ad9643 [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_mul_u16.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9643_pnmon.v" \
"axi_ad9643_channel.v" \
"axi_ad9643_if.v" \
"axi_ad9643.v" ]
adi_ip_properties axi_ad9643
ipx::save_core [ipx::current_core]

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library/axi_ad9643/axi_ad9643_pnmon.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9643_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pn_type);
// adc interface
input adc_clk;
input [13:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input adc_pn_type;
// internal registers
reg adc_pn_en = 'd0;
reg [13:0] adc_data_in = 'd0;
reg [13:0] adc_data_d = 'd0;
reg [29:0] adc_pn_data = 'd0;
reg adc_pn_en_d = 'd0;
reg adc_pn_match_d_1 = 'd0;
reg adc_pn_match_d_0 = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
// internal signals
wire [29:0] adc_pn_data_in_s;
wire adc_pn_match_d_1_s;
wire adc_pn_match_d_0_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire [29:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// PN23 function
function [29:0] pn23;
input [29:0] din;
reg [29:0] dout;
begin
dout[29] = din[22] ^ din[17];
dout[28] = din[21] ^ din[16];
dout[27] = din[20] ^ din[15];
dout[26] = din[19] ^ din[14];
dout[25] = din[18] ^ din[13];
dout[24] = din[17] ^ din[12];
dout[23] = din[16] ^ din[11];
dout[22] = din[15] ^ din[10];
dout[21] = din[14] ^ din[ 9];
dout[20] = din[13] ^ din[ 8];
dout[19] = din[12] ^ din[ 7];
dout[18] = din[11] ^ din[ 6];
dout[17] = din[10] ^ din[ 5];
dout[16] = din[ 9] ^ din[ 4];
dout[15] = din[ 8] ^ din[ 3];
dout[14] = din[ 7] ^ din[ 2];
dout[13] = din[ 6] ^ din[ 1];
dout[12] = din[ 5] ^ din[ 0];
dout[11] = din[ 4] ^ din[22] ^ din[17];
dout[10] = din[ 3] ^ din[21] ^ din[16];
dout[ 9] = din[ 2] ^ din[20] ^ din[15];
dout[ 8] = din[ 1] ^ din[19] ^ din[14];
dout[ 7] = din[ 0] ^ din[18] ^ din[13];
dout[ 6] = din[22] ^ din[12];
dout[ 5] = din[21] ^ din[11];
dout[ 4] = din[20] ^ din[10];
dout[ 3] = din[19] ^ din[ 9];
dout[ 2] = din[18] ^ din[ 8];
dout[ 1] = din[17] ^ din[ 7];
dout[ 0] = din[16] ^ din[ 6];
pn23 = dout;
end
endfunction
// PN9 function
function [29:0] pn9;
input [29:0] din;
reg [29:0] dout;
begin
dout[29] = din[ 8] ^ din[ 4];
dout[28] = din[ 7] ^ din[ 3];
dout[27] = din[ 6] ^ din[ 2];
dout[26] = din[ 5] ^ din[ 1];
dout[25] = din[ 4] ^ din[ 0];
dout[24] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[23] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[22] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[21] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[20] = din[ 8] ^ din[ 0];
dout[19] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[18] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[17] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[16] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[15] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[13] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[12] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[11] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[10] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 9] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 8] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 7] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 6] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 5] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 4] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 3] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 2] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 1] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 0] = din[ 6] ^ din[ 8] ^ din[ 0];
pn9 = dout;
end
endfunction
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// the next sequence is generated from the incoming data.
// if 16 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// the next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_in_s[29:15] = {adc_pn_data[29], adc_data_d};
assign adc_pn_data_in_s[14:0] = {adc_pn_data[14], adc_data_in};
assign adc_pn_match_d_1_s = (adc_pn_data_in_s[28:15] == adc_pn_data[28:15]) ? 1'b1 : 1'b0;
assign adc_pn_match_d_0_s = (adc_pn_data_in_s[13:0] == adc_pn_data[13:0]) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 30'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn running sequence
always @(posedge adc_clk) begin
adc_pn_en <= ~adc_pn_en;
adc_data_in <= {~adc_data[13], adc_data[12:0]};
adc_data_d <= adc_data_in;
if (adc_pn_en == 1'b1) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
end
end
end
// pn oos and counters (64 to clear and set).
always @(posedge adc_clk) begin
adc_pn_en_d <= adc_pn_en;
adc_pn_match_d_1 <= adc_pn_match_d_1_s;
adc_pn_match_d_0 <= adc_pn_match_d_0_s;
adc_pn_match_z <= adc_pn_match_z_s;
adc_pn_err <= adc_pn_en_d & adc_pn_err_s;
if (adc_pn_en_d == 1'b1) begin
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************