From a773cc4992b81f5eaeb893e6c707ad724e9208de Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 1 Sep 2014 15:18:39 +0300 Subject: [PATCH] usdrx1: updated project ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame --- library/common/ad_jesd_align.v | 15 ++-- projects/usdrx1/common/usdrx1_bd.tcl | 82 +++++++++++++-------- projects/usdrx1/common/usdrx1_spi.v | 2 +- projects/usdrx1/zc706/system_constr.xdc | 4 +- projects/usdrx1/zc706/system_top.v | 97 +++++++++++++------------ 5 files changed, 115 insertions(+), 85 deletions(-) diff --git a/library/common/ad_jesd_align.v b/library/common/ad_jesd_align.v index 08b90115e..2d571923e 100644 --- a/library/common/ad_jesd_align.v +++ b/library/common/ad_jesd_align.v @@ -59,19 +59,24 @@ module ad_jesd_align ( // internal registers reg [31:0] rx_ip_data_d = 'd0; + reg [ 3:0] rx_sof_d = 'd0; reg [31:0] rx_data = 'd0; // dword may contain more than one frame per clock always @(posedge rx_clk) begin - rx_ip_data_d <= rx_ip_data; - if (rx_sof[0] == 1'b1) begin + rx_ip_data_d <= rx_ip_data; + if (rx_sof != 4'h0) + begin + rx_sof_d <= rx_sof; + end + if (rx_sof_d[0] == 1'b1) begin rx_data <= rx_ip_data; - end else if (rx_sof[1] == 1'b1) begin + end else if (rx_sof_d[1] == 1'b1) begin rx_data <= {rx_ip_data[ 7:0], rx_ip_data_d[31: 8]}; - end else if (rx_sof[2] == 1'b1) begin + end else if (rx_sof_d[2] == 1'b1) begin rx_data <= {rx_ip_data[15:0], rx_ip_data_d[31:16]}; - end else if (rx_sof[3] == 1'b1) begin + end else if (rx_sof_d[3] == 1'b1) begin rx_data <= {rx_ip_data[23:0], rx_ip_data_d[31:24]}; end else begin rx_data <= 32'd0; diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 9a416328f..d5afeed87 100755 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -15,32 +15,31 @@ set rx_sysref [create_bd_port -dir O rx_sysref] set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] -set mlo_clk [create_bd_port -dir O mlo_clk] +#set mlo_clk [create_bd_port -dir O mlo_clk] set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data] set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0] set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1] set gt_rx_data_2 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_2] set gt_rx_data_3 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_3] -set adc_dwr_0 [create_bd_port -dir O adc_dwr_0] -set adc_dwr_1 [create_bd_port -dir O adc_dwr_1] -set adc_dwr_2 [create_bd_port -dir O adc_dwr_2] -set adc_dwr_3 [create_bd_port -dir O adc_dwr_3] -set adc_dsync_0 [create_bd_port -dir O adc_dsync_0] -set adc_dsync_1 [create_bd_port -dir O adc_dsync_1] -set adc_dsync_2 [create_bd_port -dir O adc_dsync_2] -set adc_dsync_3 [create_bd_port -dir O adc_dsync_3] -set adc_ddata_0 [create_bd_port -dir O -from 127 -to 0 adc_ddata_0] -set adc_ddata_1 [create_bd_port -dir O -from 127 -to 0 adc_ddata_1] -set adc_ddata_2 [create_bd_port -dir O -from 127 -to 0 adc_ddata_2] -set adc_ddata_3 [create_bd_port -dir O -from 127 -to 0 adc_ddata_3] +set adc_data_0 [create_bd_port -dir O -from 127 -to 0 adc_data_0] +set adc_data_1 [create_bd_port -dir O -from 127 -to 0 adc_data_1] +set adc_data_2 [create_bd_port -dir O -from 127 -to 0 adc_data_2] +set adc_data_3 [create_bd_port -dir O -from 127 -to 0 adc_data_3] +set adc_valid_0 [create_bd_port -dir O -from 7 -to 0 adc_valid_0] +set adc_valid_1 [create_bd_port -dir O -from 7 -to 0 adc_valid_1] +set adc_valid_2 [create_bd_port -dir O -from 7 -to 0 adc_valid_2] +set adc_valid_3 [create_bd_port -dir O -from 7 -to 0 adc_valid_3] +set adc_enable_0 [create_bd_port -dir O -from 7 -to 0 adc_enable_0] +set adc_enable_1 [create_bd_port -dir O -from 7 -to 0 adc_enable_1] +set adc_enable_2 [create_bd_port -dir O -from 7 -to 0 adc_enable_2] +set adc_enable_3 [create_bd_port -dir O -from 7 -to 0 adc_enable_3] set adc_dovf_0 [create_bd_port -dir I adc_dovf_0] set adc_dovf_1 [create_bd_port -dir I adc_dovf_1] set adc_dovf_2 [create_bd_port -dir I adc_dovf_2] set adc_dovf_3 [create_bd_port -dir I adc_dovf_3] -set adc_dwr [create_bd_port -dir I adc_dwr] -set adc_dsync [create_bd_port -dir I adc_dsync] -set adc_ddata [create_bd_port -dir I -from 511 -to 0 adc_ddata] +set adc_data [create_bd_port -dir I -from 511 -to 0 adc_data] +set adc_wr_en [create_bd_port -dir I adc_wr_en] set adc_dovf [create_bd_port -dir O adc_dovf] # adc peripherals @@ -163,25 +162,24 @@ connect_bd_net -net axi_usdrx1_gt_rx_data_1 [get_bd_pins axi_ad9671_core connect_bd_net -net axi_usdrx1_gt_rx_data_2 [get_bd_pins axi_ad9671_core_2/rx_data] [get_bd_ports gt_rx_data_2] connect_bd_net -net axi_usdrx1_gt_rx_data_3 [get_bd_pins axi_ad9671_core_3/rx_data] [get_bd_ports gt_rx_data_3] connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core_0/adc_clk] [get_bd_pins axi_usdrx1_dma/fifo_wr_clk] -connect_bd_net -net axi_ad9671_core_adc_dwr_0 [get_bd_pins axi_ad9671_core_0/adc_dwr] [get_bd_ports adc_dwr_0] -connect_bd_net -net axi_ad9671_core_adc_dwr_1 [get_bd_pins axi_ad9671_core_1/adc_dwr] [get_bd_ports adc_dwr_1] -connect_bd_net -net axi_ad9671_core_adc_dwr_2 [get_bd_pins axi_ad9671_core_2/adc_dwr] [get_bd_ports adc_dwr_2] -connect_bd_net -net axi_ad9671_core_adc_dwr_3 [get_bd_pins axi_ad9671_core_3/adc_dwr] [get_bd_ports adc_dwr_3] -connect_bd_net -net axi_ad9671_core_adc_dsync_0 [get_bd_pins axi_ad9671_core_0/adc_dsync] [get_bd_ports adc_dsync_0] -connect_bd_net -net axi_ad9671_core_adc_dsync_1 [get_bd_pins axi_ad9671_core_1/adc_dsync] [get_bd_ports adc_dsync_1] -connect_bd_net -net axi_ad9671_core_adc_dsync_2 [get_bd_pins axi_ad9671_core_2/adc_dsync] [get_bd_ports adc_dsync_2] -connect_bd_net -net axi_ad9671_core_adc_dsync_3 [get_bd_pins axi_ad9671_core_3/adc_dsync] [get_bd_ports adc_dsync_3] -connect_bd_net -net axi_ad9671_core_adc_ddata_0 [get_bd_pins axi_ad9671_core_0/adc_ddata] [get_bd_ports adc_ddata_0] -connect_bd_net -net axi_ad9671_core_adc_ddata_1 [get_bd_pins axi_ad9671_core_1/adc_ddata] [get_bd_ports adc_ddata_1] -connect_bd_net -net axi_ad9671_core_adc_ddata_2 [get_bd_pins axi_ad9671_core_2/adc_ddata] [get_bd_ports adc_ddata_2] -connect_bd_net -net axi_ad9671_core_adc_ddata_3 [get_bd_pins axi_ad9671_core_3/adc_ddata] [get_bd_ports adc_ddata_3] +connect_bd_net -net axi_ad9671_core_adc_data_0 [get_bd_pins axi_ad9671_core_0/adc_data] [get_bd_ports adc_data_0] +connect_bd_net -net axi_ad9671_core_adc_data_1 [get_bd_pins axi_ad9671_core_1/adc_data] [get_bd_ports adc_data_1] +connect_bd_net -net axi_ad9671_core_adc_data_2 [get_bd_pins axi_ad9671_core_2/adc_data] [get_bd_ports adc_data_2] +connect_bd_net -net axi_ad9671_core_adc_data_3 [get_bd_pins axi_ad9671_core_3/adc_data] [get_bd_ports adc_data_3] +connect_bd_net -net axi_ad9671_core_adc_valid_0 [get_bd_pins axi_ad9671_core_0/adc_valid] [get_bd_ports adc_valid_0] +connect_bd_net -net axi_ad9671_core_adc_valid_1 [get_bd_pins axi_ad9671_core_1/adc_valid] [get_bd_ports adc_valid_1] +connect_bd_net -net axi_ad9671_core_adc_valid_2 [get_bd_pins axi_ad9671_core_2/adc_valid] [get_bd_ports adc_valid_2] +connect_bd_net -net axi_ad9671_core_adc_valid_3 [get_bd_pins axi_ad9671_core_3/adc_valid] [get_bd_ports adc_valid_3] +connect_bd_net -net axi_ad9671_core_adc_enable_0 [get_bd_pins axi_ad9671_core_0/adc_enable] [get_bd_ports adc_enable_0] +connect_bd_net -net axi_ad9671_core_adc_enable_1 [get_bd_pins axi_ad9671_core_1/adc_enable] [get_bd_ports adc_enable_1] +connect_bd_net -net axi_ad9671_core_adc_enable_2 [get_bd_pins axi_ad9671_core_2/adc_enable] [get_bd_ports adc_enable_2] +connect_bd_net -net axi_ad9671_core_adc_enable_3 [get_bd_pins axi_ad9671_core_3/adc_enable] [get_bd_ports adc_enable_3] connect_bd_net -net axi_ad9671_core_adc_dovf_0 [get_bd_pins axi_ad9671_core_0/adc_dovf] [get_bd_ports adc_dovf_0] connect_bd_net -net axi_ad9671_core_adc_dovf_1 [get_bd_pins axi_ad9671_core_1/adc_dovf] [get_bd_ports adc_dovf_1] connect_bd_net -net axi_ad9671_core_adc_dovf_2 [get_bd_pins axi_ad9671_core_2/adc_dovf] [get_bd_ports adc_dovf_2] connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core_3/adc_dovf] [get_bd_ports adc_dovf_3] -connect_bd_net -net axi_ad9671_dma_adc_dwr [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_dwr] -connect_bd_net -net axi_ad9671_dma_adc_dsync [get_bd_pins axi_usdrx1_dma/fifo_wr_sync] [get_bd_ports adc_dsync] -connect_bd_net -net axi_ad9671_dma_adc_ddata [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_ddata] +connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en] +connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data] connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf] connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] @@ -269,6 +267,7 @@ set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jes set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_jesd_rx_mon connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins axi_usdrx1_gt/rx_mon_data] connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins axi_usdrx1_gt/rx_mon_trigger] @@ -276,6 +275,27 @@ connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins ila_jesd_rx_mon connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] +set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_ad9671] +set_property -dict [list CONFIG.C_NUM_OF_PROBES {8}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE1_WIDTH {8}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE3_WIDTH {8}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE4_WIDTH {128}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE5_WIDTH {8}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE6_WIDTH {128}] $ila_ad9671 +set_property -dict [list CONFIG.C_PROBE7_WIDTH {8}] $ila_ad9671 +set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_ad9671 + +connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins ila_ad9671/CLK] +connect_bd_net -net axi_ad9671_core_adc_data_0 [get_bd_pins ila_ad9671/PROBE0] +connect_bd_net -net axi_ad9671_core_adc_valid_0 [get_bd_pins ila_ad9671/PROBE1] +connect_bd_net -net axi_ad9671_core_adc_data_1 [get_bd_pins ila_ad9671/PROBE2] +connect_bd_net -net axi_ad9671_core_adc_valid_1 [get_bd_pins ila_ad9671/PROBE3] +connect_bd_net -net axi_ad9671_core_adc_data_2 [get_bd_pins ila_ad9671/PROBE4] +connect_bd_net -net axi_ad9671_core_adc_valid_2 [get_bd_pins ila_ad9671/PROBE5] +connect_bd_net -net axi_ad9671_core_adc_data_3 [get_bd_pins ila_ad9671/PROBE6] +connect_bd_net -net axi_ad9671_core_adc_valid_3 [get_bd_pins ila_ad9671/PROBE7] # address map create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0 diff --git a/projects/usdrx1/common/usdrx1_spi.v b/projects/usdrx1/common/usdrx1_spi.v index a9d293703..050f180f3 100755 --- a/projects/usdrx1/common/usdrx1_spi.v +++ b/projects/usdrx1/common/usdrx1_spi.v @@ -63,7 +63,7 @@ module usdrx1_spi ( inout spi_fout_sdio; inout spi_afe_sdio; - input spi_clk_sdio; + inout spi_clk_sdio; // internal registers diff --git a/projects/usdrx1/zc706/system_constr.xdc b/projects/usdrx1/zc706/system_constr.xdc index 97392c994..e8af4bfd6 100755 --- a/projects/usdrx1/zc706/system_constr.xdc +++ b/projects/usdrx1/zc706/system_constr.xdc @@ -24,8 +24,8 @@ set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25} [get_ports rx_sysref set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D24 FMC_HPC_LA23_N set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D26 FMC_HPC_LA26_P set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D27 FMC_HPC_LA26_N -set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports afe_mlo_p] ; ## D20 FMC_HPC_LA17_CC_P -set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports afe_mlo_n] ; ## D21 FMC_HPC_LA17_CC_N +#set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports afe_mlo_p] ; ## D20 FMC_HPC_LA17_CC_P +#set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports afe_mlo_n] ; ## D21 FMC_HPC_LA17_CC_N set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports afe_rst_p] ; ## G27 FMC_HPC_LA25_P set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports afe_rst_n] ; ## G28 FMC_HPC_LA25_N set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25} [get_ports afe_trig_p] ; ## H28 FMC_HPC_LA24_P diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index b581c8a3d..4a5d6b3e6 100755 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -101,8 +101,8 @@ module system_top ( spi_clk_clk, spi_clk_sdio, - afe_mlo_p, - afe_mlo_n, + // afe_mlo_p, + // afe_mlo_n, afe_rst_p, afe_rst_n, afe_trig_p, @@ -181,8 +181,8 @@ module system_top ( output spi_clk_clk; inout spi_clk_sdio; - output afe_mlo_p; - output afe_mlo_n; + // output afe_mlo_p; + //output afe_mlo_n; output afe_rst_p; output afe_rst_n; output afe_trig_p; @@ -210,26 +210,25 @@ module system_top ( wire rx_ref_clk; wire rx_sysref; wire rx_sync; - wire [511:0] adc_ddata; - wire [127:0] adc_ddata_0; - wire [127:0] adc_ddata_1; - wire [127:0] adc_ddata_2; - wire [127:0] adc_ddata_3; + wire [511:0] adc_data; + wire [127:0] adc_data_0; + wire [127:0] adc_data_1; + wire [127:0] adc_data_2; + wire [127:0] adc_data_3; + wire adc_valid; + wire [ 7:0] adc_valid_0; + wire [ 7:0] adc_valid_1; + wire [ 7:0] adc_valid_2; + wire [ 7:0] adc_valid_3; + wire [ 7:0] adc_enable_0; + wire [ 7:0] adc_enable_1; + wire [ 7:0] adc_enable_2; + wire [ 7:0] adc_enable_3; wire adc_dovf; wire adc_dovf_0; wire adc_dovf_1; wire adc_dovf_2; wire adc_dovf_3; - wire adc_dsync; - wire adc_dsync_0; - wire adc_dsync_1; - wire adc_dsync_2; - wire adc_dsync_3; - wire adc_dwr; - wire adc_dwr_0; - wire adc_dwr_1; - wire adc_dwr_2; - wire adc_dwr_3; wire [255:0] gt_rx_data; wire [63:0] gt_rx_data_0; wire [63:0] gt_rx_data_1; @@ -240,14 +239,16 @@ module system_top ( wire [43:0] gpio_t; wire afe_mlo; + reg afe_trig_d; + reg afe_trig_s; // spi assignments - assign spi_fout_enb_clk = spi_csn[10:10]; - assign spi_fout_enb_mlo = spi_csn[ 9: 9]; - assign spi_fout_enb_rst = spi_csn[ 8: 8]; - assign spi_fout_enb_sync = spi_csn[ 7: 7]; - assign spi_fout_enb_sysref = spi_csn[ 6: 6]; - assign spi_fout_enb_trig = spi_csn[ 5: 5]; + assign spi_fout_enb_clk = ~spi_csn[10:10]; + assign spi_fout_enb_mlo = ~spi_csn[ 9: 9]; + assign spi_fout_enb_rst = ~spi_csn[ 8: 8]; + assign spi_fout_enb_sync = ~spi_csn[ 7: 7]; + assign spi_fout_enb_sysref = ~spi_csn[ 6: 6]; + assign spi_fout_enb_trig = ~spi_csn[ 5: 5]; assign spi_afe_csn = spi_csn[ 4: 1]; assign spi_clk_csn = spi_csn[ 0: 0]; assign spi_fout_clk = spi_clk; @@ -272,9 +273,8 @@ module system_top ( assign gt_rx_data_1 = gt_rx_data[127: 64]; assign gt_rx_data_0 = gt_rx_data[ 63: 0]; - assign adc_dwr = adc_dwr_3 | adc_dwr_2 | adc_dwr_1 | adc_dwr_0; - assign adc_dsync = adc_dsync_3 | adc_dsync_2 | adc_dsync_1 | adc_dsync_0; - assign adc_ddata = {adc_ddata_3, adc_ddata_2, adc_ddata_1, adc_ddata_0}; + assign adc_data = {adc_data_3, adc_data_2, adc_data_1, adc_data_0}; + assign adc_valid = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ; assign adc_dovf_0 = adc_dovf; assign adc_dovf_1 = adc_dovf; assign adc_dovf_2 = adc_dovf; @@ -301,10 +301,10 @@ module system_top ( // gpio/control interface - OBUFDS i_obufds_mlo ( + /* OBUFDS i_obufds_mlo ( .I (afe_mlo), .O (afe_mlo_p), - .OB (afe_mlo_n)); + .OB (afe_mlo_n));*/ IOBUF i_iobuf_gpio_prc_sdo_q ( .I (gpio_o[43]), @@ -366,6 +366,12 @@ module system_top ( .T (gpio_t[34]), .IO (afe_pdn)); + // synchronize the gpio with ref_clk + /* always @(negedge rx_ref_clk) + begin + afe_trig_d <= gpio_o[33]; + afe_trig_s <= afe_trig_d; + end*/ OBUFDS i_obufds_gpio_afe_trig ( .I (gpio_o[33]), .O (afe_trig_p), @@ -425,26 +431,25 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), - .adc_ddata (adc_ddata), - .adc_ddata_0 (adc_ddata_0), - .adc_ddata_1 (adc_ddata_1), - .adc_ddata_2 (adc_ddata_2), - .adc_ddata_3 (adc_ddata_3), + .adc_data (adc_data), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_data_2 (adc_data_2), + .adc_data_3 (adc_data_3), + .adc_wr_en(adc_valid), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .adc_valid_2 (adc_valid_2), + .adc_valid_3 (adc_valid_3), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), + .adc_enable_2 (adc_enable_2), + .adc_enable_3 (adc_enable_3), .adc_dovf (adc_dovf), .adc_dovf_0 (adc_dovf_0), .adc_dovf_1 (adc_dovf_1), .adc_dovf_2 (adc_dovf_2), .adc_dovf_3 (adc_dovf_3), - .adc_dsync (adc_dsync), - .adc_dsync_0 (adc_dsync_0), - .adc_dsync_1 (adc_dsync_1), - .adc_dsync_2 (adc_dsync_2), - .adc_dsync_3 (adc_dsync_3), - .adc_dwr (adc_dwr), - .adc_dwr_0 (adc_dwr_0), - .adc_dwr_1 (adc_dwr_1), - .adc_dwr_2 (adc_dwr_2), - .adc_dwr_3 (adc_dwr_3), .gt_rx_data (gt_rx_data), .gt_rx_data_0 (gt_rx_data_0), .gt_rx_data_1 (gt_rx_data_1), @@ -457,7 +462,7 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .mlo_clk (afe_mlo), + // .mlo_clk (afe_mlo), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk),