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axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core

main
Adrian Costina 2015-04-28 15:04:18 +03:00
parent 3fdda617a4
commit a7a2d194e9
2 changed files with 15 additions and 6 deletions
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7
library/axi_jesd_gt/axi_jesd_gt.v
View File

@ -418,9 +418,6 @@ module axi_jesd_gt (
assign tx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_rst_done_s};
assign tx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_pll_locked_s};
assign rx_rst_done = | rx_rst_done_s;
assign tx_rst_done = | tx_rst_done_s;
assign drp_rdata_s = drp_rdata_gt_s[15] | drp_rdata_gt_s[14] |
drp_rdata_gt_s[13] | drp_rdata_gt_s[12] |
drp_rdata_gt_s[11] | drp_rdata_gt_s[10] |
@ -746,7 +743,7 @@ module axi_jesd_gt (
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_s),
.up_tx_out_clk_sel (up_tx_out_clk_sel_s),
.rx_clk (rx_clk),
.rx_rst (rx_rst),
.jesd_rx_rst (rx_rst),
.rx_ext_sysref (rx_ext_sysref),
.rx_sysref (rx_sysref),
.rx_ip_sync (rx_ip_sync),
@ -754,6 +751,7 @@ module axi_jesd_gt (
.rx_rst_done (rx_rst_done_extn_s[7:0]),
.rx_pll_locked (rx_pll_locked_extn_s[7:0]),
.rx_error (1'd0),
.rx_rst_done_up (rx_rst_done),
.tx_clk (tx_clk),
.tx_rst (tx_rst),
.tx_ext_sysref (tx_ext_sysref),
@ -763,6 +761,7 @@ module axi_jesd_gt (
.tx_rst_done (tx_rst_done_extn_s[7:0]),
.tx_pll_locked (tx_pll_locked_extn_s[7:0]),
.tx_error (1'd0),
.tx_rst_done_up (tx_rst_done),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),

14
library/common/up_gt.v
View File

@ -56,7 +56,7 @@ module up_gt (
// receive interface
rx_clk,
rx_rst,
jesd_rx_rst,
rx_ext_sysref,
rx_sysref,
rx_ip_sync,
@ -64,6 +64,7 @@ module up_gt (
rx_rst_done,
rx_pll_locked,
rx_error,
rx_rst_done_up,
// transmit interface
@ -76,6 +77,7 @@ module up_gt (
tx_rst_done,
tx_pll_locked,
tx_error,
tx_rst_done_up,
// drp interface
@ -158,7 +160,7 @@ module up_gt (
// receive interface
input rx_clk;
output rx_rst;
output jesd_rx_rst;
input rx_ext_sysref;
output rx_sysref;
input rx_ip_sync;
@ -166,6 +168,7 @@ module up_gt (
input [ 7:0] rx_rst_done;
input [ 7:0] rx_pll_locked;
input rx_error;
output rx_rst_done_up;
// transmit interface
@ -178,6 +181,7 @@ module up_gt (
input [ 7:0] tx_rst_done;
input [ 7:0] tx_pll_locked;
input tx_error;
output tx_rst_done_up;
// drp interface
@ -382,6 +386,11 @@ module up_gt (
assign up_rx_preset_s = ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_resetn & up_rx_pll_locked_s & up_rx_rst_done_s);
assign up_tx_preset_s = ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_resetn & up_tx_pll_locked_s & up_tx_rst_done_s);
// up clock domain reset done
assign rx_rst_done_up = up_rx_rst_done_s;
assign tx_rst_done_up = up_tx_rst_done_s;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
@ -604,6 +613,7 @@ module up_gt (
ad_rst i_gt_rx_rst_reg (.preset(up_gt_rx_preset_s), .clk(drp_clk), .rst(gt_rx_rst));
ad_rst i_gt_tx_rst_reg (.preset(up_gt_tx_preset_s), .clk(drp_clk), .rst(gt_tx_rst));
ad_rst i_rx_rst_reg (.preset(up_rx_preset_s), .clk(rx_clk), .rst(rx_rst));
ad_rst i_j_rx_rst_reg (.preset(up_rx_preset_s), .clk(up_clk), .rst(jesd_rx_rst));
ad_rst i_tx_rst_reg (.preset(up_tx_preset_s), .clk(tx_clk), .rst(tx_rst));
// reset done & pll locked