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scripts/adi_ip: Update the adi_ip_properties process 

- Add a process, which automaticaly infer AXI memory mapped
interfaces (adi_ip_infer_mm_interfaces)
  - Add missign line breaks to the 'set_propery supported_families'
command
  - Fix the deletion of pre-infered memory maps
main
Istvan Csomortani 2017-01-19 14:57:54 +02:00
parent f003b5b35a
commit a7bd4e6e82
1 changed files with 46 additions and 37 deletions
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81
library/scripts/adi_ip.tcl
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@ -126,6 +126,12 @@ proc adi_ip_infer_streaming_interfaces {ip_name} {
} }
proc adi_ip_infer_mm_interfaces {ip_name} {
ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
}
proc adi_ip_properties_lite {ip_name} { proc adi_ip_properties_lite {ip_name} {
ipx::package_project -root_dir . \ ipx::package_project -root_dir . \
@ -137,45 +143,48 @@ proc adi_ip_properties_lite {ip_name} {
set_property company_url {www.analog.com} [ipx::current_core] set_property company_url {www.analog.com} [ipx::current_core]
set_property supported_families {\ set_property supported_families {\
virtex7 Production virtex7 Production \
qvirtex7 Production qvirtex7 Production \
kintex7 Production kintex7 Production \
kintex7l Production kintex7l Production \
qkintex7 Production qkintex7 Production \
qkintex7l Production qkintex7l Production \
artix7 Production artix7 Production \
artix7l Production artix7l Production \
aartix7 Production aartix7 Production \
qartix7 Production qartix7 Production \
zynq Production zynq Production \
qzynq Production qzynq Production \
azynq Production azynq Production \
virtexu Production virtexu Production \
kintexuplus Production kintexuplus Production \
zynquplus Production zynquplus Production \
kintexu Production kintexu Production \
virtex7 Beta virtex7 Beta \
qvirtex7 Beta qvirtex7 Beta \
kintex7 Beta kintex7 Beta \
kintex7l Beta kintex7l Beta \
qkintex7 Beta qkintex7 Beta \
qkintex7l Beta qkintex7l Beta \
artix7 Beta artix7 Beta \
artix7l Beta artix7l Beta \
aartix7 Beta aartix7 Beta \
qartix7 Beta qartix7 Beta \
zynq Beta zynq Beta \
qzynq Beta qzynq Beta \
azynq Beta azynq Beta \
virtexu Beta virtexu Beta \
virtexuplus Beta virtexuplus Beta \
kintexuplus Beta kintexuplus Beta \
zynquplus Beta zynquplus Beta \
kintexu Beta}\ kintexu Beta}\
[ipx::current_core] [ipx::current_core]
ipx::remove_all_bus_interface -quiet [ipx::current_core] ipx::remove_all_bus_interface [ipx::current_core]
ipx::remove_all_address_block -quiet [ipx::get_memory_maps * -of_objects [ipx::current_core]] set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
foreach map $memory_maps {
ipx::remove_memory_map [lindex $map 2] [ipx::current_core ]
}
} }
proc adi_set_ports_dependency {port_prefix dependency} { proc adi_set_ports_dependency {port_prefix dependency} {