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Motor control cores updated for motcon2

main
Adrian Costina 2015-02-20 16:12:11 +02:00
parent 277161c143
commit a81bc7e463
13 changed files with 252 additions and 532 deletions
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42
library/axi_mc_controller/axi_mc_controller.v
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@ -47,7 +47,6 @@ module axi_mc_controller
// physical interface
input fmc_m1_fault_i,
output fmc_m1_en_o,
output pwm_ah_o,
output pwm_al_o,
@ -55,7 +54,7 @@ module axi_mc_controller
output pwm_bl_o,
output pwm_ch_o,
output pwm_cl_o,
output [7:0] gpo_o,
output [3:0] gpo_o,
// controller connections
@ -77,11 +76,9 @@ module axi_mc_controller
output[1:0] sensors_o,
input [2:0] position_i,
// dma interface
// channel interface
output adc_clk_o,
input adc_dovf_i,
input adc_dunf_i,
output adc_enable_c0,
output adc_enable_c1,
output adc_enable_c2,
@ -137,13 +134,10 @@ module axi_mc_controller
//------------------------------------------------------------------------------
// internal registers
reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg pwm_gen_clk = 'd0;
reg one_chan_reg = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg pwm_gen_clk = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
@ -196,16 +190,12 @@ wire star_delta_s;
wire dir_s;
wire [10:0] pwm_open_s;
wire [10:0] pwm_s;
wire [10:0] gpo_s;
wire dpwm_ah_s;
wire dpwm_al_s;
wire dpwm_bh_s;
wire dpwm_bl_s;
wire dpwm_ch_s;
wire dpwm_cl_s;
wire foc_ctrl_s;
//------------------------------------------------------------------------------
@ -237,7 +227,6 @@ assign adc_data_c5 = ctrl_data5_i;
assign adc_data_c6 = ctrl_data6_i;
assign adc_data_c7 = ctrl_data7_i;
assign ctrl_rst_o = !run_s;
// monitor signals
@ -252,11 +241,6 @@ assign pwm_bl_o = foc_ctrl_s ? pwm_b_i : dpwm_bl_s;
assign pwm_ch_o = foc_ctrl_s ? !pwm_c_i : dpwm_ch_s;
assign pwm_cl_o = foc_ctrl_s ? pwm_c_i : dpwm_cl_s;
// assign gpo
assign gpo_o[7:4] = gpo_s[10:7];
assign gpo_o[3:0] = gpo_s[3:0];
// clock generation
always @(posedge ref_clk)
@ -264,7 +248,6 @@ begin
pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
@ -284,7 +267,7 @@ end
motor_driver
#( .PWM_BITS(11))
motor_driver_inst(
.clk_i(ref_clk),
.clk_i(ctrl_data_clk),
.pwm_clk_i(pwm_gen_clk),
.rst_n_i(up_rstn) ,
.run_i(run_s),
@ -322,7 +305,7 @@ control_registers control_reg_inst(
.kp1_o(),
.ki1_o(),
.kd1_o(),
.gpo_o(gpo_s),
.gpo_o(gpo_o),
.reference_speed_o(),
.oloop_matlab_o(foc_ctrl_s),
.err_i(),
@ -707,9 +690,9 @@ up_adc_common i_up_adc_common(
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b0),
.adc_status_ovf(adc_dovf_i),
.adc_status_unf(adc_dunf_i),
.adc_sync_status(1'b1),
.adc_status_ovf(),
.adc_status_unf(),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
@ -735,7 +718,7 @@ up_adc_common i_up_adc_common(
.drp_ready(1'b0),
.drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.adc_usr_chanmax(8'd7),
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
.up_rstn (up_rstn),
@ -784,4 +767,3 @@ endmodule
// ***************************************************************************
// ***************************************************************************

1
library/axi_mc_controller/axi_mc_controller_ip.tcl Executable file → Normal file
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@ -17,6 +17,7 @@ adi_ip_files axi_mc_controller [list \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"motor_driver.v" \
"delay.v" \
"control_registers.v" \
"axi_mc_controller.v" ]

8
library/axi_mc_controller/control_registers.v
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@ -66,8 +66,8 @@ module control_registers
output break_o,
output dir_o,
output star_delta_o,
output [1:0] sensors_o,
output [10:0] gpo_o,
output [ 1:0] sensors_o,
output [ 3:0] gpo_o,
output oloop_matlab_o,
output calibrate_adcs_o
);
@ -96,8 +96,6 @@ reg [10:0] gpo_r;
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
//internal signals
wire up_wreq_s;
wire up_rreq_s;
@ -115,7 +113,7 @@ assign star_delta_o = control_r[4]; // Select between star [0] o
assign sensors_o = control_r[9:8]; // Select between Hall[00] and BEMF[01] sensors
assign calibrate_adcs_o = control_r[16];
assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1]
assign gpo_o = control_r[30:20];
assign gpo_o = control_r[23:20];
assign pwm_open_o = pwm_open_r[10:0]; // PWM value, for open loop control
assign reference_speed_o = reference_speed_r;

80
library/axi_mc_controller/delay.v Normal file
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@ -0,0 +1,80 @@
// -----------------------------------------------------------------------------
//
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : delay.v
// MODULE NAME : debouncer
// AUTHOR : ACozma
// AUTHOR’S EMAIL : andrei.cozma@analog.com
//
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
module delay
//----------- Parameters Declarations -------------------------------------------
#(
parameter DELAY = 128
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input rst_n_i,
input sig_i,
output reg sig_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [DELAY-1:0] shift_reg;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
always @(posedge clk_i)
begin
if(rst_n_i == 0)
begin
shift_reg <= 0;
sig_o <= 0;
end
else
begin
shift_reg <= {shift_reg[DELAY-2:0], sig_i};
sig_o <= shift_reg[DELAY-1];
end
end
endmodule

82
library/axi_mc_controller/motor_driver.v
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@ -90,6 +90,19 @@ wire align_complete;
wire [PWMBW:0] pwm_duty_s;
wire [1:0] commutation_table[0:2];
wire pwm_al_s;
wire pwm_ah_s;
wire pwm_bl_s;
wire pwm_bh_s;
wire pwm_cl_s;
wire pwm_ch_s;
wire pwmd_al_s;
wire pwmd_ah_s;
wire pwmd_bl_s;
wire pwmd_bh_s;
wire pwmd_cl_s;
wire pwmd_ch_s;
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
@ -97,9 +110,10 @@ wire [1:0] commutation_table[0:2];
localparam OFF = 3'b001;
localparam ALIGN = 3'b010;
localparam RUN = 3'b100;
localparam DT = 20;
localparam [PWMBW:0] ALIGN_PWM_DUTY = 2**(PWMBW) + 2**(PWMBW-3);
localparam [15:0] ALIGN_TIME = 16'h4000;
localparam [15:0] ALIGN_TIME = 16'h8000;
localparam [1:0] COMMUTATION_TABLE_DELTA_CW_0[0:5] = { 2'd1,-2'd1, 2'd1,-2'd1, 2'd1,-2'd1};
@ -116,6 +130,51 @@ localparam [1:0] COMMUTATION_TABLE_STAR_CCW_0[0:5] = {-2'd1, 2'd1, 2'd0, 2'd0,
localparam [1:0] COMMUTATION_TABLE_STAR_CCW_1[0:5] = { 2'd0,-2'd1,-2'd1, 2'd1, 2'd1, 2'd0};
localparam [1:0] COMMUTATION_TABLE_STAR_CCW_2[0:5] = { 2'd1, 2'd0, 2'd1,-2'd1, 2'd0,-2'd1};
delay #(
.DELAY(DT))
delay_ah_i (
.clk_i (clk_i),
.rst_n_i (pwm_ah_s),
.sig_i (pwm_ah_s),
.sig_o (pwmd_ah_s));
delay #(
.DELAY(DT))
delay_al_i (
.clk_i (clk_i),
.rst_n_i (pwm_al_s),
.sig_i (pwm_al_s),
.sig_o (pwmd_al_s));
delay #(
.DELAY(DT))
delay_bh_i (
.clk_i (clk_i),
.rst_n_i (pwm_bh_s),
.sig_i (pwm_bh_s),
.sig_o (pwmd_bh_s));
delay #(
.DELAY(DT))
delay_bl_i (
.clk_i (clk_i),
.rst_n_i (pwm_bl_s),
.sig_i (pwm_bl_s),
.sig_o (pwmd_bl_s));
delay #(
.DELAY(DT))
delay_ch_i (
.clk_i (clk_i),
.rst_n_i (pwm_ch_s),
.sig_i (pwm_ch_s),
.sig_o (pwmd_ch_s));
delay #(
.DELAY(DT))
delay_cl_i (
.clk_i (clk_i),
.rst_n_i (pwm_cl_s),
.sig_i (pwm_cl_s),
.sig_o (pwmd_cl_s));
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
@ -136,14 +195,23 @@ assign commutation_table[2] = star_delta_i ?
//Motor Phases Control
assign AH_o = commutation_table[0] == 2'd1 ? ~pwm_s : commutation_table[0] == -2'd1 ? pwm_s : 1;
assign AL_o = commutation_table[0] == 2'd1 ? pwm_s : commutation_table[0] == -2'd1 ? ~pwm_s : 1;
assign pwm_ah_s = commutation_table[0] == 2'd1 ? ~pwm_s : commutation_table[0] == -2'd1 ? pwm_s : 0;
assign pwm_al_s = commutation_table[0] == 2'd1 ? pwm_s : commutation_table[0] == -2'd1 ? ~pwm_s : 0;
assign BH_o = commutation_table[1] == 2'd1 ? ~pwm_s : commutation_table[1] == -2'd1 ? pwm_s : 1;
assign BL_o = commutation_table[1] == 2'd1 ? pwm_s : commutation_table[1] == -2'd1 ? ~pwm_s : 1;
assign pwm_bh_s = commutation_table[1] == 2'd1 ? ~pwm_s : commutation_table[1] == -2'd1 ? pwm_s : 0;
assign pwm_bl_s = commutation_table[1] == 2'd1 ? pwm_s : commutation_table[1] == -2'd1 ? ~pwm_s : 0;
assign CH_o = commutation_table[2] == 2'd1 ? ~pwm_s : commutation_table[2] == -2'd1 ? pwm_s : 1;
assign CL_o = commutation_table[2] == 2'd1 ? pwm_s : commutation_table[2] == -2'd1 ? ~pwm_s : 1;
assign pwm_ch_s = commutation_table[2] == 2'd1 ? ~pwm_s : commutation_table[2] == -2'd1 ? pwm_s : 0;
assign pwm_cl_s = commutation_table[2] == 2'd1 ? pwm_s : commutation_table[2] == -2'd1 ? ~pwm_s : 0;
assign AL_o = pwmd_ah_s? 0 : pwmd_al_s;
assign AH_o = pwmd_ah_s;
assign BL_o = pwmd_bh_s ? 0 : pwmd_bl_s;
assign BH_o = pwmd_bh_s;
assign CL_o = pwmd_ch_s ? 0 : pwmd_cl_s;
assign CH_o = pwmd_ch_s;
//Control the current motor state
always @(posedge clk_i)

4
library/axi_mc_current_monitor/ad7401.v
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@ -77,8 +77,7 @@ module ad7401
output reg adc_status_o,
//AD7401 control and data interface
input adc_mdata_i, // AD7401 MDAT pin
output adc_mclkin_o // AD7401 MCLKIN pin
input adc_mdata_i // AD7401 MDAT pin
);
//------------------------------------------------------------------------------
@ -113,7 +112,6 @@ localparam WAIT_DATA_RDY_LOW_STATE = 5'b10000;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign adc_mclkin_o = adc_clk_i; // use clock signal for driver and for ADC
// synchronize data on fpga_clki
always @(posedge fpga_clk_i)

443
library/axi_mc_current_monitor/axi_mc_current_monitor.v
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@ -37,8 +37,7 @@
`timescale 1ns/100ps
module axi_mc_current_monitor
#(
module axi_mc_current_monitor #(
parameter C_S_AXI_MIN_SIZE = 32'hffff
)
(
@ -46,30 +45,22 @@ module axi_mc_current_monitor
// physical interface
input adc_ia_dat_i,
output adc_ia_clk_o,
output adc_enable_ia,
input adc_ib_dat_i,
output adc_ib_clk_o,
input adc_it_dat_i,
output adc_it_clk_o,
output adc_enable_ib,
input adc_vbus_dat_i,
output adc_vbus_clk_o,
output adc_enable_vbus,
output adc_enable_stub,
output adc_clk_o,
input ref_clk,
input adc_clk_i,
output [17:0] ia_o,
output [17:0] ib_o,
output [17:0] it_o,
output [15:0] ia_o,
output [15:0] ib_o,
output [15:0] vbus_o,
output i_ready_o,
// dma interface
output adc_clk_o,
output adc_dwr_o,
output [63:0] adc_ddata_o,
output adc_dsync_o,
input adc_dovf_i,
input adc_dunf_i,
// axi interface
input s_axi_aclk,
@ -90,40 +81,16 @@ module axi_mc_current_monitor
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// debug signals
output adc_mon_valid,
output [31:0] adc_mon_data
input s_axi_rready
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg adc_valid = 'd0;
reg [63:0] adc_data = 'd0;
reg [47:0] adc_data_3 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [1:0] adc_data_cnt = 'd0;
reg [9:0] adc_clk_cnt = 'd0; // used to generate 10 MHz clock for ADCs
reg adc_clk_reg = 'd0; // used to generate 10 MHz clock for ADCs
reg acq_run_reg = 'd0; // register used for synchronizing data acquisition
reg adc_valid_3 = 'd0;
reg [47:0] adc_data_3_1110 = 'd0;
reg [47:0] adc_data_3_1101 = 'd0;
reg [47:0] adc_data_3_1011 = 'd0;
reg [47:0] adc_data_3_0111 = 'd0;
reg [63:0] adc_data_1110 = 'd0;
reg [63:0] adc_data_1101 = 'd0;
reg [63:0] adc_data_1011 = 'd0;
reg [63:0] adc_data_0111 = 'd0;
reg adc_dsync_r_3 = 'd0;
reg adc_dsync_r = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
@ -148,27 +115,22 @@ wire [31:0] up_rdata_0_s;
wire [31:0] up_rdata_1_s;
wire [31:0] up_rdata_2_s;
wire [31:0] up_rdata_3_s;
wire up_ack_0_s;
wire up_ack_1_s;
wire up_ack_2_s;
wire up_ack_3_s;
wire up_rack_0_s;
wire up_rack_1_s;
wire up_rack_2_s;
wire up_rack_3_s;
wire up_wack_0_s;
wire up_wack_1_s;
wire up_wack_2_s;
wire up_wack_3_s;
wire adc_status_a_s;
wire [15:0] adc_data_ia_s ;
wire data_rd_ready_ia_s;
wire adc_status_b_s;
wire [15:0] adc_data_ib_s;
wire adc_status_it_s;
wire [15:0] adc_data_it_s;
wire [15:0] adc_data_it_n_s;
wire adc_status_vbus_s;
wire [15:0] adc_data_vbus_s ;
wire adc_enable_ia;
wire adc_enable_ib;
wire adc_enable_it;
wire adc_enable_vbus;
wire adc_clk_s;
wire [15:0] adc_data_vbus_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
@ -179,304 +141,17 @@ wire adc_clk_s;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ref_clk; // use reference clock to send data to the dma
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
assign adc_dsync_o = adc_dsync_r;
// monitor signals
assign adc_mon_valid = data_rd_ready_ia_s;
assign adc_mon_data[15: 0] = adc_data[15:0];
assign adc_mon_data[31:16] = {adc_enable_vbus, adc_enable_it, adc_enable_ib, adc_enable_ia, adc_rst, data_rd_ready_ia_s, adc_data_cnt, adc_ia_clk_o, adc_data_ia_s[6:0]};
// current outputs
assign i_ready_o = data_rd_ready_ia_s;
assign ia_o = {adc_data_ia_s - 16'h7FFF, 2'b00};
assign ib_o = {adc_data_ib_s - 16'h7FFF, 2'b00};
assign it_o = {adc_data_it_s, 2'b00};
assign adc_data_it_n_s = 65535 - adc_data_it_s;
assign i_ready_o = data_rd_ready_ia_s;
assign ia_o = adc_data_ia_s ;
assign ib_o = adc_data_ib_s ;
assign vbus_o = adc_data_vbus_s;
// adc clock
assign adc_clk_s = adc_clk_reg;
// ADC clock generation
always @(posedge ref_clk)
begin
if(adc_clk_cnt < 10'd4)
begin
adc_clk_cnt <= adc_clk_cnt + 1;
end
else
begin
adc_clk_cnt <= 10'd0;
adc_clk_reg <= ~adc_clk_reg;
end
end
// adc channels - dma interface
always @(posedge ref_clk)
begin
if(data_rd_ready_ia_s == 1'b1)
begin
adc_valid_3 <= adc_data_cnt[0] | adc_data_cnt[1];
adc_dsync_r_3 <= adc_data_cnt[0] | ~adc_data_cnt[1];
adc_data_3_1110[47:32] <= adc_data_vbus_s;
adc_data_3_1110[31:16] <= adc_data_it_n_s;
adc_data_3_1110[15:0] <= adc_data_ib_s;
adc_data_3_1101[47:32] <= adc_data_vbus_s;
adc_data_3_1101[31:16] <= adc_data_it_n_s;
adc_data_3_1101[15:0] <= adc_data_ia_s;
adc_data_3_1011[47:32] <= adc_data_vbus_s;
adc_data_3_1011[31:16] <= adc_data_ib_s;
adc_data_3_1011[15:0] <= adc_data_ia_s;
adc_data_3_0111[47:32] <= adc_data_it_n_s;
adc_data_3_0111[31:16] <= adc_data_ib_s;
adc_data_3_0111[15:0] <= adc_data_ia_s;
case(adc_data_cnt)
2'b11:
begin
adc_data_1110[63:48] <= adc_data_vbus_s;
adc_data_1110[47:32] <= adc_data_it_n_s;
adc_data_1110[31:16] <= adc_data_ib_s;
adc_data_1110[15:0] <= adc_data_3_1110[47:32];
adc_data_1101[63:48] <= adc_data_vbus_s;
adc_data_1101[47:32] <= adc_data_it_n_s;
adc_data_1101[31:16] <= adc_data_ia_s;
adc_data_1101[15:0] <= adc_data_3_1101[47:32];
adc_data_1011[63:48] <= adc_data_vbus_s;
adc_data_1011[47:32] <= adc_data_ib_s;
adc_data_1011[31:16] <= adc_data_ia_s;
adc_data_1011[15:0] <= adc_data_3_1011[47:32];
adc_data_0111[63:48] <= adc_data_it_n_s;
adc_data_0111[47:32] <= adc_data_ib_s;
adc_data_0111[31:16] <= adc_data_ia_s;
adc_data_0111[15:0] <= adc_data_3_0111[47:32];
end
2'b10:
begin
adc_data_1110[63:48] <= adc_data_it_n_s;
adc_data_1110[47:32] <= adc_data_ib_s;
adc_data_1110[31:16] <= adc_data_3_1110[47:32];
adc_data_1110[15:0] <= adc_data_3_1110[31:16];
adc_data_1101[63:48] <= adc_data_it_n_s;
adc_data_1101[47:32] <= adc_data_ia_s;
adc_data_1101[31:16] <= adc_data_3_1101[47:32];
adc_data_1101[15:0] <= adc_data_3_1101[31:16];
adc_data_1011[63:48] <= adc_data_ib_s;
adc_data_1011[47:32] <= adc_data_ia_s;
adc_data_1011[31:16] <= adc_data_3_1011[47:32];
adc_data_1011[15:0] <= adc_data_3_1011[31:16];
adc_data_0111[63:48] <= adc_data_ib_s;
adc_data_0111[47:32] <= adc_data_ia_s;
adc_data_0111[31:16] <= adc_data_3_0111[47:32];
adc_data_0111[15:0] <= adc_data_3_0111[31:16];
end
2'b01:
begin
adc_data_1110[63:48] <= adc_data_ib_s;
adc_data_1110[47:32] <= adc_data_3_1110[47:32];
adc_data_1110[31:16] <= adc_data_3_1110[31:16];
adc_data_1110[15:0] <= adc_data_3_1110[15:0];
adc_data_1101[63:48] <= adc_data_ia_s;
adc_data_1101[47:32] <= adc_data_3_1101[47:32];
adc_data_1101[31:16] <= adc_data_3_1101[31:16];
adc_data_1101[15:0] <= adc_data_3_1101[15:0];
adc_data_1011[63:48] <= adc_data_ia_s;
adc_data_1011[47:32] <= adc_data_3_1011[47:32];
adc_data_1011[31:16] <= adc_data_3_1011[31:16];
adc_data_1011[15:0] <= adc_data_3_1011[15:0];
adc_data_0111[63:48] <= adc_data_ia_s;
adc_data_0111[47:32] <= adc_data_3_0111[47:32];
adc_data_0111[31:16] <= adc_data_3_0111[31:16];
adc_data_0111[15:0] <= adc_data_3_0111[15:0];
end
2'b00:
begin
adc_data_1110[63:48] <= 16'hdead;
adc_data_1110[47:32] <= 16'hdead;
adc_data_1110[31:16] <= 16'hdead;
adc_data_1110[15:0] <= 16'hdead;
adc_data_1101[63:48] <= 16'hdead;
adc_data_1101[47:32] <= 16'hdead;
adc_data_1101[31:16] <= 16'hdead;
adc_data_1101[15:0] <= 16'hdead;
adc_data_1011[63:48] <= 16'hdead;
adc_data_1011[47:32] <= 16'hdead;
adc_data_1011[31:16] <= 16'hdead;
adc_data_1011[15:0] <= 16'hdead;
adc_data_0111[63:48] <= 16'hdead;
adc_data_0111[47:32] <= 16'hdead;
adc_data_0111[31:16] <= 16'hdead;
adc_data_0111[15:0] <= 16'hdead;
end
endcase
end
end
always @(posedge ref_clk)
begin
if(data_rd_ready_ia_s == 1'b1)
begin
case({adc_enable_vbus, adc_enable_it, adc_enable_ib, adc_enable_ia})
4'b1111:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= 1'b1;
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data_it_n_s;
adc_data[31:16] <= adc_data_ib_s;
adc_data[15: 0] <= adc_data_ia_s;
end
4'b1110:
begin
adc_dsync_r <= adc_dsync_r_3;
adc_valid <= adc_valid_3;
adc_data <= adc_data_1110;
end
4'b1101:
begin
adc_dsync_r <= adc_dsync_r_3;
adc_valid <= adc_valid_3;
adc_data <= adc_data_1101;
end
4'b1100:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data_it_n_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1011:
begin
adc_dsync_r <= adc_dsync_r_3;
adc_valid <= adc_valid_3;
adc_data <= adc_data_1011;
end
4'b1010:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data_ib_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1001:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data_ia_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1000:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= adc_data_vbus_s;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0111:
begin
adc_dsync_r <= adc_dsync_r_3;
adc_valid <= adc_valid_3;
adc_data <= adc_data_0111;
end
4'b0110:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_it_n_s;
adc_data[47:32] <= adc_data_ib_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0101:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_it_n_s;
adc_data[47:32] <= adc_data_ia_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0100:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= adc_data_it_n_s;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0011:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[0];
adc_data[63:48] <= adc_data_ib_s;
adc_data[47:32] <= adc_data_ia_s;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0010:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= adc_data_ib_s;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0001:
begin
adc_dsync_r <= 1'b1;
adc_data_3 <= 48'd0;
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= adc_data_ia_s;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
default:
begin
adc_dsync_r <= 1'b0;
adc_data_3 <= 48'd0;
adc_valid <= 1'b1;
adc_data[63:48] <= 16'hdead;
adc_data[47:32] <= 16'hdead;
adc_data[31:16] <= 16'hdead;
adc_data[15: 0] <= 16'hdead;
end
endcase
adc_data_cnt <= adc_data_cnt + 2'b1;
end
else
begin
adc_valid <= 1'b0;
adc_data <= adc_data;
adc_data_cnt <= adc_data_cnt;
end
end
assign adc_clk_o = adc_clk_i;
// processor read interface
@ -485,14 +160,14 @@ begin
if(up_rstn == 0)
begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end
else
begin
up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s ;
up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s ;
up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s ;
up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s |up_rdata_3_s ;
up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s ;
up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s;
end
end
@ -500,46 +175,33 @@ end
ad7401 ia_if(
.fpga_clk_i(ref_clk),
.adc_clk_i(adc_clk_s),
.adc_clk_i(adc_clk_o),
.reset_i(adc_rst),
.adc_status_o(adc_status_a_s),
.data_o(adc_data_ia_s),
.data_rd_ready_o(data_rd_ready_ia_s),
.adc_mdata_i(adc_ia_dat_i),
.adc_mclkin_o(adc_ia_clk_o));
.adc_mdata_i(adc_ia_dat_i));
ad7401 ib_if(
.fpga_clk_i(ref_clk),
.adc_clk_i(adc_clk_s),
.adc_clk_i(adc_clk_o),
.reset_i(adc_rst),
.adc_status_o(adc_status_b_s),
.data_o(adc_data_ib_s),
.data_rd_ready_o(),
.adc_mdata_i(adc_ib_dat_i),
.adc_mclkin_o(adc_ib_clk_o));
ad7401 it_if(
.fpga_clk_i(ref_clk),
.adc_clk_i(adc_clk_s),
.reset_i(adc_rst),
.adc_status_o(adc_status_it_s),
.data_o(adc_data_it_s),
.data_rd_ready_o(),
.adc_mdata_i(adc_it_dat_i),
.adc_mclkin_o(adc_it_clk_o));
.adc_mdata_i(adc_ib_dat_i));
ad7401 vbus_if(
.fpga_clk_i(ref_clk),
.adc_clk_i(adc_clk_s),
.adc_clk_i(adc_clk_o),
.reset_i(adc_rst),
.adc_status_o(adc_status_vbus_s),
.data_o(adc_data_vbus_s),
.data_rd_ready_o(),
.adc_mdata_i(adc_vbus_dat_i),
.adc_mclkin_o(adc_vbus_clk_o));
.adc_mdata_i(adc_vbus_dat_i));
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
.adc_clk(adc_clk_s),
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_enable(adc_enable_ia),
.adc_iqcor_enb(),
@ -585,7 +247,7 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
.up_rack (up_rack_0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
.adc_clk(adc_clk_s),
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_enable(adc_enable_ib),
.adc_iqcor_enb(),
@ -628,10 +290,10 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
.up_rdata (up_rdata_1_s),
.up_rack (up_rack_1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
.adc_clk(adc_clk_s),
up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_vbus(
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_enable(adc_enable_it),
.adc_enable(adc_enable_vbus),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
@ -672,10 +334,10 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
.up_rdata (up_rdata_2_s),
.up_rack (up_rack_2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
.adc_clk(adc_clk_s),
up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_stub(
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_enable(adc_enable_vbus),
.adc_enable(adc_enable_stub),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
@ -720,15 +382,15 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(adc_clk_s),
.adc_clk(adc_clk_o),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b0),
.adc_status_ovf(adc_dovf_i),
.adc_status_unf(adc_dunf_i),
.adc_sync_status(1'b1),
.adc_status_ovf(),
.adc_status_unf(),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
@ -758,7 +420,7 @@ up_adc_common i_up_adc_common(
.drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.adc_usr_chanmax(8'd3),
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
@ -808,4 +470,3 @@ endmodule
// ***************************************************************************
// ***************************************************************************

0
library/axi_mc_current_monitor/axi_mc_current_monitor_ip.tcl Executable file → Normal file
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103
library/axi_mc_speed/axi_mc_speed.v
View File

@ -39,14 +39,12 @@
module axi_mc_speed
#(
parameter C_S_AXI_MIN_SIZE = 32'hffff,
parameter MOTOR_CONTROL_REVISION = 2
parameter C_S_AXI_MIN_SIZE = 32'hffff
)
//----------- Ports Declarations -----------------------------------------------
(
// physical interface
input [2:0] position_i,
input [2:0] bemf_i,
output [2:0] position_o,
output [31:0] speed_o,
output new_speed_o,
@ -54,16 +52,7 @@ module axi_mc_speed
input ref_clk,
// dma interface
output adc_clk_o,
output adc_dwr_o,
output [31:0] adc_ddata_o,
input adc_dovf_i,
input adc_dunf_i,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
@ -82,19 +71,11 @@ module axi_mc_speed
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
// debug signals
output adc_mon_valid,
output [31:0] adc_mon_data);
input s_axi_rready);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
@ -103,14 +84,11 @@ reg up_rack = 'd0;
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire adc_start_s;
wire [31:0] speed_data_s;
wire adc_enable_s;
wire adc_status_s;
@ -123,45 +101,25 @@ wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_wack_s;
wire up_adc_common_rack_s;
wire [31:0] pid_s;
wire [ 2:0] position_s;
wire [ 2:0] bemf_s;
wire [ 2:0] bemf_delayed_s;
wire new_speed_s;
wire [ 2:0] bemf_multiplex_s;
wire [ 2:0] position_s;
wire [ 2:0] bemf_s;
wire [ 2:0] bemf_delayed_s;
wire new_speed_s;
wire [ 2:0] bemf_multiplex_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ref_clk;
assign adc_dwr_o = adc_valid;
assign adc_ddata_o = adc_data;
// monitor signals
assign adc_mon_valid = new_speed_s;
assign adc_mon_data = { 20'h0, bemf_multiplex_s, bemf_s, bemf_delayed_s, position_s };
assign bemf_multiplex_s =(MOTOR_CONTROL_REVISION == 2) ? position_i : bemf_i;
assign bemf_s = position_s ;
assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s;
assign new_speed_o = new_speed_s;
assign speed_o = speed_data_s;
// adc channels - dma interface
always @(posedge ref_clk)
begin
adc_data <= speed_data_s;
adc_valid <= new_speed_s;
end
// processor read interface
always @(negedge up_rstn or posedge up_clk)
begin
if(up_rstn == 0)
@ -178,7 +136,6 @@ begin
end
// HALL sensors debouncers
debouncer
#( .DEBOUNCER_LEN(400))
position_0(
@ -203,31 +160,6 @@ position_2(
.sig_i(position_i[2]),
.sig_o(position_s[2]));
// BEMF debouncer
debouncer
#( .DEBOUNCER_LEN(400))
bemf_0(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(bemf_multiplex_s[0]),
.sig_o(bemf_s[0]));
debouncer
#( .DEBOUNCER_LEN(400))
bemf_1(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(bemf_multiplex_s[1]),
.sig_o(bemf_s[1]));
debouncer
#( .DEBOUNCER_LEN(400))
bemf_2(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(bemf_multiplex_s[2]),
.sig_o(bemf_s[2]));
delay_30_degrees delay_30_degrees_i1(
.clk_i(ref_clk),
.rst_i(adc_rst),
@ -247,8 +179,7 @@ speed_detector_inst(
.current_speed_o(),
.speed_o(speed_data_s));
// common processor control
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(ref_clk),
@ -257,9 +188,15 @@ up_adc_common i_up_adc_common(
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_status_ovf(adc_dovf_i),
.adc_status_unf(adc_dunf_i),
.adc_sync_status(1'b1),
.adc_status_ovf(),
.adc_status_unf(),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.delay_clk(1'b0),
.delay_rst(),
.delay_sel(),
@ -279,8 +216,8 @@ up_adc_common i_up_adc_common(
.drp_ready(1'b0),
.drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd0),
.up_adc_gpio_in(),
.adc_usr_chanmax(8'd2),
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
.up_rstn(up_rstn),
.up_clk(up_clk),
@ -294,7 +231,6 @@ up_adc_common i_up_adc_common(
.up_rack (up_adc_common_rack_s));
// up bus interface
up_axi i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
@ -325,6 +261,5 @@ up_axi i_up_axi(
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

0
library/axi_mc_speed/axi_mc_speed_ip.tcl Executable file → Normal file
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1
library/axi_mc_speed/debouncer.v
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@ -77,6 +77,7 @@ reg [DEBOUNCER_LEN-1:0] shift_reg;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
always @(posedge clk_i)
begin
if(rst_i == 1)

12
library/axi_mc_speed/delay_30_degrees.v
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@ -83,12 +83,12 @@ localparam IDLE = 6'b100000;
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [5:0] state; // current state
reg [5:0] next_state; // next state
reg [2:0] position_old; // saves the latest position
reg [31:0] speed_count; // counts the current speed of rotation
reg [31:0] speed_divider; // divides the speed of rotation by 2, correspoding to 30 degrees
reg [31:0] delay_count; // Applied the delay to the input signal
reg [5:0] state = RESET; // current state
reg [5:0] next_state = RESET; // next state
reg [2:0] position_old = 3'h0; // saves the latest position
reg [31:0] speed_count = 32'h0; // counts the current speed of rotation
reg [31:0] speed_divider = 32'h0; // divides the speed of rotation by 2, correspoding to 30 degrees
reg [31:0] delay_count = 32'h0; // Applied the delay to the input signal
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------

8
library/axi_mc_speed/speed_detector.v
View File

@ -77,9 +77,7 @@ module speed_detector
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
localparam AW = LOG_2_AW - 1;
localparam MAX_SPEED_CNT = 32'h10000;
//State machine
@ -94,14 +92,13 @@ localparam IDLE = 8'b10000000;
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [ 2:0] position_old;
reg [63:0] avg_register;
reg [63:0] avg_register_stable;
reg [31:0] cnt_period;
reg [31:0] decimation; // register used to divide by ten the speed
reg [31:0] decimation; // register used to divide by ten the speed
reg [31:0] cnt_period_old;
reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM
reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM
reg [AW:0] write_addr;
reg [AW:0] read_addr;
@ -113,7 +110,6 @@ reg [ 7:0] next_state;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// Count ticks per position
always @(posedge clk_i)
begin