docs: Add ad7606x documentation
docs/projects/ad7606x_fmcz: Add ad7606_fmcz project documentation Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>main
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.. _ad7606x_fmc:
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AD7606X-FMCZ HDL project
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===============================================================================
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Overview
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-------------------------------------------------------------------------------
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The :adi:`AD7606` is a 8-/6-/4-Channel DAS with 16-Bit, Bipolar Input,
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Simultaneous Sampling ADC. Each part contains analog input clamp protection, a
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second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge
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redistribution successive approximation analog-to-digital converter (ADC), a
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flexible digital filter, a 2.5 V reference and reference buffer, and high speed
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serial and parallel interfaces. The :adi:`AD7606` operate from a single 5 V
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supply and can accommodate ±10 V and ±5 V true bipolar input signals while
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sampling at throughput rates up to 200 kSPS for all channels. The input clamp
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protection circuitry can tolerate voltages up to ±16.5 V. The AD7606 has 1 MΩ
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analog input impedance regardless of sampling frequency. The single supply
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operation, on-chip filtering, and high input impedance eliminate the need for
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driver op amps and external bipolar supplies.
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The :adi:`AD7606C` is a directly pin replacement (software and hardware) for
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both AD7608 and AD7609, with higher input impedance, throughput rate and
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extended temperature range with additional features such as 16/18-bit sample
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size, system gain/offset/phase calibration, sensor disconnect detection,
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lower Vdrive operation, diagnostics, additional oversampling ratios and per
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channel analog input range selection with bipolar differential, bipolar
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single-ended and unipolar single-ended options.
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The :adi:`EVAL-AD7606B-FMCZ <EVAL-AD7606B-FMCZ>` and
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:adi:`EVAL-AD7606C-18 <EVAL-AD7606C-18>` evaluation boards are designed to
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help users to easily evaluate the features of :adi:`AD7606B`,
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:adi:`AD7606C-16` and :adi:`AD7606C-18` analog-to-digital converters (ADCs).
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`EVAL-AD7606B <EVAL-AD7606B>`
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- :adi:`EVAL-AD7606C-16 <AD7606C-16>`
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- :adi:`EVAL-AD7606C-18 <EVAL-AD7606C-18>`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD7606B`
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- :adi:`AD7606C-16`
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- :adi:`AD7606C-18`
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- :adi:`ADP7118`
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- :adi:`ADR4525`
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Supported carriers
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-------------------------------------------------------------------------------
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- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot
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Block design
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-------------------------------------------------------------------------------
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The data path of the HDL design is simple as follows:
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- the parallel interface is controlled by the
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:dokuwiki:`axi_ad7606x <resources/fpga/docs/axi_ad7606x>` IP core
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- the serial interface is controlled by the :ref:`SPI_Engine <spi_engine>`
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Framework
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- data is written into memory by a DMA (:ref:`axi_dmac core <axi_dmac>`)
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- all the control pins of the device are driven by GPIOs
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagrams:
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AD7606x_FMCZ serial interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. image:: ad7606x_serial_hdl.svg
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:width: 800
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:align: center
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:alt: AD7606X_FMC using the serial interface block diagram
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AD7606x_FMCZ parallel interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. image:: ad7606x_parallel_hdl.svg
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:width: 800
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:align: center
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:alt: AD7606X_FMC using the parallel interface block diagram
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Configuration modes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The INTF configuration parameter defines the interface type (Serial or Parallel).
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By default it is set to 0. Depending on the required interface mode, some
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hardware modifications need to be done on the board and/or ``make`` command:
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In case of the **PARALLEL** interface:
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.. code-block::
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make INTF=0
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In case of the **SERIAL** interface:
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.. code-block::
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make INTF=1
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.. note::
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This switch is a **hardware** switch. Please rebuild the design if the
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variable has been changed.
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- JP5 - Position A - Serial interface
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- JP5 - Position B - Parallel interface
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The DEV_CONFIG configuration parameter defines the device which will be used:
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- Options: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18.
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By default it is set to 0.
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The NUM_OF_SDI configuration parameter defines the number of SDI lines used:
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- Options: 1, 2, 4, 8.
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By default is set to 8.
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The EXT_CLK configuration parameter defines the external clock option for
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the ADC clock:
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- Options: 0 - No, 1 - Yes.
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By default is set to 0.
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Jumper setup
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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================== ================ =============================================
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Jumper/Solder link Default Position Description
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================== ================ =============================================
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JP1 A The STBY pin is tied to VDRIVE
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JP2 A 12V supply from the carrier
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JP3 A 3.3V supply from the ADP7118
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JP4 A ±10V range is selected
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JP5 A Serial interface
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JP6 B The internal reference is disabled, and
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the external reference is selected.
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P5 must be inserted if using the on-board
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U1 device
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JP7 B Connects the V1- line to the J5 SMB connector
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JP8,JP10 A Bypasses the amplifier mezzanine card
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JP9,JP11 A Bypasses the amplifier mezzanine card
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JP12 B Connects the V2- line to the J6 SMB connector
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JP13 B Connects the V3- line to the J7 SMB connector
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JP14 B Connects the V4- line to the J8 SMB connector
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P13 Inserted Connects the V5- line to ground
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P14 Inserted Connects the V8- line to ground
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P15 Inserted Connects the V6- line to ground
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P16 Inserted Connects the V7- line to ground
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S1 On Controls the OS0, OS1, and OS2 pins
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================== ================ =============================================
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref:`architecture`).
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======================== ===========
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Instance Address
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======================== ===========
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axi_ad7606x_dma 0x44A3_0000
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spi_clkgen 0x44A7_0000
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ad7606_pwm_gen 0x44B0_0000
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spi_ad7616_axi_regmap ** 0x44A0_0000
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axi_ad7606x * 0x44A0_0000
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======================== ===========
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.. admonition:: Legend
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:class: note
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- ``*`` instantiated only for INTF=0 (parallel interface)
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- ``**`` instantiated only for INTF=1 (serial interface)
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I2C connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 20 20 20 20 20
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:header-rows: 1
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* - I2C type
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- I2C manager instance
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- Alias
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- Address
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- I2C subordinate
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* - PL
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- iic_fmc
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- axi_iic_fmc
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- 0x4162_0000
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- ---
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* - PL
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- iic_main
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- axi_iic_main
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- 0x4160_0000
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- ---
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS
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* - PL
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- axi_spi_engine
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- AD7606
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- 0
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Software GPIO number is calculated as follows:
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- Zynq-7000: if PS7 is used, then offset is 54
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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* - adc_serpar
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- OUT
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- 39
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- 93
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* - adc_refsel *
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- OUT
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- 38
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- 92
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* - adc_first_data **
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- IN
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- 38
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- 92
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* - adc_reset
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- OUT
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- 37
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- 91
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* - adc_stby
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- OUT
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- 36
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- 90
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* - adc_range
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- OUT
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- 35
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- 89
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* - adc_os
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- OUT
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- 34-32
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- 88-86
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.. admonition:: Legend
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:class: note
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- ``*`` instantiated only for INTF=0 (parallel interface)
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- ``**`` instantiated only for INTF=1 (serial interface)
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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=============== === ========== ===========
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Instance name HDL Linux Zynq Actual Zynq
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=============== === ========== ===========
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axi_ad7606_dma 13 57 89
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spi_ad7606 ** 12 56 88
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=============== === ========== ===========
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.. admonition:: Legend
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:class: note
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- ``*`` instantiated only for INTF=0 (parallel interface)
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- ``**`` instantiated only for INTF=1 (serial interface)
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here <main:/>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:.
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**Linux/Cygwin/WSL**
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.. code-block::
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:linenos:
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user@analog:~$ cd hdl/projects/ad7606x_fmc/zed
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user@analog:~/hdl/projects/ad7606x_fmc/zed$ make DEV_CONFIG=2 INTF=0
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The result of the build, if parameters were used, will be in a folder named
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by the configuration used:
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if the following command was run
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``make DEV_CONFIG=2 INTF=0``
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then the folder name will be:
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``DEVCONFIG2_INTF0``
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A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
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Connections and hardware changes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. warning::
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**The following hardware changes are required:**
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Depending on the required interface mode, some hardware modifications need to
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be done.
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- **JP5** - A - Serial interface
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- **JP5** - B - Parallel interface
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- **JP7, JP12, JP13, JP14** - B - Differential operation
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Resources
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-------------------------------------------------------------------------------
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheets:
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- :adi:`AD7606`
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- :adi:`AD7606B`
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- :adi:`AD7606C-16`
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- :adi:`AD7606C-18`
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- :adi:`ADP7118`
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- :adi:`ADR4525`
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- :adi:`UG-1870, Evaluation Board User Guide <media/en/technical-documentation/user-guides/eval-ad7606c-fmcz-ug-1870.pdf>`
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`AD7606X_FMC HDL project source code <projects/ad7606x_fmc>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - SYNC_BITS
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- :git-hdl:`library/util_cdc/sync_bits.v <library/util_cdc/sync_bits.v>` **
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- ---
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* - AD_EDGE_DETECT
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- :git-hdl:`library/common/ad_edge_detect.v <library/common/ad_edge_detect.v>`
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- ---
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* - AXI_AD7606x
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- :git-hdl:`library/axi_ad7606x <library/axi_ad7606x>` *
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_ad7606x>`
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac <library/axi_dmac>`
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- :ref:`here <axi_dmac>`
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* - AXI_HDMI_TX
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- :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_I2S_ADI
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- :git-hdl:`library/axi_i2s_adi <library/axi_i2s_adi>`
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- ---
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* - AXI_PWM_GEN
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||||||
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- :git-hdl:`library/axi_pwm_gen <library/axi_pwm_gen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_pwm_gen>`
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* - AXI_SPDIF_TX
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||||||
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- :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
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||||||
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- ---
|
||||||
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* - AXI_SYSID
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||||||
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- :git-hdl:`library/axi_sysid <library/axi_sysid>`
|
||||||
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
||||||
|
* - AXI_SPI_ENGINE
|
||||||
|
- :git-hdl:`library/spi_engine/axi_spi_engine <library/spi_engine/axi_spi_engine>` **
|
||||||
|
- :ref:`here <spi_engine axi>`
|
||||||
|
* - SPI_ENGINE_EXECUTION
|
||||||
|
- :git-hdl:`library/spi_engine/spi_engine_execution <library/spi_engine/spi_engine_execution>` **
|
||||||
|
- :ref:`here <spi_engine execution>`
|
||||||
|
* - SPI_ENGINE_INTERCONNECT
|
||||||
|
- :git-hdl:`library/spi_engine/spi_engine_interconnect <library/spi_engine/spi_engine_interconnect>` **
|
||||||
|
- :ref:`here <spi_engine interconnect>`
|
||||||
|
* - SPI_ENGINE_OFFLOAD
|
||||||
|
- :git-hdl:`library/spi_engine/spi_engine_offload <library/spi_engine/spi_engine_offload>` **
|
||||||
|
- :ref:`here <spi_engine offload>`
|
||||||
|
* - SYSID_ROM
|
||||||
|
- :git-hdl:`library/sysid_rom <library/sysid_rom>`
|
||||||
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
||||||
|
* - UTIL_I2C_MIXER
|
||||||
|
- :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
|
||||||
|
- ---
|
||||||
|
* - UTIL_CPACK2
|
||||||
|
- :git-hdl:`library/util_pack/util_cpack2 <library/util_pack/util_cpack2>` *
|
||||||
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/util_cpack>`
|
||||||
|
|
||||||
|
.. admonition:: Legend
|
||||||
|
:class: note
|
||||||
|
|
||||||
|
- ``*`` instantiated only for INTF=0 (parallel interface)
|
||||||
|
- ``**`` instantiated only for INTF=1 (serial interface)
|
||||||
|
|
||||||
|
- :ref:`SPI Engine Framework documentation <spi_engine>`
|
||||||
|
|
||||||
|
Software related
|
||||||
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||||
|
|
||||||
|
- :git-no-os:`AD7606_FMC No-OS driver source code <drivers/adc/ad7606>`
|
||||||
|
- :dokuwiki:`AD7606 - No-OS Driver [Wiki] <resources/tools-software/uc-drivers/ad7606>`
|
||||||
|
- :dokuwiki:`How to build No-OS <resources/no-os/build>`
|
||||||
|
|
||||||
|
.. include:: ../common/more_information.rst
|
||||||
|
|
||||||
|
.. include:: ../common/support.rst
|
||||||
|
|
@ -25,6 +25,7 @@ Contents
|
||||||
AD7134-FMC <ad7134_fmc/index>
|
AD7134-FMC <ad7134_fmc/index>
|
||||||
AD719X-ASDZ <ad719x_asdz/index>
|
AD719X-ASDZ <ad719x_asdz/index>
|
||||||
AD738X-FMC <ad738x_fmc/index>
|
AD738X-FMC <ad738x_fmc/index>
|
||||||
|
AD7606X-FMC <ad7606x_fmc/index>
|
||||||
AD7616-SDZ <ad7616_sdz/index>
|
AD7616-SDZ <ad7616_sdz/index>
|
||||||
AD7768-EVB <ad7768evb/index>
|
AD7768-EVB <ad7768evb/index>
|
||||||
AD9081-FMCA-EBZ/AD9082-FMCA-EBZ <ad9081_fmca_ebz/index>
|
AD9081-FMCA-EBZ/AD9082-FMCA-EBZ <ad9081_fmca_ebz/index>
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue