From a8815576452970d6cf046fd763ceb9a670d820b3 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 31 Mar 2014 17:38:20 +0300 Subject: [PATCH] base_design: Fixed AC701 and VC707 contstraints AC701: Modified the IOSTANDARD for some of the pins to correspond to the AC701 user guide. VC707: Fixed naming for some system clocks --- projects/common/ac701/ac701_system_constr.xdc | 50 +++++++++---------- projects/common/vc707/vc707_system_constr.xdc | 10 ++-- 2 files changed, 28 insertions(+), 32 deletions(-) diff --git a/projects/common/ac701/ac701_system_constr.xdc b/projects/common/ac701/ac701_system_constr.xdc index 38c03d6ba..797cca0c6 100755 --- a/projects/common/ac701/ac701_system_constr.xdc +++ b/projects/common/ac701/ac701_system_constr.xdc @@ -5,8 +5,8 @@ set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS15} [get_ports sys_rst # clocks -set_property -dict {PACKAGE_PIN R3 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_p] -set_property -dict {PACKAGE_PIN P3 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD DIFF_SSTL15 DIFF_TERM TRUE} [get_ports sys_clk_p] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD DIFF_SSTL15 DIFF_TERM TRUE} [get_ports sys_clk_n] create_clock -name sys_clk -period 5.00 [get_ports sys_clk_p] @@ -42,32 +42,32 @@ set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS25} [get_ports fan_pwm # lcd -set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[6]] ; ## lcd_e -set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[5]] ; ## lcd_rs -set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[4]] ; ## lcd_rw -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[3]] ; ## lcd_db[7] -set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[2]] ; ## lcd_db[6] -set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[1]] ; ## lcd_db[5] -set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[0]] ; ## lcd_db[4] -set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS15} [get_ports gpio_sw[0]] ; ## GPIO_DIP_SW0 -set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS15} [get_ports gpio_sw[1]] ; ## GPIO_DIP_SW1 -set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS15} [get_ports gpio_sw[2]] ; ## GPIO_DIP_SW2 -set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[3]] ; ## GPIO_DIP_SW3 +set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[6]] ; ## lcd_e +set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[5]] ; ## lcd_rs +set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[4]] ; ## lcd_rw +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[3]] ; ## lcd_db[7] +set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[2]] ; ## lcd_db[6] +set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[1]] ; ## lcd_db[5] +set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[0]] ; ## lcd_db[4] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD SSTL15} [get_ports gpio_sw[0]] ; ## GPIO_DIP_SW0 +set_property -dict {PACKAGE_PIN P8 IOSTANDARD SSTL15} [get_ports gpio_sw[1]] ; ## GPIO_DIP_SW1 +set_property -dict {PACKAGE_PIN R7 IOSTANDARD SSTL15} [get_ports gpio_sw[2]] ; ## GPIO_DIP_SW2 +set_property -dict {PACKAGE_PIN R6 IOSTANDARD SSTL15} [get_ports gpio_sw[3]] ; ## GPIO_DIP_SW3 set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[4]] ; ## GPIO_SW_N -set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[5]] ; ## GPIO_SW_E -set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[6]] ; ## GPIO_SW_S -set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[7]] ; ## GPIO_SW_W -set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[8]] ; ## GPIO_SW_C -set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS15} [get_ports gpio_led[0]] ; ## GPIO_LED_0_LS -set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS15} [get_ports gpio_led[1]] ; ## GPIO_LED_1_LS -set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS15} [get_ports gpio_led[2]] ; ## GPIO_LED_2_LS -set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS15} [get_ports gpio_led[3]] ; ## GPIO_LED_3_LS +set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15} [get_ports gpio_sw[5]] ; ## GPIO_SW_E +set_property -dict {PACKAGE_PIN T5 IOSTANDARD SSTL15} [get_ports gpio_sw[6]] ; ## GPIO_SW_S +set_property -dict {PACKAGE_PIN R5 IOSTANDARD SSTL15} [get_ports gpio_sw[7]] ; ## GPIO_SW_W +set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15} [get_ports gpio_sw[8]] ; ## GPIO_SW_C +set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports gpio_led[0]] ; ## GPIO_LED_0_LS +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports gpio_led[1]] ; ## GPIO_LED_1_LS +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports gpio_led[2]] ; ## GPIO_LED_2_LS +set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports gpio_led[3]] ; ## GPIO_LED_3_LS # iic -set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS15} [get_ports iic_rstn] -set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS15 DRIVE 8 SLEW SLOW} [get_ports iic_scl] -set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS15 DRIVE 8 SLEW SLOW} [get_ports iic_sda] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports iic_rstn] +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW} [get_ports iic_sda] # hdmi @@ -108,7 +108,7 @@ set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS18} [get_ports spdif] create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/ui_clk] create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/ui_addn_clk_0] -create_clock -name m125_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ethernet_clkgen/clk_out_1] +create_clock -name m125_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ethernet_clkgen/clk_out1] create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0] create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1] diff --git a/projects/common/vc707/vc707_system_constr.xdc b/projects/common/vc707/vc707_system_constr.xdc index b1f9b77e7..2491b2a80 100644 --- a/projects/common/vc707/vc707_system_constr.xdc +++ b/projects/common/vc707/vc707_system_constr.xdc @@ -121,16 +121,12 @@ set_property -dict {PACKAGE_PIN AR23 IOSTANDARD LVCMOS18} [get_ports spdif] # clocks -create_clock -name ddr_clk -period 10.00 [get_nets i_system_wrapper/system_i/axi_ddr_cntrl_1_100mhz] -create_clock -name cpu_clk -period 10.00 [get_nets i_system_wrapper/system_i/proc_sys_clk_1_100mhz] -create_clock -name m200_clk -period 5.00 [get_nets i_system_wrapper/system_i/proc_sys_clk_1_200mhz] +create_clock -name cpu_clk -period 10.00 [get_nets i_system_wrapper/system_i/axi_ddr_cntrl/ui_clk] +create_clock -name m200_clk -period 5.00 [get_nets i_system_wrapper/system_i/axi_ddr_cntrl/ui_addn_clk_0] create_clock -name hdmi_clk -period 6.73 [get_nets i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s] -create_clock -name spdif_clk -period 50.00 [get_nets i_system_wrapper/system_i/sys_audio_clkgen_clk] +create_clock -name spdif_clk -period 50.00 [get_nets i_system_wrapper/system_i/sys_audio_clkgen/clk_out1] set_clock_groups -asynchronous -group {cpu_clk} set_clock_groups -asynchronous -group {m200_clk} set_clock_groups -asynchronous -group {hdmi_clk} set_clock_groups -asynchronous -group {spdif_clk} - - -