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fifo2s: bug fixes- on 64mhz dma clock

main
Rejeesh Kutty 2014-07-08 16:57:16 -04:00
parent b434fe6dd5
commit a9992f02b0
3 changed files with 17 additions and 3 deletions
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9
library/axi_fifo2s/axi_fifo2s_rd.v
View File

@ -134,6 +134,7 @@ module axi_fifo2s_rd (
// internal registers
reg [ 31:0] axi_rd_addr_h = 'd0;
reg axi_rd = 'd0;
reg axi_rd_active = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
@ -156,17 +157,23 @@ module axi_fifo2s_rd (
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_addr_h <= 'd0;
axi_rd <= 'd0;
axi_rd_active <= 'd0;
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
end else begin
if (axi_xfer_init == 1'b1) begin
axi_rd_addr_h <= AXI_ADDRESS;
end else if (axi_rd_req == 1'b1) begin
axi_rd_addr_h <= axi_rd_addr;
end
if (axi_rd_active == 1'b1) begin
axi_rd <= 1'b0;
if (axi_rlast == 1'b1) begin
axi_rd_active <= 1'b0;
end
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr)) begin
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
axi_rd <= 1'b1;
axi_rd_active <= 1'b1;
end

3
library/axi_fifo2s/axi_fifo2s_wr.v
View File

@ -82,6 +82,7 @@ module axi_fifo2s_wr (
axi_buser,
axi_bready,
// axi status
axi_dwovf,
@ -252,7 +253,7 @@ module axi_fifo2s_wr (
m_xfer_init <= m_xfer_req_m[1] & ~m_xfer_req_m[2];
if (m_xfer_init == 1'b1) begin
m_xfer_limit <= 1'd1;
end else if (m_xfer_addr >= AXI_ADDRLIMIT) begin
end else if ((m_xfer_addr >= AXI_ADDRLIMIT) || (m_xfer_enable == 1'b0)) begin
m_xfer_limit <= 1'd0;
end
if (m_xfer_init == 1'b1) begin

8
library/common/ad_axis_inf_rx.v
View File

@ -103,6 +103,10 @@ module ad_axis_inf_rx (
reg inf_last = 'd0;
reg [DW:0] inf_data = 'd0;
// internal signals
wire inf_ready_s;
// write interface
always @(posedge clk) begin
@ -147,13 +151,15 @@ module ad_axis_inf_rx (
// read interface
assign inf_ready_s = inf_ready | ~inf_valid;
always @(posedge clk) begin
if (rst == 1'b1) begin
rcnt <= 'd0;
inf_valid <= 'd0;
inf_last <= 'b0;
inf_data <= 'd0;
end else if ((inf_ready == 1'b1) || (inf_valid == 1'b0)) begin
end else if (inf_ready_s == 1'b1) begin
if (rcnt == wcnt) begin
rcnt <= rcnt;
inf_valid <= 1'd0;