axi_adrv9001: Let gate signals have initial value, useful for simulation

2021-01-05 07:17:00 +00:00 · 2021-01-05 07:17:00 +00:00 · aa180fb272
parent b85784ebe8
commit aa180fb272
1 changed files with 2 additions and 2 deletions
--- a/library/axi_adrv9001/axi_adrv9001_tdd.v
+++ b/library/axi_adrv9001/axi_adrv9001_tdd.v
@ -64,8 +64,8 @@ module axi_adrv9001_tdd #(

  // tx/rx data flow control

-  output  reg             tdd_tx_valid,
-  output  reg             tdd_rx_valid,
+  output  reg             tdd_tx_valid = 1'b1,
+  output  reg             tdd_rx_valid = 1'b1,

  // bus interface