From ca9f7bf1f62cf0bf0d262a2f0f79a422bcacf117 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 19 Sep 2014 09:47:25 -0400 Subject: [PATCH 1/3] axi_ad9234: axi_ad9680 copy --- library/axi_ad9234/axi_ad9234.v | 323 +++++++++++++++++++++++ library/axi_ad9234/axi_ad9234_channel.v | 183 +++++++++++++ library/axi_ad9234/axi_ad9234_constr.xdc | 6 + library/axi_ad9234/axi_ad9234_if.v | 132 +++++++++ library/axi_ad9234/axi_ad9234_ip.tcl | 29 ++ library/axi_ad9234/axi_ad9234_pnmon.v | 244 +++++++++++++++++ 6 files changed, 917 insertions(+) create mode 100644 library/axi_ad9234/axi_ad9234.v create mode 100644 library/axi_ad9234/axi_ad9234_channel.v create mode 100644 library/axi_ad9234/axi_ad9234_constr.xdc create mode 100644 library/axi_ad9234/axi_ad9234_if.v create mode 100644 library/axi_ad9234/axi_ad9234_ip.tcl create mode 100644 library/axi_ad9234/axi_ad9234_pnmon.v diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v new file mode 100644 index 000000000..efcf4c366 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234.v @@ -0,0 +1,323 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9680 ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // dma interface + + adc_clk, + adc_enable_0, + adc_valid_0, + adc_data_0, + adc_enable_1, + adc_valid_1, + adc_data_1, + adc_dovf, + adc_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [127:0] rx_data; + + // dma interface + + output adc_clk; + output adc_enable_0; + output adc_valid_0; + output [63:0] adc_data_0; + output adc_enable_1; + output adc_valid_1; + output [63:0] adc_data_1; + input adc_dovf; + input adc_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_ack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + + // internal signals + + wire [55:0] adc_data_a_s; + wire [55:0] adc_data_b_s; + wire adc_or_a_s; + wire adc_or_b_s; + wire adc_status_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire [31:0] up_rdata_s[0:2]; + wire up_ack_s[0:2]; + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // defaults + + assign adc_valid_0 = 1'b1; + assign adc_valid_1 = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata <= 'd0; + up_ack <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2]; + end + end + + // main (device interface) + + axi_ad9680_if i_if ( + .rx_clk (rx_clk), + .rx_data (rx_data), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_a (adc_data_a_s), + .adc_data_b (adc_data_b_s), + .adc_or_a (adc_or_a_s), + .adc_or_b (adc_or_b_s), + .adc_status (adc_status_s)); + + // channel + + axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_a_s), + .adc_or (adc_or_a_s), + .adc_dfmt_data (adc_data_0), + .adc_enable (adc_enable_0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[0]), + .up_ack (up_ack_s[0])); + + // channel + + axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_b_s), + .adc_or (adc_or_b_s), + .adc_dfmt_data (adc_data_1), + .adc_enable (adc_enable_1), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[1]), + .up_ack (up_ack_s[1])); + + // common processor control + + up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd40), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .delay_clk (1'b0), + .delay_rst (), + .delay_sel (), + .delay_rwn (), + .delay_addr (), + .delay_wdata (), + .delay_rdata (5'd0), + .delay_ack_t (1'b0), + .delay_locked (1'b1), + .drp_clk (1'd0), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[2]), + .up_ack (up_ack_s[2])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v new file mode 100644 index 000000000..b80395265 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_channel.v @@ -0,0 +1,183 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad9680_channel ( + + // adc interface + + adc_clk, + adc_rst, + adc_data, + adc_or, + + // channel interface + + adc_dfmt_data, + adc_enable, + up_adc_pn_err, + up_adc_pn_oos, + up_adc_or, + + // processor interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack); + + // parameters + + parameter IQSEL = 0; + parameter CHID = 0; + + // adc interface + + input adc_clk; + input adc_rst; + input [55:0] adc_data; + input adc_or; + + // channel interface + + output [63:0] adc_dfmt_data; + output adc_enable; + output up_adc_pn_err; + output up_adc_pn_oos; + output up_adc_or; + + // processor interface + + input up_rstn; + input up_clk; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + wire [ 3:0] adc_pnseq_sel_s; + + // instantiations + + axi_ad9680_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + genvar n; + generate + for (n = 0; n < 4; n = n + 1) begin: g_ad_datafmt_1 + ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*14+13:n*14]), + .valid_out (), + .data_out (adc_dfmt_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_constr.xdc b/library/axi_ad9234/axi_ad9234_constr.xdc new file mode 100644 index 000000000..f22d7bdfa --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_constr.xdc @@ -0,0 +1,6 @@ + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]] + + + diff --git a/library/axi_ad9234/axi_ad9234_if.v b/library/axi_ad9234/axi_ad9234_if.v new file mode 100644 index 000000000..c658b6b84 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_if.v @@ -0,0 +1,132 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface + +`timescale 1ns/100ps + +module axi_ad9680_if ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // adc data output + + adc_clk, + adc_rst, + adc_data_a, + adc_data_b, + adc_or_a, + adc_or_b, + adc_status); + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [127:0] rx_data; + + // adc data output + + output adc_clk; + input adc_rst; + output [55:0] adc_data_a; + output [55:0] adc_data_b; + output adc_or_a; + output adc_or_b; + output adc_status; + + // internal registers + + reg adc_status = 'd0; + + // internal signals + + wire [15:0] adc_data_a_s3_s; + wire [15:0] adc_data_a_s2_s; + wire [15:0] adc_data_a_s1_s; + wire [15:0] adc_data_a_s0_s; + wire [15:0] adc_data_b_s3_s; + wire [15:0] adc_data_b_s2_s; + wire [15:0] adc_data_b_s1_s; + wire [15:0] adc_data_b_s0_s; + + // adc clock is the reference clock + + assign adc_clk = rx_clk; + assign adc_or_a = 1'b0; + assign adc_or_b = 1'b0; + + // adc channels + + assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0], + adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]}; + + assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0], + adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]}; + + // data multiplex + + assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]}; + assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]}; + assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]}; + assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]}; + + assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]}; + assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]}; + assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]}; + assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]}; + + // status + + always @(posedge rx_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_ip.tcl b/library/axi_ad9234/axi_ad9234_ip.tcl new file mode 100644 index 000000000..9426b317e --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_ip.tcl @@ -0,0 +1,29 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9680 +adi_ip_files axi_ad9680 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "axi_ad9680_pnmon.v" \ + "axi_ad9680_channel.v" \ + "axi_ad9680_if.v" \ + "axi_ad9680.v" ] + +adi_ip_properties axi_ad9680 +adi_ip_constraints axi_ad9680 [list \ + "axi_ad9680_constr.xdc" ] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9234/axi_ad9234_pnmon.v b/library/axi_ad9234/axi_ad9234_pnmon.v new file mode 100644 index 000000000..4e64ca0fb --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_pnmon.v @@ -0,0 +1,244 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9680_pnmon ( + + // adc interface + + adc_clk, + adc_data, + + // pn out of sync and error + + adc_pn_oos, + adc_pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + + adc_pnseq_sel); + + // adc interface + + input adc_clk; + input [55:0] adc_data; + + // pn out of sync and error + + output adc_pn_oos; + output adc_pn_err; + + // processor interface PN9 (0x0), PN23 (0x1) + + input [ 3:0] adc_pnseq_sel; + + // internal registers + + reg [55:0] adc_pn_data_in = 'd0; + reg [55:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [55:0] adc_pn_data_pn_s; + + // PN23 function + + function [55:0] pn23; + input [55:0] din; + reg [55:0] dout; + begin + dout[55] = din[22] ^ din[17]; + dout[54] = din[21] ^ din[16]; + dout[53] = din[20] ^ din[15]; + dout[52] = din[19] ^ din[14]; + dout[51] = din[18] ^ din[13]; + dout[50] = din[17] ^ din[12]; + dout[49] = din[16] ^ din[11]; + dout[48] = din[15] ^ din[10]; + dout[47] = din[14] ^ din[ 9]; + dout[46] = din[13] ^ din[ 8]; + dout[45] = din[12] ^ din[ 7]; + dout[44] = din[11] ^ din[ 6]; + dout[43] = din[10] ^ din[ 5]; + dout[42] = din[ 9] ^ din[ 4]; + dout[41] = din[ 8] ^ din[ 3]; + dout[40] = din[ 7] ^ din[ 2]; + dout[39] = din[ 6] ^ din[ 1]; + dout[38] = din[ 5] ^ din[ 0]; + dout[37] = din[ 4] ^ din[22] ^ din[17]; + dout[36] = din[ 3] ^ din[21] ^ din[16]; + dout[35] = din[ 2] ^ din[20] ^ din[15]; + dout[34] = din[ 1] ^ din[19] ^ din[14]; + dout[33] = din[ 0] ^ din[18] ^ din[13]; + dout[32] = din[22] ^ din[12]; + dout[31] = din[21] ^ din[11]; + dout[30] = din[20] ^ din[10]; + dout[29] = din[19] ^ din[ 9]; + dout[28] = din[18] ^ din[ 8]; + dout[27] = din[17] ^ din[ 7]; + dout[26] = din[16] ^ din[ 6]; + dout[25] = din[15] ^ din[ 5]; + dout[24] = din[14] ^ din[ 4]; + dout[23] = din[13] ^ din[ 3]; + dout[22] = din[12] ^ din[ 2]; + dout[21] = din[11] ^ din[ 1]; + dout[20] = din[10] ^ din[ 0]; + dout[19] = din[ 9] ^ din[22] ^ din[17]; + dout[18] = din[ 8] ^ din[21] ^ din[16]; + dout[17] = din[ 7] ^ din[20] ^ din[15]; + dout[16] = din[ 6] ^ din[19] ^ din[14]; + dout[15] = din[ 5] ^ din[18] ^ din[13]; + dout[14] = din[ 4] ^ din[17] ^ din[12]; + dout[13] = din[ 3] ^ din[16] ^ din[11]; + dout[12] = din[ 2] ^ din[15] ^ din[10]; + dout[11] = din[ 1] ^ din[14] ^ din[ 9]; + dout[10] = din[ 0] ^ din[13] ^ din[ 8]; + dout[ 9] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; + dout[ 8] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; + dout[ 7] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; + dout[ 6] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; + dout[ 5] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; + dout[ 4] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; + dout[ 3] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; + dout[ 2] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; + dout[ 1] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17]; + dout[ 0] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [55:0] pn9; + input [55:0] din; + reg [55:0] dout; + begin + dout[55] = din[ 8] ^ din[ 4]; + dout[54] = din[ 7] ^ din[ 3]; + dout[53] = din[ 6] ^ din[ 2]; + dout[52] = din[ 5] ^ din[ 1]; + dout[51] = din[ 4] ^ din[ 0]; + dout[50] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[49] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[48] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[47] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[46] = din[ 8] ^ din[ 0]; + dout[45] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[44] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[43] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[42] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[41] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[40] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[39] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[38] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[37] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[36] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[35] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[34] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[33] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[32] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[31] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[30] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[29] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[28] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[27] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[26] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[25] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[24] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + dout[23] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2]; + dout[22] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[21] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0]; + dout[20] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[19] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3]; + dout[18] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2]; + dout[17] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[16] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0]; + dout[15] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8]; + dout[14] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7]; + dout[13] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6]; + dout[12] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5]; + dout[11] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4]; + dout[ 8] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 7] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 6] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 5] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0]; + dout[ 4] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8]; + dout[ 3] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7]; + dout[ 2] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6]; + dout[ 1] = din[ 3] ^ din[ 8] ^ din[ 5]; + dout[ 0] = din[ 2] ^ din[ 4] ^ din[ 7]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0], + ~adc_data[27], adc_data[26:14], + ~adc_data[41], adc_data[40:28], + ~adc_data[55], adc_data[54:42]}; + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #(.DATA_WIDTH(56)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (1'b1), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + From 0cb75671100892f520732284e199ea89777528fe Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 19 Sep 2014 09:53:47 -0400 Subject: [PATCH 2/3] fmcadc3: daq2 copy --- projects/fmcadc3/common/fmcadc3_bd.tcl | 508 ++++++++++++++++++++ projects/fmcadc3/common/fmcadc3_spi.v | 109 +++++ projects/fmcadc3/zc706/system_bd.tcl | 58 +++ projects/fmcadc3/zc706/system_constr.xdc | 74 +++ projects/fmcadc3/zc706/system_project.tcl | 17 + projects/fmcadc3/zc706/system_top.v | 537 ++++++++++++++++++++++ 6 files changed, 1303 insertions(+) create mode 100644 projects/fmcadc3/common/fmcadc3_bd.tcl create mode 100644 projects/fmcadc3/common/fmcadc3_spi.v create mode 100644 projects/fmcadc3/zc706/system_bd.tcl create mode 100644 projects/fmcadc3/zc706/system_constr.xdc create mode 100644 projects/fmcadc3/zc706/system_project.tcl create mode 100644 projects/fmcadc3/zc706/system_top.v diff --git a/projects/fmcadc3/common/fmcadc3_bd.tcl b/projects/fmcadc3/common/fmcadc3_bd.tcl new file mode 100644 index 000000000..d7f93512c --- /dev/null +++ b/projects/fmcadc3/common/fmcadc3_bd.tcl @@ -0,0 +1,508 @@ + + # daq2 + + set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] + set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + set spi_clk_i [create_bd_port -dir I spi_clk_i] + set spi_clk_o [create_bd_port -dir O spi_clk_o] + set spi_sdo_i [create_bd_port -dir I spi_sdo_i] + set spi_sdo_o [create_bd_port -dir O spi_sdo_o] + set spi_sdi_i [create_bd_port -dir I spi_sdi_i] + + set rx_ref_clk [create_bd_port -dir I rx_ref_clk] + set rx_sync [create_bd_port -dir O rx_sync] + set rx_sysref [create_bd_port -dir I rx_sysref] + set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] + set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] + + set tx_ref_clk [create_bd_port -dir I tx_ref_clk] + set tx_sync [create_bd_port -dir I tx_sync] + set tx_sysref [create_bd_port -dir I tx_sysref] + set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] + set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] + +if {$sys_zynq == 0} { + + set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] + set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] + set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] + set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] + set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] + set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] +} + + set dac_clk [create_bd_port -dir O dac_clk] + set dac_valid_0 [create_bd_port -dir O dac_valid_0] + set dac_enable_0 [create_bd_port -dir O dac_enable_0] + set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] + set dac_valid_1 [create_bd_port -dir O dac_valid_1] + set dac_enable_1 [create_bd_port -dir O dac_enable_1] + set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] + set dac_valid_2 [create_bd_port -dir O dac_valid_2] + set dac_enable_2 [create_bd_port -dir O dac_enable_2] + set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2] + set dac_valid_3 [create_bd_port -dir O dac_valid_3] + set dac_enable_3 [create_bd_port -dir O dac_enable_3] + set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3] + set dac_drd [create_bd_port -dir I dac_drd] + set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] + + set adc_clk [create_bd_port -dir O adc_clk] + set adc_enable_0 [create_bd_port -dir O adc_enable_0] + set adc_valid_0 [create_bd_port -dir O adc_valid_0] + set adc_data_0 [create_bd_port -dir O -from 63 -to 0 adc_data_0] + set adc_enable_1 [create_bd_port -dir O adc_enable_1] + set adc_valid_1 [create_bd_port -dir O adc_valid_1] + set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] + set adc_dwr [create_bd_port -dir I adc_dwr] + set adc_dsync [create_bd_port -dir I adc_dsync] + set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] + + # dac peripherals + + set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] + set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core + + set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9144_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd + + set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma + set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma + +if {$sys_zynq == 1} { + + set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect +} + + # adc peripherals + + set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + + set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9680_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + + set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma + +if {$sys_zynq == 1} { + + set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect +} + + # dac/adc common gt/gpio + + set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] + set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt + +if {$sys_zynq == 1} { + + set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect +} + + # gpio and spi + +if {$sys_zynq == 0} { + + set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_daq2_spi] + set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi + set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi + set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi + + set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] + set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio +} + + # additions to default configuration + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect + +} else { + + set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect +} + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect + set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc +} + +if {$sys_zynq == 1} { + + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + + set_property LEFT 42 [get_bd_ports GPIO_I] + set_property LEFT 42 [get_bd_ports GPIO_O] + set_property LEFT 42 [get_bd_ports GPIO_T] +} + + # connections (spi and gpio) + +if {$sys_zynq == 0} { + + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] + +} else { + set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat] + set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat + + set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc] + set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc + + connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O] + connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout] + connect_bd_net -net spi_csn_i [get_bd_pins sys_const_vcc/const] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] +} + +if {$sys_zynq == 0} { + + connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] + connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] + connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] + connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] + connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] + connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] +} + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2] + delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3] +} + + # connections (gt) + + connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] + connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] + connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] + connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] + connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] + connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] + connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] + connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] + + # connections (dac) + + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] + + connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] + connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] + connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] + connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] + connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] + connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] + connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] + connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] + connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] + connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0] + connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0] + connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0] + connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1] + connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1] + connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1] + connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2] + connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2] + connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2] + connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3] + connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3] + connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3] + connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] + connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] + connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] + connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] + + # connections (adc) + + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] + + connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] + connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] + connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] + connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] + connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] + connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] + connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] + connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] + connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] + connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] + connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] + connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] + connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] + connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] + connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] + connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] + connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] + connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] + connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] + connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + + # dac/adc clocks + + connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] + + # interconnect (cpu) + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] + + connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] + connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] +} + + # gt uses hp3, and 100MHz clock for both DRP and AXI4 + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] +} + + # memory interconnects share the same clock (fclk2) + +if {$sys_zynq == 1} { + set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] + + set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] + set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] + + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] + connect_bd_net -net sys_fmc_dma_async_reset \ + [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ + [get_bd_pins sys_ps7/FCLK_RESET2_N] + + connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source +} + + # interconnect (mem/dac) + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] +} + + # ila + + set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] + set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon + + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] + + set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_tx_mon] + set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon + + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] + + # address map + + create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt + create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd + create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd + create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma + create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio + create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi +} + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + +} else { + + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm +} + diff --git a/projects/fmcadc3/common/fmcadc3_spi.v b/projects/fmcadc3/common/fmcadc3_spi.v new file mode 100644 index 000000000..eb3e7d91e --- /dev/null +++ b/projects/fmcadc3/common/fmcadc3_spi.v @@ -0,0 +1,109 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module daq2_spi ( + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + spi_sdio); + + // 4 wire + + input [ 2:0] spi_csn; + input spi_clk; + input spi_mosi; + output spi_miso; + + // 3 wire + + inout spi_sdio; + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_s = & spi_csn; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= spi_count + 1'b1; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io butter + + IOBUF i_iobuf_sdio ( + .T (spi_enable_s), + .I (spi_mosi), + .O (spi_miso), + .IO (spi_sdio)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcadc3/zc706/system_bd.tcl b/projects/fmcadc3/zc706/system_bd.tcl new file mode 100644 index 000000000..177e09f7f --- /dev/null +++ b/projects/fmcadc3/zc706/system_bd.tcl @@ -0,0 +1,58 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl +source ../common/daq2_bd.tcl + +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma + +p_plddr3_fifo [current_bd_instance .] plddr3_fifo 128 + +set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] +set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] + +connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3] +connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk] + +delete_bd_objs [get_bd_nets axi_ad9680_adc_clk] +delete_bd_objs [get_bd_nets axi_ad9680_adc_dwr] +delete_bd_objs [get_bd_nets axi_ad9680_adc_ddata] +delete_bd_objs [get_bd_nets axi_ad9680_adc_dsync] +delete_bd_objs [get_bd_nets axi_ad9680_adc_dovf] + +connect_bd_net -net [get_bd_nets axi_daq2_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst] +connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] +connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] + +connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] +connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] +connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] +connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] + +connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] +connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] +connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] +connect_bd_net -net axi_ad9680_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] + +connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] +connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] + +set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon] +set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon +set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon +set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon +set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon + +connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins ila_dma_mon/clk] +connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins ila_dma_mon/probe0] +connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] +connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins ila_dma_mon/probe2] +connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status] + + +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr + diff --git a/projects/fmcadc3/zc706/system_constr.xdc b/projects/fmcadc3/zc706/system_constr.xdc new file mode 100644 index 000000000..ff599d9e8 --- /dev/null +++ b/projects/fmcadc3/zc706/system_constr.xdc @@ -0,0 +1,74 @@ + +# daq2 + +set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N +set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P +set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P + +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P + +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N + +# clocks + +create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] +create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] +create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] +create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk] +create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0] + +set_clock_groups -asynchronous -group {tx_div_clk} +set_clock_groups -asynchronous -group {rx_div_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} +set_clock_groups -asynchronous -group {pl_ddr_clk} +set_clock_groups -asynchronous -group {pl_dma_clk} + +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/fmcadc3/zc706/system_project.tcl b/projects/fmcadc3/zc706/system_project.tcl new file mode 100644 index 000000000..73e0af659 --- /dev/null +++ b/projects/fmcadc3/zc706/system_project.tcl @@ -0,0 +1,17 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create daq2_zc706 +adi_project_files daq2_zc706 [list \ + "../common/daq2_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run daq2_zc706 + + diff --git a/projects/fmcadc3/zc706/system_top.v b/projects/fmcadc3/zc706/system_top.v new file mode 100644 index 000000000..17917e91c --- /dev/null +++ b/projects/fmcadc3/zc706/system_top.v @@ -0,0 +1,537 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + sys_clk_p, + sys_clk_n, + + DDR3_addr, + DDR3_ba, + DDR3_cas_n, + DDR3_ck_n, + DDR3_ck_p, + DDR3_cke, + DDR3_cs_n, + DDR3_dm, + DDR3_dq, + DDR3_dqs_n, + DDR3_dqs_p, + DDR3_odt, + DDR3_ras_n, + DDR3_reset_n, + DDR3_we_n, + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + tx_ref_clk_p, + tx_ref_clk_n, + tx_sysref_p, + tx_sysref_n, + tx_sync_p, + tx_sync_n, + tx_data_p, + tx_data_n, + + adc_fdb, + adc_fda, + dac_irq, + clkd_status, + + adc_pd, + dac_txen, + dac_reset, + clkd_pd, + clkd_sync, + clkd_reset, + + spi_csn_clk, + spi_csn_dac, + spi_csn_adc, + spi_clk, + spi_sdio); + + input sys_clk_p; + input sys_clk_n; + + output [13:0] DDR3_addr; + output [ 2:0] DDR3_ba; + output DDR3_cas_n; + output [ 0:0] DDR3_ck_n; + output [ 0:0] DDR3_ck_p; + output [ 0:0] DDR3_cke; + output [ 0:0] DDR3_cs_n; + output [ 7:0] DDR3_dm; + inout [63:0] DDR3_dq; + inout [ 7:0] DDR3_dqs_n; + inout [ 7:0] DDR3_dqs_p; + output [ 0:0] DDR3_odt; + output DDR3_ras_n; + output DDR3_reset_n; + output DDR3_we_n; + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_ref_clk_p; + input rx_ref_clk_n; + input rx_sysref_p; + input rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + + input tx_ref_clk_p; + input tx_ref_clk_n; + input tx_sysref_p; + input tx_sysref_n; + input tx_sync_p; + input tx_sync_n; + output [ 3:0] tx_data_p; + output [ 3:0] tx_data_n; + + inout adc_fdb; + inout adc_fda; + inout dac_irq; + inout [ 1:0] clkd_status; + + inout adc_pd; + inout dac_txen; + inout dac_reset; + inout clkd_pd; + inout clkd_sync; + inout clkd_reset; + + output spi_csn_clk; + output spi_csn_dac; + output spi_csn_adc; + output spi_clk; + inout spi_sdio; + + // internal registers + + reg dac_drd = 'd0; + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg [63:0] dac_ddata_2 = 'd0; + reg [63:0] dac_ddata_3 = 'd0; + reg adc_dsync = 'd0; + reg adc_dwr = 'd0; + reg [127:0] adc_ddata = 'd0; + + // internal signals + + wire [42:0] gpio_i; + wire [42:0] gpio_o; + wire [42:0] gpio_t; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + wire [ 2:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire dac_clk; + wire [127:0] dac_ddata; + wire dac_enable_0; + wire dac_enable_1; + wire dac_enable_2; + wire dac_enable_3; + wire dac_valid_0; + wire dac_valid_1; + wire dac_valid_2; + wire dac_valid_3; + wire adc_clk; + wire [63:0] adc_data_0; + wire [63:0] adc_data_1; + wire adc_enable_0; + wire adc_enable_1; + wire adc_valid_0; + wire adc_valid_1; + + // adc-dac data + + always @(posedge dac_clk) begin + case ({dac_enable_1, dac_enable_0}) + 2'b11: begin + dac_drd <= dac_valid_0 & dac_valid_1; + dac_ddata_0[63:48] <= dac_ddata[111: 96]; + dac_ddata_0[47:32] <= dac_ddata[ 79: 64]; + dac_ddata_0[31:16] <= dac_ddata[ 47: 32]; + dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; + dac_ddata_1[63:48] <= dac_ddata[127:112]; + dac_ddata_1[47:32] <= dac_ddata[ 95: 80]; + dac_ddata_1[31:16] <= dac_ddata[ 63: 48]; + dac_ddata_1[15: 0] <= dac_ddata[ 31: 16]; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + 2'b10: begin + dac_drd <= dac_valid_1 & ~dac_drd; + dac_ddata_0 <= 64'd0; + if (dac_drd == 1'b1) begin + dac_ddata_1[63:48] <= dac_ddata[127:112]; + dac_ddata_1[47:32] <= dac_ddata[111: 96]; + dac_ddata_1[31:16] <= dac_ddata[ 95: 80]; + dac_ddata_1[15: 0] <= dac_ddata[ 79: 64]; + end else begin + dac_ddata_1[63:48] <= dac_ddata[ 63: 48]; + dac_ddata_1[47:32] <= dac_ddata[ 47: 32]; + dac_ddata_1[31:16] <= dac_ddata[ 31: 16]; + dac_ddata_1[15: 0] <= dac_ddata[ 15: 0]; + end + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + 2'b01: begin + dac_drd <= dac_valid_0 & ~dac_drd; + if (dac_drd == 1'b1) begin + dac_ddata_0[63:48] <= dac_ddata[127:112]; + dac_ddata_0[47:32] <= dac_ddata[111: 96]; + dac_ddata_0[31:16] <= dac_ddata[ 95: 80]; + dac_ddata_0[15: 0] <= dac_ddata[ 79: 64]; + end else begin + dac_ddata_0[63:48] <= dac_ddata[ 63: 48]; + dac_ddata_0[47:32] <= dac_ddata[ 47: 32]; + dac_ddata_0[31:16] <= dac_ddata[ 31: 16]; + dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; + end + dac_ddata_1 <= 64'd0; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + default: begin + dac_drd <= 1'b0; + dac_ddata_0 <= 64'd0; + dac_ddata_1 <= 64'd0; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + endcase + end + + always @(posedge adc_clk) begin + case ({adc_enable_1, adc_enable_0}) + 2'b11: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_1 & adc_valid_0; + adc_ddata[127:112] <= adc_data_1[63:48]; + adc_ddata[111: 96] <= adc_data_0[63:48]; + adc_ddata[ 95: 80] <= adc_data_1[47:32]; + adc_ddata[ 79: 64] <= adc_data_0[47:32]; + adc_ddata[ 63: 48] <= adc_data_1[31:16]; + adc_ddata[ 47: 32] <= adc_data_0[31:16]; + adc_ddata[ 31: 16] <= adc_data_1[15: 0]; + adc_ddata[ 15: 0] <= adc_data_0[15: 0]; + end + 2'b10: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_1 & ~adc_dwr; + adc_ddata[127:112] <= adc_data_1[63:48]; + adc_ddata[111: 96] <= adc_data_1[47:32]; + adc_ddata[ 95: 80] <= adc_data_1[31:16]; + adc_ddata[ 79: 64] <= adc_data_1[15: 0]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + 2'b01: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_0 & ~adc_dwr; + adc_ddata[127:112] <= adc_data_0[63:48]; + adc_ddata[111: 96] <= adc_data_0[47:32]; + adc_ddata[ 95: 80] <= adc_data_0[31:16]; + adc_ddata[ 79: 64] <= adc_data_0[15: 0]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + default: begin + adc_dsync <= 1'b0; + adc_dwr <= 1'b0; + adc_ddata <= 128'd0; + end + endcase + end + + // spi + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE2 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq2_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + ad_iobuf #(.DATA_WIDTH(26)) i_iobuf ( + .dt ({gpio_t[42:32], gpio_t[14:0]}), + .di ({gpio_o[42:32], gpio_o[14:0]}), + .do ({gpio_i[42:32], gpio_i[14:0]}), + .dio ({ adc_pd, // 42 + dac_txen, // 41 + dac_reset, // 40 + clkd_pd, // 39 + clkd_sync, // 38 + clkd_reset, // 37 + adc_fdb, // 36 + adc_fda, // 35 + dac_irq, // 34 + clkd_status, // 32 + gpio_bd})); // 0 + + system_wrapper i_system_wrapper ( + .DDR3_addr (DDR3_addr), + .DDR3_ba (DDR3_ba), + .DDR3_cas_n (DDR3_cas_n), + .DDR3_ck_n (DDR3_ck_n), + .DDR3_ck_p (DDR3_ck_p), + .DDR3_cke (DDR3_cke), + .DDR3_cs_n (DDR3_cs_n), + .DDR3_dm (DDR3_dm), + .DDR3_dq (DDR3_dq), + .DDR3_dqs_n (DDR3_dqs_n), + .DDR3_dqs_p (DDR3_dqs_p), + .DDR3_odt (DDR3_odt), + .DDR3_ras_n (DDR3_ras_n), + .DDR3_reset_n (DDR3_reset_n), + .DDR3_we_n (DDR3_we_n), + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .adc_clk (adc_clk), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_ddata (adc_ddata), + .adc_dsync (adc_dsync), + .adc_dwr (adc_dwr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .dac_clk (dac_clk), + .dac_ddata (dac_ddata), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_ddata_2 (dac_ddata_2), + .dac_ddata_3 (dac_ddata_3), + .dac_drd (dac_drd), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), + .dac_enable_2 (dac_enable_2), + .dac_enable_3 (dac_enable_3), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), + .dac_valid_2 (dac_valid_2), + .dac_valid_3 (dac_valid_3), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .tx_data_n (tx_data_n), + .tx_data_p (tx_data_p), + .tx_ref_clk (tx_ref_clk), + .tx_sync (tx_sync), + .tx_sysref (tx_sysref)); + +endmodule + +// *************************************************************************** +// *************************************************************************** From 07f5795255874eb82544f21dfc5cc33979e6a516 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 22 Sep 2014 11:17:20 -0400 Subject: [PATCH 3/3] fmcadc3: initial updates --- library/axi_ad9234/axi_ad9234.v | 8 +- library/axi_ad9234/axi_ad9234_channel.v | 4 +- library/axi_ad9234/axi_ad9234_if.v | 2 +- library/axi_ad9234/axi_ad9234_ip.tcl | 18 +- library/axi_ad9234/axi_ad9234_pnmon.v | 2 +- projects/fmcadc3/common/fmcadc3_bd.tcl | 531 +++++++++------------- projects/fmcadc3/common/fmcadc3_spi.v | 10 +- projects/fmcadc3/zc706/system_bd.tcl | 59 ++- projects/fmcadc3/zc706/system_constr.xdc | 98 ++-- projects/fmcadc3/zc706/system_project.tcl | 8 +- projects/fmcadc3/zc706/system_top.v | 395 +++++++--------- 11 files changed, 484 insertions(+), 651 deletions(-) diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v index efcf4c366..657573eff 100644 --- a/library/axi_ad9234/axi_ad9234.v +++ b/library/axi_ad9234/axi_ad9234.v @@ -39,7 +39,7 @@ `timescale 1ns/100ps -module axi_ad9680 ( +module axi_ad9234 ( // jesd interface // rx_clk is (line-rate/40) @@ -187,7 +187,7 @@ module axi_ad9680 ( // main (device interface) - axi_ad9680_if i_if ( + axi_ad9234_if i_if ( .rx_clk (rx_clk), .rx_data (rx_data), .adc_clk (adc_clk), @@ -200,7 +200,7 @@ module axi_ad9680 ( // channel - axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + axi_ad9234_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_a_s), @@ -221,7 +221,7 @@ module axi_ad9680 ( // channel - axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + axi_ad9234_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_b_s), diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v index b80395265..89913a6e3 100644 --- a/library/axi_ad9234/axi_ad9234_channel.v +++ b/library/axi_ad9234/axi_ad9234_channel.v @@ -40,7 +40,7 @@ `timescale 1ns/100ps -module axi_ad9680_channel ( +module axi_ad9234_channel ( // adc interface @@ -110,7 +110,7 @@ module axi_ad9680_channel ( // instantiations - axi_ad9680_pnmon i_pnmon ( + axi_ad9234_pnmon i_pnmon ( .adc_clk (adc_clk), .adc_data (adc_data), .adc_pn_oos (adc_pn_oos_s), diff --git a/library/axi_ad9234/axi_ad9234_if.v b/library/axi_ad9234/axi_ad9234_if.v index c658b6b84..5f91208f0 100644 --- a/library/axi_ad9234/axi_ad9234_if.v +++ b/library/axi_ad9234/axi_ad9234_if.v @@ -40,7 +40,7 @@ `timescale 1ns/100ps -module axi_ad9680_if ( +module axi_ad9234_if ( // jesd interface // rx_clk is (line-rate/40) diff --git a/library/axi_ad9234/axi_ad9234_ip.tcl b/library/axi_ad9234/axi_ad9234_ip.tcl index 9426b317e..b1b75291f 100644 --- a/library/axi_ad9234/axi_ad9234_ip.tcl +++ b/library/axi_ad9234/axi_ad9234_ip.tcl @@ -3,8 +3,8 @@ source ../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip.tcl -adi_ip_create axi_ad9680 -adi_ip_files axi_ad9680 [list \ +adi_ip_create axi_ad9234 +adi_ip_files axi_ad9234 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ @@ -16,14 +16,14 @@ adi_ip_files axi_ad9680 [list \ "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ - "axi_ad9680_pnmon.v" \ - "axi_ad9680_channel.v" \ - "axi_ad9680_if.v" \ - "axi_ad9680.v" ] + "axi_ad9234_pnmon.v" \ + "axi_ad9234_channel.v" \ + "axi_ad9234_if.v" \ + "axi_ad9234.v" ] -adi_ip_properties axi_ad9680 -adi_ip_constraints axi_ad9680 [list \ - "axi_ad9680_constr.xdc" ] +adi_ip_properties axi_ad9234 +adi_ip_constraints axi_ad9234 [list \ + "axi_ad9234_constr.xdc" ] ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9234/axi_ad9234_pnmon.v b/library/axi_ad9234/axi_ad9234_pnmon.v index 4e64ca0fb..3e8f620c8 100644 --- a/library/axi_ad9234/axi_ad9234_pnmon.v +++ b/library/axi_ad9234/axi_ad9234_pnmon.v @@ -40,7 +40,7 @@ `timescale 1ns/100ps -module axi_ad9680_pnmon ( +module axi_ad9234_pnmon ( // adc interface diff --git a/projects/fmcadc3/common/fmcadc3_bd.tcl b/projects/fmcadc3/common/fmcadc3_bd.tcl index d7f93512c..aa5c9c71e 100644 --- a/projects/fmcadc3/common/fmcadc3_bd.tcl +++ b/projects/fmcadc3/common/fmcadc3_bd.tcl @@ -1,8 +1,19 @@ - # daq2 + # fmcadc3 + +if {$sys_zynq == 0} { set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + +} else { + + set spi_csn_0 [create_bd_port -dir O spi_csn_0] + set spi_csn_1 [create_bd_port -dir O spi_csn_1] + set spi_csn_2 [create_bd_port -dir O spi_csn_2] + set spi_csn_i [create_bd_port -dir I spi_csn_i] +} + set spi_clk_i [create_bd_port -dir I spi_clk_i] set spi_clk_o [create_bd_port -dir O spi_clk_o] set spi_sdo_i [create_bd_port -dir I spi_sdo_i] @@ -12,41 +23,22 @@ set rx_ref_clk [create_bd_port -dir I rx_ref_clk] set rx_sync [create_bd_port -dir O rx_sync] set rx_sysref [create_bd_port -dir I rx_sysref] - set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] - set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] - - set tx_ref_clk [create_bd_port -dir I tx_ref_clk] - set tx_sync [create_bd_port -dir I tx_sync] - set tx_sysref [create_bd_port -dir I tx_sysref] - set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] - set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] + set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] + set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] if {$sys_zynq == 0} { - set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] - set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] - set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] + set gpio_ctl_i [create_bd_port -dir I gpio_ctl_i] + set gpio_ctl_o [create_bd_port -dir O gpio_ctl_o] + set gpio_ctl_t [create_bd_port -dir O gpio_ctl_t] set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] } - set dac_clk [create_bd_port -dir O dac_clk] - set dac_valid_0 [create_bd_port -dir O dac_valid_0] - set dac_enable_0 [create_bd_port -dir O dac_enable_0] - set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] - set dac_valid_1 [create_bd_port -dir O dac_valid_1] - set dac_enable_1 [create_bd_port -dir O dac_enable_1] - set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] - set dac_valid_2 [create_bd_port -dir O dac_valid_2] - set dac_enable_2 [create_bd_port -dir O dac_enable_2] - set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2] - set dac_valid_3 [create_bd_port -dir O dac_valid_3] - set dac_enable_3 [create_bd_port -dir O dac_enable_3] - set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3] - set dac_drd [create_bd_port -dir I dac_drd] - set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] - + set gt_data [create_bd_port -dir O -from 255 -to 0 gt_data] + set gt_data_0 [create_bd_port -dir I -from 127 -to 0 gt_data_0] + set gt_data_1 [create_bd_port -dir I -from 127 -to 0 gt_data_1] set adc_clk [create_bd_port -dir O adc_clk] set adc_enable_0 [create_bd_port -dir O adc_enable_0] set adc_valid_0 [create_bd_port -dir O adc_valid_0] @@ -54,102 +46,81 @@ if {$sys_zynq == 0} { set adc_enable_1 [create_bd_port -dir O adc_enable_1] set adc_valid_1 [create_bd_port -dir O adc_valid_1] set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] + set adc_enable_2 [create_bd_port -dir O adc_enable_2] + set adc_valid_2 [create_bd_port -dir O adc_valid_2] + set adc_data_2 [create_bd_port -dir O -from 63 -to 0 adc_data_2] + set adc_enable_3 [create_bd_port -dir O adc_enable_3] + set adc_valid_3 [create_bd_port -dir O adc_valid_3] + set adc_data_3 [create_bd_port -dir O -from 63 -to 0 adc_data_3] set adc_dwr [create_bd_port -dir I adc_dwr] set adc_dsync [create_bd_port -dir I adc_dsync] - set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] - - # dac peripherals - - set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] - set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core - - set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9144_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd - set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd - - set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma - set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma - -if {$sys_zynq == 1} { - - set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect -} + set adc_ddata [create_bd_port -dir I -from 255 -to 0 adc_ddata] # adc peripherals - set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + set axi_ad9234_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9234:1.0 axi_ad9234_core_0] + set axi_ad9234_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9234:1.0 axi_ad9234_core_1] - set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9680_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd - set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + set axi_ad9234_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9234_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9234_jesd + set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9234_jesd - set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma + set axi_ad9234_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9234_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9234_dma if {$sys_zynq == 1} { - set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect + set axi_ad9234_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9234_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9234_dma_interconnect } # dac/adc common gt/gpio - set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] - set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt + set axi_fmcadc3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc3_gt] + set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_fmcadc3_gt if {$sys_zynq == 1} { - set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect + set axi_fmcadc3_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_fmcadc3_gt_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_fmcadc3_gt_interconnect } # gpio and spi if {$sys_zynq == 0} { - set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_daq2_spi] - set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi - set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi - set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi + set axi_fmcadc3_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_fmcadc3_spi] + set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcadc3_spi + set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_fmcadc3_spi + set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcadc3_spi - set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] - set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio + set axi_fmcadc3_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_fmcadc3_gpio] + set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_fmcadc3_gpio + set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_fmcadc3_gpio + set_property -dict [list CONFIG.C_GPIO2_WIDTH {1}] $axi_fmcadc3_gpio + set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_fmcadc3_gpio } # additions to default configuration if {$sys_zynq == 0} { - set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect + set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect } else { - set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect + set_property -dict [list CONFIG.NUM_MI {12}] $axi_cpu_interconnect } if {$sys_zynq == 0} { @@ -160,60 +131,53 @@ if {$sys_zynq == 0} { if {$sys_zynq == 1} { - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 - set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {38}] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 - set_property LEFT 42 [get_bd_ports GPIO_I] - set_property LEFT 42 [get_bd_ports GPIO_O] - set_property LEFT 42 [get_bd_ports GPIO_T] + set_property LEFT 37 [get_bd_ports GPIO_I] + set_property LEFT 37 [get_bd_ports GPIO_O] + set_property LEFT 37 [get_bd_ports GPIO_T] } # connections (spi and gpio) if {$sys_zynq == 0} { - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_fmcadc3_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_fmcadc3_spi/ss_o] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_fmcadc3_spi/sck_i] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_fmcadc3_spi/sck_o] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_fmcadc3_spi/io0_i] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_fmcadc3_spi/io0_o] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_fmcadc3_spi/io1_i] } else { - set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat] - set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat - set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc] - set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc - - connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O] - connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O] - connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout] - connect_bd_net -net spi_csn_i [get_bd_pins sys_const_vcc/const] [get_bd_pins sys_ps7/SPI0_SS_I] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] + connect_bd_net -net spi_csn_0 [get_bd_ports spi_csn_0] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_csn_1 [get_bd_ports spi_csn_1] [get_bd_pins sys_ps7/SPI0_SS1_O] + connect_bd_net -net spi_csn_2 [get_bd_ports spi_csn_2] [get_bd_pins sys_ps7/SPI0_SS2_O] + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] } if {$sys_zynq == 0} { - connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] - connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] - connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] - connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] - connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] - connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] + connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_fmcadc3_gpio/gpio_io_i] + connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_fmcadc3_gpio/gpio_io_o] + connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_fmcadc3_gpio/gpio_io_t] + connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_i] + connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_o] + connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_t] } if {$sys_zynq == 0} { @@ -224,169 +188,128 @@ if {$sys_zynq == 0} { # connections (gt) - connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] - connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] - connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] - connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] - connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] - connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] - connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] - connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] - connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] - connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] - - # connections (dac) - - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] - - connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] - connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] - connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] - connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] - connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] - connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] - connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] - connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] - connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] - connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] - connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0] - connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0] - connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0] - connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1] - connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1] - connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1] - connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2] - connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2] - connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2] - connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3] - connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3] - connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3] - connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] - connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] - connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] + connect_bd_net -net axi_fmcadc3_gt_ref_clk_q [get_bd_pins axi_fmcadc3_gt/ref_clk_q] [get_bd_ports rx_ref_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_data_p [get_bd_pins axi_fmcadc3_gt/rx_data_p] [get_bd_ports rx_data_p] + connect_bd_net -net axi_fmcadc3_gt_rx_data_n [get_bd_pins axi_fmcadc3_gt/rx_data_n] [get_bd_ports rx_data_n] + connect_bd_net -net axi_fmcadc3_gt_rx_sync [get_bd_pins axi_fmcadc3_gt/rx_sync] [get_bd_ports rx_sync] + connect_bd_net -net axi_fmcadc3_gt_rx_ext_sysref [get_bd_pins axi_fmcadc3_gt/rx_ext_sysref] [get_bd_ports rx_sysref] # connections (adc) - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_fmcadc3_gt/rx_clk_g] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_fmcadc3_gt/rx_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_core_0/rx_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_core_1/rx_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_jesd/rx_core_clk] - connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] - connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] - connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] - connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] - connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] - connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] - connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] - connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] - connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] - connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] - connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] - connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] - connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] - connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] - connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] - connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] - connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] - connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] - connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] - connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] - connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] - connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + connect_bd_net -net axi_fmcadc3_gt_rx_rst [get_bd_pins axi_fmcadc3_gt/rx_rst] [get_bd_pins axi_ad9234_jesd/rx_reset] + connect_bd_net -net axi_fmcadc3_gt_rx_sysref [get_bd_pins axi_fmcadc3_gt/rx_sysref] [get_bd_pins axi_ad9234_jesd/rx_sysref] + connect_bd_net -net axi_fmcadc3_gt_rx_gt_charisk [get_bd_pins axi_fmcadc3_gt/rx_gt_charisk] [get_bd_pins axi_ad9234_jesd/gt_rxcharisk_in] + connect_bd_net -net axi_fmcadc3_gt_rx_gt_disperr [get_bd_pins axi_fmcadc3_gt/rx_gt_disperr] [get_bd_pins axi_ad9234_jesd/gt_rxdisperr_in] + connect_bd_net -net axi_fmcadc3_gt_rx_gt_notintable [get_bd_pins axi_fmcadc3_gt/rx_gt_notintable] [get_bd_pins axi_ad9234_jesd/gt_rxnotintable_in] + connect_bd_net -net axi_fmcadc3_gt_rx_gt_data [get_bd_pins axi_fmcadc3_gt/rx_gt_data] [get_bd_pins axi_ad9234_jesd/gt_rxdata_in] + connect_bd_net -net axi_fmcadc3_gt_rx_rst_done [get_bd_pins axi_fmcadc3_gt/rx_rst_done] [get_bd_pins axi_ad9234_jesd/rx_reset_done] + connect_bd_net -net axi_fmcadc3_gt_rx_ip_comma_align [get_bd_pins axi_fmcadc3_gt/rx_ip_comma_align] [get_bd_pins axi_ad9234_jesd/rxencommaalign_out] + connect_bd_net -net axi_fmcadc3_gt_rx_ip_sync [get_bd_pins axi_fmcadc3_gt/rx_ip_sync] [get_bd_pins axi_ad9234_jesd/rx_sync] + connect_bd_net -net axi_fmcadc3_gt_rx_ip_sof [get_bd_pins axi_fmcadc3_gt/rx_ip_sof] [get_bd_pins axi_ad9234_jesd/rx_start_of_frame] + connect_bd_net -net axi_fmcadc3_gt_rx_ip_data [get_bd_pins axi_fmcadc3_gt/rx_ip_data] [get_bd_pins axi_ad9234_jesd/rx_tdata] + connect_bd_net -net axi_fmcadc3_gt_rx_data [get_bd_pins axi_fmcadc3_gt/rx_data] [get_bd_ports gt_data] + connect_bd_net -net axi_fmcadc3_gt_0_rx_data [get_bd_pins axi_ad9234_core_0/rx_data] [get_bd_ports gt_data_0] + connect_bd_net -net axi_fmcadc3_gt_1_rx_data [get_bd_pins axi_ad9234_core_1/rx_data] [get_bd_ports gt_data_1] + connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins axi_ad9234_dma/fifo_wr_clk] + connect_bd_net -net axi_ad9234_0_adc_enable_0 [get_bd_pins axi_ad9234_core_0/adc_enable_0] [get_bd_ports adc_enable_0] + connect_bd_net -net axi_ad9234_0_adc_valid_0 [get_bd_pins axi_ad9234_core_0/adc_valid_0] [get_bd_ports adc_valid_0] + connect_bd_net -net axi_ad9234_0_adc_data_0 [get_bd_pins axi_ad9234_core_0/adc_data_0] [get_bd_ports adc_data_0] + connect_bd_net -net axi_ad9234_0_adc_enable_1 [get_bd_pins axi_ad9234_core_0/adc_enable_1] [get_bd_ports adc_enable_1] + connect_bd_net -net axi_ad9234_0_adc_valid_1 [get_bd_pins axi_ad9234_core_0/adc_valid_1] [get_bd_ports adc_valid_1] + connect_bd_net -net axi_ad9234_0_adc_data_1 [get_bd_pins axi_ad9234_core_0/adc_data_1] [get_bd_ports adc_data_1] + connect_bd_net -net axi_ad9234_1_adc_enable_0 [get_bd_pins axi_ad9234_core_1/adc_enable_0] [get_bd_ports adc_enable_2] + connect_bd_net -net axi_ad9234_1_adc_valid_0 [get_bd_pins axi_ad9234_core_1/adc_valid_0] [get_bd_ports adc_valid_2] + connect_bd_net -net axi_ad9234_1_adc_data_0 [get_bd_pins axi_ad9234_core_1/adc_data_0] [get_bd_ports adc_data_2] + connect_bd_net -net axi_ad9234_1_adc_enable_1 [get_bd_pins axi_ad9234_core_1/adc_enable_1] [get_bd_ports adc_enable_3] + connect_bd_net -net axi_ad9234_1_adc_valid_1 [get_bd_pins axi_ad9234_core_1/adc_valid_1] [get_bd_ports adc_valid_3] + connect_bd_net -net axi_ad9234_1_adc_data_1 [get_bd_pins axi_ad9234_core_1/adc_data_1] [get_bd_ports adc_data_3] + connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9234_dma/fifo_wr_en] + connect_bd_net -net axi_ad9234_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9234_dma/fifo_wr_sync] + connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9234_dma/fifo_wr_din] + connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins axi_ad9234_dma/fifo_wr_overflow] + connect_bd_net -net axi_ad9234_dma_irq [get_bd_pins axi_ad9234_dma/irq] [get_bd_pins sys_concat_intc/In2] # dac/adc clocks - connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk] - connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] + connect_bd_net -net axi_ad9234_adc_clk [get_bd_ports adc_clk] # interconnect (cpu) - connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9234_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9234_core_0/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9234_core_1/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9234_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_fmcadc3_gt/s_axi] connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_core_0/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_core_1/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_dma/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_core_0/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_core_1/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_dma/s_axi_aresetn] if {$sys_zynq == 0} { - connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_fmcadc3_spi/axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_fmcadc3_gpio/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_spi/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_spi/ext_spi_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gpio/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_spi/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gpio/s_axi_aresetn] - connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] - connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] + connect_bd_net -net axi_fmcadc3_spi_irq [get_bd_pins axi_fmcadc3_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] + connect_bd_net -net axi_fmcadc3_gpio_irq [get_bd_pins axi_fmcadc3_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] } # gt uses hp3, and 100MHz clock for both DRP and AXI4 if {$sys_zynq == 0} { - connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_fmcadc3_gt/m_axi] connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/drp_clk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/m_axi_aresetn] } else { - connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] - connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_intf_net -intf_net axi_fmcadc3_gt_interconnect_m00_axi [get_bd_intf_pins axi_fmcadc3_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_fmcadc3_gt_interconnect_s00_axi [get_bd_intf_pins axi_fmcadc3_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_fmcadc3_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/S00_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/m_axi_aresetn] } # memory interconnects share the same clock (fclk2) @@ -410,99 +333,67 @@ if {$sys_zynq == 1} { if {$sys_zynq == 0} { - connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9234_dma/m_dest_axi] connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] - - connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] } else { - connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] - connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] - - connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] - connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_intf_net -intf_net axi_ad9234_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9234_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_ad9234_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9234_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9234_dma/m_dest_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] } # ila - set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] + set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] + set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_jesd_rx_mon - connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] - connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] - connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] - connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] - connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] - - set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_tx_mon] - set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon - - connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] - connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] - connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] - connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] + connect_bd_net -net axi_fmcadc3_gt_rx_mon_data [get_bd_pins axi_fmcadc3_gt/rx_mon_data] + connect_bd_net -net axi_fmcadc3_gt_rx_mon_trigger [get_bd_pins axi_fmcadc3_gt/rx_mon_trigger] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] + connect_bd_net -net axi_fmcadc3_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] + connect_bd_net -net axi_fmcadc3_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] + connect_bd_net -net axi_fmcadc3_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] + connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] # address map - create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt - create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd - create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd - create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma - create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma + create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_core_0/s_axi/axi_lite] SEG_data_ad9234_0_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_core_1/s_axi/axi_lite] SEG_data_ad9234_1_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_gt/s_axi/axi_lite] SEG_data_fmcadc3_gt + create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_jesd/s_axi/Reg] SEG_data_ad9234_jesd + create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_dma/s_axi/axi_lite] SEG_data_ad9234_dma if {$sys_zynq == 0} { - create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio - create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_gpio/S_AXI/Reg] SEG_data_fmcadc3_gpio + create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_spi/axi_lite/Reg] SEG_data_fmcadc3_spi } if {$sys_zynq == 0} { - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9234_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_fmcadc3_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl } else { - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9234_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_fmcadc3_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm } diff --git a/projects/fmcadc3/common/fmcadc3_spi.v b/projects/fmcadc3/common/fmcadc3_spi.v index eb3e7d91e..a038044cf 100644 --- a/projects/fmcadc3/common/fmcadc3_spi.v +++ b/projects/fmcadc3/common/fmcadc3_spi.v @@ -39,7 +39,9 @@ module daq2_spi ( - spi_csn, + ad9528_csn, + ad9234_1_csn, + ad9234_2_csn, spi_clk, spi_mosi, spi_miso, @@ -48,7 +50,9 @@ module daq2_spi ( // 4 wire - input [ 2:0] spi_csn; + input ad9528_csn; + input ad9234_1_csn; + input ad9234_2_csn; input spi_clk; input spi_mosi; output spi_miso; @@ -70,7 +74,7 @@ module daq2_spi ( // check on rising edge and change on falling edge - assign spi_csn_s = & spi_csn; + assign spi_csn_s = ad9528_csn & ad9234_1_csn & ad9234_2_csn; assign spi_enable_s = spi_enable & ~spi_csn_s; always @(posedge spi_clk or posedge spi_csn_s) begin diff --git a/projects/fmcadc3/zc706/system_bd.tcl b/projects/fmcadc3/zc706/system_bd.tcl index 177e09f7f..09cfe6587 100644 --- a/projects/fmcadc3/zc706/system_bd.tcl +++ b/projects/fmcadc3/zc706/system_bd.tcl @@ -1,14 +1,12 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl -source ../common/daq2_bd.tcl +source ../common/fmcadc3_bd.tcl -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9234_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9234_dma -p_plddr3_fifo [current_bd_instance .] plddr3_fifo 128 +p_plddr3_fifo [current_bd_instance .] plddr3_fifo 256 set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] @@ -16,41 +14,42 @@ set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clo connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk] -delete_bd_objs [get_bd_nets axi_ad9680_adc_clk] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dwr] -delete_bd_objs [get_bd_nets axi_ad9680_adc_ddata] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dsync] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dovf] +delete_bd_objs [get_bd_nets axi_ad9234_adc_clk] +delete_bd_objs [get_bd_nets axi_ad9234_adc_dwr] +delete_bd_objs [get_bd_nets axi_ad9234_adc_ddata] +delete_bd_objs [get_bd_nets axi_ad9234_adc_dsync] +delete_bd_objs [get_bd_nets axi_ad9234_adc_dovf] -connect_bd_net -net [get_bd_nets axi_daq2_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst] -connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] -connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] +connect_bd_net -net [get_bd_nets axi_fmcadc3_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_fmcadc3_gt/rx_rst] +connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] +connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins axi_ad9234_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] -connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] -connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] -connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] -connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] +connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] +connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] +connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] +connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] -connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] -connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] -connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] -connect_bd_net -net axi_ad9680_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] +connect_bd_net -net axi_ad9234_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9234_dma/fifo_wr_clk] +connect_bd_net -net axi_ad9234_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9234_dma/fifo_wr_en] +connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9234_dma/fifo_wr_din] +connect_bd_net -net axi_ad9234_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9234_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9234_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9234_dma/fifo_wr_sync] -connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] -connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] +connect_bd_net -net axi_ad9234_adc_clk [get_bd_ports adc_clk] +connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] -set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon] +set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon] +set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon -connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins ila_dma_mon/clk] -connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins ila_dma_mon/probe0] -connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] -connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins ila_dma_mon/probe2] +connect_bd_net -net axi_ad9234_dma_clk [get_bd_pins ila_dma_mon/clk] +connect_bd_net -net axi_ad9234_dma_dwr [get_bd_pins ila_dma_mon/probe0] +connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] +connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins ila_dma_mon/probe2] connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status] diff --git a/projects/fmcadc3/zc706/system_constr.xdc b/projects/fmcadc3/zc706/system_constr.xdc index ff599d9e8..9b8b8a799 100644 --- a/projects/fmcadc3/zc706/system_constr.xdc +++ b/projects/fmcadc3/zc706/system_constr.xdc @@ -1,74 +1,58 @@ -# daq2 +# fmcadc3 -set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P -set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N -set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[0]] ; ## A14 FMC_HPC_DP4_M2C_P +set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[0]] ; ## A15 FMC_HPC_DP4_M2C_N +set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[1]] ; ## A18 FMC_HPC_DP5_M2C_P +set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[1]] ; ## A19 FMC_HPC_DP5_M2C_N +set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[2]] ; ## B16 FMC_HPC_DP6_M2C_P +set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[2]] ; ## B17 FMC_HPC_DP6_M2C_N +set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[3]] ; ## B12 FMC_HPC_DP7_M2C_P +set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[3]] ; ## B13 FMC_HPC_DP7_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[4]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[4]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[5]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[5]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[6]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[6]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[7]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[7]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports rx_sync_0_p] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports rx_sync_0_n] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_n] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P -set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N -set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P -set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N -set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P -set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N -set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P -set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports ad9528_csn] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports ada4961_1a_csn] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports ada4961_1b_csn] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports ad9234_1_csn] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports ada4961_2a_csn] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports ada4961_2b_csn] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports ad9234_2_csn] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P - -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P - -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports ad9528_rstn] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports ad9528_status] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports ad9234_1_fda] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports ad9234_1_fdb] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9234_2_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9234_2_fdb] ; ## H17 FMC_HPC_LA11_N # clocks -create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] -create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] +create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcadc3_gt_rx_clk] create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk] create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0] -set_clock_groups -asynchronous -group {tx_div_clk} set_clock_groups -asynchronous -group {rx_div_clk} set_clock_groups -asynchronous -group {fmc_dma_clk} set_clock_groups -asynchronous -group {pl_ddr_clk} set_clock_groups -asynchronous -group {pl_dma_clk} -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/fmcadc3/zc706/system_project.tcl b/projects/fmcadc3/zc706/system_project.tcl index 73e0af659..8df512560 100644 --- a/projects/fmcadc3/zc706/system_project.tcl +++ b/projects/fmcadc3/zc706/system_project.tcl @@ -4,14 +4,14 @@ source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl -adi_project_create daq2_zc706 -adi_project_files daq2_zc706 [list \ - "../common/daq2_spi.v" \ +adi_project_create fmcadc3_zc706 +adi_project_files fmcadc3_zc706 [list \ + "../common/fmcadc3_spi.v" \ "system_top.v" \ "system_constr.xdc"\ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -adi_project_run daq2_zc706 +adi_project_run fmcadc3_zc706 diff --git a/projects/fmcadc3/zc706/system_top.v b/projects/fmcadc3/zc706/system_top.v index 17917e91c..089932a70 100644 --- a/projects/fmcadc3/zc706/system_top.v +++ b/projects/fmcadc3/zc706/system_top.v @@ -100,35 +100,27 @@ module system_top ( rx_ref_clk_n, rx_sysref_p, rx_sysref_n, - rx_sync_p, - rx_sync_n, + rx_sync_0_p, + rx_sync_0_n, + rx_sync_1_p, + rx_sync_1_n, rx_data_p, rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync_p, - tx_sync_n, - tx_data_p, - tx_data_n, - - adc_fdb, - adc_fda, - dac_irq, - clkd_status, - - adc_pd, - dac_txen, - dac_reset, - clkd_pd, - clkd_sync, - clkd_reset, + ad9528_rstn, + ad9528_status, + ad9234_1_fda; + ad9234_1_fdb; + ad9234_2_fda; + ad9234_2_fdb; - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, + ad9528_csn, + ada4961_1a_csn, + ada4961_1b_csn, + ad9234_1_csn, + ada4961_2a_csn, + ada4961_2b_csn, + ad9234_2_csn, spi_clk, spi_sdio); @@ -191,175 +183,162 @@ module system_top ( input rx_ref_clk_n; input rx_sysref_p; input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; + output rx_sync_0_p; + output rx_sync_0_n; + output rx_sync_1_p; + output rx_sync_1_n; + input [ 7:0] rx_data_p; + input [ 7:0] rx_data_n; - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync_p; - input tx_sync_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; + inout ad9528_rstn; + inout ad9528_status; + inout ad9234_1_fda; + inout ad9234_1_fdb; + inout ad9234_2_fda; + inout ad9234_2_fdb; - inout adc_fdb; - inout adc_fda; - inout dac_irq; - inout [ 1:0] clkd_status; - - inout adc_pd; - inout dac_txen; - inout dac_reset; - inout clkd_pd; - inout clkd_sync; - inout clkd_reset; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; + output ad9528_csn; + output ada4961_1a_csn; + output ada4961_1b_csn; + output ad9234_1_csn; + output ada4961_2a_csn; + output ada4961_2b_csn; + output ad9234_2_csn; output spi_clk; inout spi_sdio; // internal registers - reg dac_drd = 'd0; - reg [63:0] dac_ddata_0 = 'd0; - reg [63:0] dac_ddata_1 = 'd0; - reg [63:0] dac_ddata_2 = 'd0; - reg [63:0] dac_ddata_3 = 'd0; + reg [ 1:0] adc_dcnt = 'd0; reg adc_dsync = 'd0; reg adc_dwr = 'd0; - reg [127:0] adc_ddata = 'd0; + reg [255:0] adc_ddata = 'd0; // internal signals - wire [42:0] gpio_i; - wire [42:0] gpio_o; - wire [42:0] gpio_t; + wire [37:0] gpio_i; + wire [37:0] gpio_o; + wire [37:0] gpio_t; wire rx_ref_clk; wire rx_sysref; wire rx_sync; - wire tx_ref_clk; - wire tx_sysref; - wire tx_sync; - wire [ 2:0] spi_csn; wire spi_mosi; wire spi_miso; - wire dac_clk; - wire [127:0] dac_ddata; - wire dac_enable_0; - wire dac_enable_1; - wire dac_enable_2; - wire dac_enable_3; - wire dac_valid_0; - wire dac_valid_1; - wire dac_valid_2; - wire dac_valid_3; wire adc_clk; wire [63:0] adc_data_0; wire [63:0] adc_data_1; + wire [63:0] adc_data_2; + wire [63:0] adc_data_3; wire adc_enable_0; wire adc_enable_1; + wire adc_enable_2; + wire adc_enable_3; wire adc_valid_0; wire adc_valid_1; + wire adc_valid_2; + wire adc_valid_3; + wire [255:0] gt_data; - // adc-dac data - - always @(posedge dac_clk) begin - case ({dac_enable_1, dac_enable_0}) - 2'b11: begin - dac_drd <= dac_valid_0 & dac_valid_1; - dac_ddata_0[63:48] <= dac_ddata[111: 96]; - dac_ddata_0[47:32] <= dac_ddata[ 79: 64]; - dac_ddata_0[31:16] <= dac_ddata[ 47: 32]; - dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; - dac_ddata_1[63:48] <= dac_ddata[127:112]; - dac_ddata_1[47:32] <= dac_ddata[ 95: 80]; - dac_ddata_1[31:16] <= dac_ddata[ 63: 48]; - dac_ddata_1[15: 0] <= dac_ddata[ 31: 16]; - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - 2'b10: begin - dac_drd <= dac_valid_1 & ~dac_drd; - dac_ddata_0 <= 64'd0; - if (dac_drd == 1'b1) begin - dac_ddata_1[63:48] <= dac_ddata[127:112]; - dac_ddata_1[47:32] <= dac_ddata[111: 96]; - dac_ddata_1[31:16] <= dac_ddata[ 95: 80]; - dac_ddata_1[15: 0] <= dac_ddata[ 79: 64]; - end else begin - dac_ddata_1[63:48] <= dac_ddata[ 63: 48]; - dac_ddata_1[47:32] <= dac_ddata[ 47: 32]; - dac_ddata_1[31:16] <= dac_ddata[ 31: 16]; - dac_ddata_1[15: 0] <= dac_ddata[ 15: 0]; - end - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - 2'b01: begin - dac_drd <= dac_valid_0 & ~dac_drd; - if (dac_drd == 1'b1) begin - dac_ddata_0[63:48] <= dac_ddata[127:112]; - dac_ddata_0[47:32] <= dac_ddata[111: 96]; - dac_ddata_0[31:16] <= dac_ddata[ 95: 80]; - dac_ddata_0[15: 0] <= dac_ddata[ 79: 64]; - end else begin - dac_ddata_0[63:48] <= dac_ddata[ 63: 48]; - dac_ddata_0[47:32] <= dac_ddata[ 47: 32]; - dac_ddata_0[31:16] <= dac_ddata[ 31: 16]; - dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; - end - dac_ddata_1 <= 64'd0; - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - default: begin - dac_drd <= 1'b0; - dac_ddata_0 <= 64'd0; - dac_ddata_1 <= 64'd0; - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - endcase - end + // adc-pack place holder always @(posedge adc_clk) begin - case ({adc_enable_1, adc_enable_0}) - 2'b11: begin + adc_dcnt <= adc_dcnt + 1'b1; + case ({adc_enable_3, adc_enable_2, adc_enable_1, adc_enable_0}) + 4'b1111: begin adc_dsync <= 1'b1; - adc_dwr <= adc_valid_1 & adc_valid_0; - adc_ddata[127:112] <= adc_data_1[63:48]; - adc_ddata[111: 96] <= adc_data_0[63:48]; - adc_ddata[ 95: 80] <= adc_data_1[47:32]; - adc_ddata[ 79: 64] <= adc_data_0[47:32]; - adc_ddata[ 63: 48] <= adc_data_1[31:16]; - adc_ddata[ 47: 32] <= adc_data_0[31:16]; + adc_dwr <= adc_valid_3 & adc_valid_2 & adc_valid_1 & adc_valid_0; + adc_ddata[255:240] <= adc_data_3[63:48]; + adc_ddata[239:224] <= adc_data_2[63:48]; + adc_ddata[223:208] <= adc_data_1[63:48]; + adc_ddata[207:192] <= adc_data_0[63:48]; + adc_ddata[191:176] <= adc_data_3[47:32]; + adc_ddata[175:160] <= adc_data_2[47:32]; + adc_ddata[159:144] <= adc_data_1[47:32]; + adc_ddata[143:128] <= adc_data_0[47:32]; + adc_ddata[127:112] <= adc_data_3[31:16]; + adc_ddata[111: 96] <= adc_data_2[31:16]; + adc_ddata[ 95: 80] <= adc_data_1[31:16]; + adc_ddata[ 79: 64] <= adc_data_0[31:16]; + adc_ddata[ 63: 48] <= adc_data_3[15: 0]; + adc_ddata[ 47: 32] <= adc_data_2[15: 0]; adc_ddata[ 31: 16] <= adc_data_1[15: 0]; adc_ddata[ 15: 0] <= adc_data_0[15: 0]; end - 2'b10: begin + 4'b0001: begin adc_dsync <= 1'b1; - adc_dwr <= adc_valid_1 & ~adc_dwr; - adc_ddata[127:112] <= adc_data_1[63:48]; - adc_ddata[111: 96] <= adc_data_1[47:32]; - adc_ddata[ 95: 80] <= adc_data_1[31:16]; - adc_ddata[ 79: 64] <= adc_data_1[15: 0]; + adc_dwr <= adc_valid_0 & adc_dcnt[0] & adc_dcnt[1]; + adc_ddata[255:240] <= adc_data_0[63:48]; + adc_ddata[239:224] <= adc_data_0[47:32]; + adc_ddata[223:208] <= adc_data_0[31:16]; + adc_ddata[207:192] <= adc_data_0[15: 0]; + adc_ddata[191:176] <= adc_ddata[255:240]; + adc_ddata[175:160] <= adc_ddata[239:224]; + adc_ddata[159:144] <= adc_ddata[223:208]; + adc_ddata[143:128] <= adc_ddata[207:192]; + adc_ddata[127:112] <= adc_ddata[191:176]; + adc_ddata[111: 96] <= adc_ddata[175:160]; + adc_ddata[ 95: 80] <= adc_ddata[159:144]; + adc_ddata[ 79: 64] <= adc_ddata[143:128]; adc_ddata[ 63: 48] <= adc_ddata[127:112]; adc_ddata[ 47: 32] <= adc_ddata[111: 96]; adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; end - 2'b01: begin + 4'b0010: begin adc_dsync <= 1'b1; - adc_dwr <= adc_valid_0 & ~adc_dwr; - adc_ddata[127:112] <= adc_data_0[63:48]; - adc_ddata[111: 96] <= adc_data_0[47:32]; - adc_ddata[ 95: 80] <= adc_data_0[31:16]; - adc_ddata[ 79: 64] <= adc_data_0[15: 0]; + adc_dwr <= adc_valid_1 & adc_dcnt[0] & adc_dcnt[1]; + adc_ddata[255:240] <= adc_data_1[63:48]; + adc_ddata[239:224] <= adc_data_1[47:32]; + adc_ddata[223:208] <= adc_data_1[31:16]; + adc_ddata[207:192] <= adc_data_1[15: 0]; + adc_ddata[191:176] <= adc_ddata[255:240]; + adc_ddata[175:160] <= adc_ddata[239:224]; + adc_ddata[159:144] <= adc_ddata[223:208]; + adc_ddata[143:128] <= adc_ddata[207:192]; + adc_ddata[127:112] <= adc_ddata[191:176]; + adc_ddata[111: 96] <= adc_ddata[175:160]; + adc_ddata[ 95: 80] <= adc_ddata[159:144]; + adc_ddata[ 79: 64] <= adc_ddata[143:128]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + 4'b0100: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_2 & adc_dcnt[0] & adc_dcnt[1]; + adc_ddata[255:240] <= adc_data_2[63:48]; + adc_ddata[239:224] <= adc_data_2[47:32]; + adc_ddata[223:208] <= adc_data_2[31:16]; + adc_ddata[207:192] <= adc_data_2[15: 0]; + adc_ddata[191:176] <= adc_ddata[255:240]; + adc_ddata[175:160] <= adc_ddata[239:224]; + adc_ddata[159:144] <= adc_ddata[223:208]; + adc_ddata[143:128] <= adc_ddata[207:192]; + adc_ddata[127:112] <= adc_ddata[191:176]; + adc_ddata[111: 96] <= adc_ddata[175:160]; + adc_ddata[ 95: 80] <= adc_ddata[159:144]; + adc_ddata[ 79: 64] <= adc_ddata[143:128]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + 4'b1000: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_3 & adc_dcnt[0] & adc_dcnt[1]; + adc_ddata[255:240] <= adc_data_3[63:48]; + adc_ddata[239:224] <= adc_data_3[47:32]; + adc_ddata[223:208] <= adc_data_3[31:16]; + adc_ddata[207:192] <= adc_data_3[15: 0]; + adc_ddata[191:176] <= adc_ddata[255:240]; + adc_ddata[175:160] <= adc_ddata[239:224]; + adc_ddata[159:144] <= adc_ddata[223:208]; + adc_ddata[143:128] <= adc_ddata[207:192]; + adc_ddata[127:112] <= adc_ddata[191:176]; + adc_ddata[111: 96] <= adc_ddata[175:160]; + adc_ddata[ 95: 80] <= adc_ddata[159:144]; + adc_ddata[ 79: 64] <= adc_ddata[143:128]; adc_ddata[ 63: 48] <= adc_ddata[127:112]; adc_ddata[ 47: 32] <= adc_ddata[111: 96]; adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; @@ -368,17 +347,11 @@ module system_top ( default: begin adc_dsync <= 1'b0; adc_dwr <= 1'b0; - adc_ddata <= 128'd0; + adc_ddata <= 256'd0; end endcase end - // spi - - assign spi_csn_adc = spi_csn[2]; - assign spi_csn_dac = spi_csn[1]; - assign spi_csn_clk = spi_csn[0]; - // instantiations IBUFDS_GTE2 i_ibufds_rx_ref_clk ( @@ -393,49 +366,40 @@ module system_top ( .IB (rx_sysref_n), .O (rx_sysref)); - OBUFDS i_obufds_rx_sync ( + OBUFDS i_obufds_rx_sync_0 ( .I (rx_sync), - .O (rx_sync_p), - .OB (rx_sync_n)); + .O (rx_sync_0_p), + .OB (rx_sync_0_n)); - IBUFDS_GTE2 i_ibufds_tx_ref_clk ( - .CEB (1'd0), - .I (tx_ref_clk_p), - .IB (tx_ref_clk_n), - .O (tx_ref_clk), - .ODIV2 ()); + OBUFDS i_obufds_rx_sync_1 ( + .I (rx_sync), + .O (rx_sync_1_p), + .OB (rx_sync_1_n)); - IBUFDS i_ibufds_tx_sysref ( - .I (tx_sysref_p), - .IB (tx_sysref_n), - .O (tx_sysref)); + assign ada4961_1a_csn = 1'b1; + assign ada4961_1b_csn = 1'b1; + assign ada4961_2a_csn = 1'b1; + assign ada4961_2b_csn = 1'b1; - IBUFDS i_ibufds_tx_sync ( - .I (tx_sync_p), - .IB (tx_sync_n), - .O (tx_sync)); - - daq2_spi i_spi ( - .spi_csn (spi_csn), + fmcadc3_spi i_spi ( + .ad9528_csn (ad9528_csn), + .ad9234_1_csn (ad9234_1_csn), + .ad9234_2_csn (ad9234_2_csn), .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi_miso), .spi_sdio (spi_sdio)); - ad_iobuf #(.DATA_WIDTH(26)) i_iobuf ( - .dt ({gpio_t[42:32], gpio_t[14:0]}), - .di ({gpio_o[42:32], gpio_o[14:0]}), - .do ({gpio_i[42:32], gpio_i[14:0]}), - .dio ({ adc_pd, // 42 - dac_txen, // 41 - dac_reset, // 40 - clkd_pd, // 39 - clkd_sync, // 38 - clkd_reset, // 37 - adc_fdb, // 36 - adc_fda, // 35 - dac_irq, // 34 - clkd_status, // 32 + ad_iobuf #(.DATA_WIDTH(38)) i_iobuf ( + .dt ({gpio_t[37:32], gpio_t[14:0]}), + .di ({gpio_o[37:32], gpio_o[14:0]}), + .do ({gpio_i[37:32], gpio_i[14:0]}), + .dio ({ ad9234_2_fdb, // 37 + ad9234_2_fda, // 36 + ad9234_1_fdb, // 35 + ad9234_1_fda, // 34 + ad9528_status, // 33 + ad9528_rstn, // 32 gpio_bd})); // 0 system_wrapper i_system_wrapper ( @@ -481,28 +445,22 @@ module system_top ( .adc_clk (adc_clk), .adc_data_0 (adc_data_0), .adc_data_1 (adc_data_1), + .adc_data_2 (adc_data_2), + .adc_data_3 (adc_data_3), .adc_ddata (adc_ddata), .adc_dsync (adc_dsync), .adc_dwr (adc_dwr), .adc_enable_0 (adc_enable_0), .adc_enable_1 (adc_enable_1), + .adc_enable_2 (adc_enable_2), + .adc_enable_3 (adc_enable_3), .adc_valid_0 (adc_valid_0), .adc_valid_1 (adc_valid_1), - .dac_clk (dac_clk), - .dac_ddata (dac_ddata), - .dac_ddata_0 (dac_ddata_0), - .dac_ddata_1 (dac_ddata_1), - .dac_ddata_2 (dac_ddata_2), - .dac_ddata_3 (dac_ddata_3), - .dac_drd (dac_drd), - .dac_enable_0 (dac_enable_0), - .dac_enable_1 (dac_enable_1), - .dac_enable_2 (dac_enable_2), - .dac_enable_3 (dac_enable_3), - .dac_valid_0 (dac_valid_0), - .dac_valid_1 (dac_valid_1), - .dac_valid_2 (dac_valid_2), - .dac_valid_3 (dac_valid_3), + .adc_valid_2 (adc_valid_2), + .adc_valid_3 (adc_valid_3), + .gt_data (gt_data), + .gt_data_0 (gt_data[127:0]), + .gt_data_1 (gt_data[255:128]), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -518,18 +476,15 @@ module system_top ( .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), - .spi_csn_i (spi_csn), - .spi_csn_o (spi_csn), + .spi_csn_0 (ad9528_csn), + .spi_csn_1 (ad9234_1_csn), + .spi_csn_2 (ad9234_2_csn), + .spi_csn_i (1'b1), .spi_sdi_i (spi_miso), .spi_sdo_i (spi_mosi), .spi_sdo_o (spi_mosi), .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref)); + .sys_clk_clk_p (sys_clk_p)); endmodule