From aaae350b3defa5664ab1dd38041c3203d5a397e5 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 26 May 2017 11:00:07 -0400 Subject: [PATCH] alt_serdes- 16.1 updates --- .../common/alt_serdes/alt_serdes_hw.tcl | 359 ++++++++---------- 1 file changed, 165 insertions(+), 194 deletions(-) diff --git a/library/altera/common/alt_serdes/alt_serdes_hw.tcl b/library/altera/common/alt_serdes/alt_serdes_hw.tcl index 781ec56e6..c242e3484 100644 --- a/library/altera/common/alt_serdes/alt_serdes_hw.tcl +++ b/library/altera/common/alt_serdes/alt_serdes_hw.tcl @@ -1,49 +1,32 @@ package require qsys -set_module_property NAME alt_serdes -set_module_property DESCRIPTION "Altera SERDES" -set_module_property VERSION 1.0 -set_module_property GROUP "Analog Devices" -set_module_property DISPLAY_NAME alt_serdes +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl + +ad_ip_create alt_serdes {Altera SERDES} set_module_property COMPOSITION_CALLBACK p_alt_serdes # parameters +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +set_parameter_property DEVICE_FAMILY ALLOWED_RANGES {"Arria 10" "Cyclone V"} + add_parameter MODE STRING "CLK" -set_parameter_property MODE DISPLAY_NAME MODE -set_parameter_property MODE TYPE STRING -set_parameter_property MODE UNITS None set_parameter_property MODE HDL_PARAMETER false set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"} add_parameter DDR_OR_SDR_N INTEGER 1 -set_parameter_property DDR_OR_SDR_N DISPLAY_NAME DDR_OR_SDR_N -set_parameter_property DDR_OR_SDR_N TYPE INTEGER -set_parameter_property DDR_OR_SDR_N UNITS None set_parameter_property DDR_OR_SDR_N HDL_PARAMETER false set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1} add_parameter SERDES_FACTOR INTEGER 8 -set_parameter_property SERDES_FACTOR DISPLAY_NAME SERDES_FACTOR -set_parameter_property SERDES_FACTOR TYPE INTEGER -set_parameter_property SERDES_FACTOR UNITS None set_parameter_property SERDES_FACTOR HDL_PARAMETER false set_parameter_property SERDES_FACTOR ALLOWED_RANGES {2 4 8} add_parameter CLKIN_FREQUENCY FLOAT 500.0 -set_parameter_property CLKIN_FREQUENCY DISPLAY_NAME CLKIN_FREQUENCY -set_parameter_property CLKIN_FREQUENCY TYPE FLOAT -set_parameter_property CLKIN_FREQUENCY UNITS None -set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz" set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false - -add_parameter DEVICE_FAMILY STRING "Arria 10" -set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY} -set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true -set_parameter_property DEVICE_FAMILY HDL_PARAMETER false -set_parameter_property DEVICE_FAMILY ENABLED false -set_parameter_property DEVICE_FAMILY ALLOWED_RANGES {"Arria 10" "Cyclone V"} +set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz" proc p_alt_serdes {} { @@ -59,186 +42,174 @@ proc p_alt_serdes {} { set m_ls_phase 22.5 set m_ld_phase 315.0 set m_ld_duty_cycle 12.5 + if {$m_serdes_factor == 4} { set m_ls_phase 45 set m_ld_phase 270.0 set m_ld_duty_cycle 25.0 } - ## arria 10, cmos data-in and data-out - - if {($m_serdes_factor == 2) && ($m_device_family == "Arria 10")} { - - add_instance alt_serdes_out altera_gpio - set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output} - set_instance_parameter_value alt_serdes_out {SIZE} {1} - set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0} - set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO} - add_interface clk conduit end - set_interface_property clk EXPORT_OF alt_serdes_out.ck - add_interface din conduit end - set_interface_property din EXPORT_OF alt_serdes_out.din - add_interface pad_out conduit end - set_interface_property pad_out EXPORT_OF alt_serdes_out.pad_out + ## cyclone V, clock only - others are megafunctions + if {$m_device_family == "Cyclone V"} { + if {$m_mode == "CLK"} { + add_instance alt_serdes_pll altera_pll + set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency + set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds} + set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1} + set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3} + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0} + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase + set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase + set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true} + add_interface rst reset sink + set_interface_property rst EXPORT_OF alt_serdes_pll.reset + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk + add_interface locked conduit end + set_interface_property locked EXPORT_OF alt_serdes_pll.locked + add_interface hs_clk clock source + set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0 + add_interface loaden clock source + set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1 + add_interface ls_clk clock source + set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2 + add_instance alt_serdes_pll_reconfig altera_pll_reconfig + add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll + add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll + add_interface drp_clk clock sink + set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk + add_interface drp_rst reset sink + set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset + add_interface pll_reconfig avalon slave + set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave + return + } return } - ## cyclone v, cmos data-in and data-out - - if {($m_serdes_factor == 2) && ($m_device_family == "Cyclone V")} { - - return - } - - ## arria 10, serdes clock, data-in and data-out - - if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} { - - add_instance alt_serdes_pll altera_iopll - set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency - set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1} - set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds} - set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0} - set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true} - set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true} - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate - set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees} - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0} - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate - set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees} - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase - set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase - set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees} - add_interface rst reset sink - set_interface_property rst EXPORT_OF alt_serdes_pll.reset - add_interface ref_clk clock sink - set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk - add_interface locked conduit end - set_interface_property locked EXPORT_OF alt_serdes_pll.locked - add_interface hs_phase conduit end - set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout - add_interface hs_clk conduit end - set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk - add_interface loaden conduit end - set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden - add_interface ls_clk clock source - set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2 - - add_instance alt_serdes_pll_reconfig altera_pll_reconfig - add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll - add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll - add_interface drp_clk clock sink - set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk - add_interface drp_rst reset sink - set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset - add_interface pll_reconfig avalon slave - set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave - - return - } - - if {($m_mode == "IN") && ($m_device_family == "Arria 10")} { - - add_instance alt_serdes_in altera_lvds - set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO} - set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1} - set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate - set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor - set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true} - set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency - set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false} - add_interface data_in conduit end - set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in - add_interface clk conduit end - set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk - add_interface loaden conduit end - set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden - add_interface div_clk conduit end - set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock - add_interface hs_phase conduit end - set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph - add_interface locked conduit end - set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked - add_interface data_s conduit end - set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out - add_interface delay_locked conduit end - set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked - - return - } - - if {($m_mode == "OUT") && ($m_device_family == "Arria 10")} { - - add_instance alt_serdes_out altera_lvds - set_instance_parameter_value alt_serdes_out {MODE} {TX} - set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1} - set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate - set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor - set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false} - set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false} - set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true} - set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency - set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false} - add_interface data_out conduit end - set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out - add_interface clk conduit end - set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk - add_interface loaden conduit end - set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden - add_interface div_clk conduit end - set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock - add_interface data_s conduit end - set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in - - return - } - - ## cyclone v, serdes clock, data-in and data-out - - if {($m_mode == "CLK") && ($m_device_family == "Cyclone V")} { - - add_instance alt_serdes_pll altera_pll - set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency - set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds} - set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1} - set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3} - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate - set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees} - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0} - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate - set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees} - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase - set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle - set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate - set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees} - set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase - set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true} - add_interface rst reset sink - set_interface_property rst EXPORT_OF alt_serdes_pll.reset - add_interface ref_clk clock sink - set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk - add_interface locked conduit end - set_interface_property locked EXPORT_OF alt_serdes_pll.locked - add_interface hs_clk clock source - set_interface_property hs_clk EXPORT_OF alt_serdes_pll.outclk0 - add_interface loaden clock source - set_interface_property loaden EXPORT_OF alt_serdes_pll.outclk1 - add_interface ls_clk clock source - set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2 - - add_instance alt_serdes_pll_reconfig altera_pll_reconfig - add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll - add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll - add_interface drp_clk clock sink - set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk - add_interface drp_rst reset sink - set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset - add_interface pll_reconfig avalon slave - set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave + ## arria 10 + if {$m_device_family == "Arria 10"} { + if {$m_mode == "CLK"} { + add_instance alt_serdes_pll altera_iopll + set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency + set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1} + set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds} + set_instance_parameter_value alt_serdes_pll {gui_number_of_clocks} {3} + set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0} + set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true} + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0} + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate + set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees} + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ld_phase + set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle + set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate + set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg2} $m_ls_phase + set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees} + add_interface rst reset sink + set_interface_property rst EXPORT_OF alt_serdes_pll.reset + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk + add_interface locked conduit end + set_interface_property locked EXPORT_OF alt_serdes_pll.locked + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout + add_interface hs_clk conduit end + set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden + add_interface ls_clk clock source + set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2 + return + } + if {($m_mode == "IN") && ($m_serdes_factor == 2)} { + add_instance alt_serdes_in altera_gpio + set_instance_parameter_value alt_serdes_in {PIN_TYPE_GUI} {Input} + set_instance_parameter_value alt_serdes_in {SIZE} {1} + set_instance_parameter_value alt_serdes_in {gui_diff_buff} {0} + set_instance_parameter_value alt_serdes_in {gui_io_reg_mode} {DDIO} + add_interface clk conduit end + set_interface_property clk EXPORT_OF alt_serdes_in.ck + add_interface din conduit end + set_interface_property din EXPORT_OF alt_serdes_in.din + add_interface pad_out conduit end + set_interface_property pad_out EXPORT_OF alt_serdes_in.pad_out + return + } + if {($m_mode == "OUT") && ($m_serdes_factor == 2)} { + add_instance alt_serdes_out altera_gpio + set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output} + set_instance_parameter_value alt_serdes_out {SIZE} {1} + set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0} + set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO} + add_interface clk conduit end + set_interface_property clk EXPORT_OF alt_serdes_out.ck + add_interface din conduit end + set_interface_property din EXPORT_OF alt_serdes_out.din + add_interface pad_out conduit end + set_interface_property pad_out EXPORT_OF alt_serdes_out.pad_out + return + } + if {$m_mode == "IN"} { + add_instance alt_serdes_in altera_lvds + set_instance_parameter_value alt_serdes_in {MODE} {RX_DPA-FIFO} + set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1} + set_instance_parameter_value alt_serdes_in {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value alt_serdes_in {J_FACTOR} $m_serdes_factor + set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true} + set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false} + add_interface data_in conduit end + set_interface_property data_in EXPORT_OF alt_serdes_in.rx_in + add_interface clk conduit end + set_interface_property clk EXPORT_OF alt_serdes_in.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF alt_serdes_in.ext_loaden + add_interface div_clk conduit end + set_interface_property div_clk EXPORT_OF alt_serdes_in.ext_coreclock + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF alt_serdes_in.ext_vcoph + add_interface locked conduit end + set_interface_property locked EXPORT_OF alt_serdes_in.ext_pll_locked + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out + add_interface delay_locked conduit end + set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked + return + } + if {$m_mode == "OUT"} { + add_instance alt_serdes_out altera_lvds + set_instance_parameter_value alt_serdes_out {MODE} {TX} + set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1} + set_instance_parameter_value alt_serdes_out {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value alt_serdes_out {J_FACTOR} $m_serdes_factor + set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false} + set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false} + set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true} + set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false} + add_interface data_out conduit end + set_interface_property data_out EXPORT_OF alt_serdes_out.tx_out + add_interface clk conduit end + set_interface_property clk EXPORT_OF alt_serdes_out.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF alt_serdes_out.ext_loaden + add_interface div_clk conduit end + set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in + return + } return } }