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adrv9009/common/adrv9009_bd: Take ref clock from the IBUFDS_GT 

In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR.  The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :

Enable device clocks (user clock)
Remove the reset from the XCVR
main
Laszlo Nagy 2022-02-14 08:05:09 +00:00 committed by Laszlo Nagy
parent 3c6c45962a
commit aac4746398
1 changed files with 5 additions and 3 deletions
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8
projects/adrv9009/common/adrv9009_bd.tcl
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@ -45,6 +45,8 @@ source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
# adrv9009
create_bd_port -dir I ref_clk
create_bd_port -dir I dac_fifo_bypass
create_bd_port -dir I adc_fir_filter_active
create_bd_port -dir I dac_fir_filter_active
@ -220,14 +222,14 @@ ad_connect $sys_cpu_clk util_adrv9009_xcvr/up_clk
# Tx
ad_connect adrv9009_tx_device_clk axi_adrv9009_tx_clkgen/clk_0
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_tx_xcvr axi_adrv9009_tx_jesd {0 3 2 1} adrv9009_tx_device_clk {} $MAX_TX_NUM_OF_LANES
ad_connect util_adrv9009_xcvr/tx_out_clk_0 axi_adrv9009_tx_clkgen/clk
ad_connect ref_clk axi_adrv9009_tx_clkgen/clk
ad_xcvrpll $tx_ref_clk util_adrv9009_xcvr/qpll_ref_clk_0
ad_xcvrpll axi_adrv9009_tx_xcvr/up_pll_rst util_adrv9009_xcvr/up_qpll_rst_0
# Rx
ad_connect adrv9009_rx_device_clk axi_adrv9009_rx_clkgen/clk_0
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_rx_xcvr axi_adrv9009_rx_jesd {} adrv9009_rx_device_clk {} $MAX_RX_NUM_OF_LANES
ad_connect util_adrv9009_xcvr/rx_out_clk_0 axi_adrv9009_rx_clkgen/clk
ad_connect ref_clk axi_adrv9009_rx_clkgen/clk
for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} {
set ch [expr $i]
ad_xcvrpll $rx_ref_clk util_adrv9009_xcvr/cpll_ref_clk_$ch
@ -237,7 +239,7 @@ for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} {
# Rx - OBS
ad_connect adrv9009_rx_os_device_clk axi_adrv9009_rx_os_clkgen/clk_0
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_rx_os_xcvr axi_adrv9009_rx_os_jesd {} adrv9009_rx_os_device_clk {} $MAX_RX_OS_NUM_OF_LANES
ad_connect util_adrv9009_xcvr/rx_out_clk_$MAX_RX_NUM_OF_LANES axi_adrv9009_rx_os_clkgen/clk
ad_connect ref_clk axi_adrv9009_rx_os_clkgen/clk
for {set i 0} {$i < $MAX_RX_OS_NUM_OF_LANES} {incr i} {
# channel indexing starts from the last RX
set ch [expr $MAX_RX_NUM_OF_LANES + $i]