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zcu102- updates

main
Rejeesh Kutty 2016-05-10 15:40:12 -04:00
parent e1350018da
commit aadb220a3f
1 changed files with 67 additions and 89 deletions
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156
library/scripts/adi_ip.tcl
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@ -77,31 +77,7 @@ proc adi_ip_bd {ip_name ip_bd_files} {
proc adi_ip_properties {ip_name} { proc adi_ip_properties {ip_name} {
ipx::package_project -root_dir . adi_ip_properties_lite $ip_name
set_property vendor {analog.com} [ipx::current_core]
set_property library {user} [ipx::current_core]
set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
set_property vendor_display_name {Analog Devices} [ipx::current_core]
set_property company_url {www.analog.com} [ipx::current_core]
set_property supported_families \
{{kintexu} {Pre-Production} \
{virtexu} {Pre-Production} \
{virtex7} {Production} \
{qvirtex7} {Production} \
{kintex7} {Production} \
{kintex7l} {Production} \
{qkintex7} {Production} \
{qkintex7l} {Production} \
{artix7} {Production} \
{artix7l} {Production} \
{aartix7} {Production} \
{qartix7} {Production} \
{zynq} {Production} \
{qzynq} {Production} \
{azynq} {Production}} \
[ipx::current_core]
ipx::remove_all_bus_interface [ipx::current_core] ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface {\ ipx::infer_bus_interface {\
@ -139,10 +115,10 @@ proc adi_ip_properties {ip_name} {
-of_objects [ipx::get_bus_interfaces s_axi_aclk \ -of_objects [ipx::get_bus_interfaces s_axi_aclk \
-of_objects [ipx::current_core]]] -of_objects [ipx::current_core]]]
ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core] ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
} }
proc adi_ip_properties_lite {ip_name} { proc adi_ip_properties_lite {ip_name} {
@ -155,91 +131,93 @@ proc adi_ip_properties_lite {ip_name} {
set_property vendor_display_name {Analog Devices} [ipx::current_core] set_property vendor_display_name {Analog Devices} [ipx::current_core]
set_property company_url {www.analog.com} [ipx::current_core] set_property company_url {www.analog.com} [ipx::current_core]
set_property supported_families \ set_property supported_families {\
{{kintexu} {Pre-Production} \ virtex7 Production
{virtexu} {Pre-Production} \ qvirtex7 Production
{virtex7} {Production} \ kintex7 Production
{qvirtex7} {Production} \ kintex7l Production
{kintex7} {Production} \ qkintex7 Production
{kintex7l} {Production} \ qkintex7l Production
{qkintex7} {Production} \ artix7 Production
{qkintex7l} {Production} \ artix7l Production
{artix7} {Production} \ aartix7 Production
{artix7l} {Production} \ qartix7 Production
{aartix7} {Production} \ zynq Production
{qartix7} {Production} \ qzynq Production
{zynq} {Production} \ azynq Production
{qzynq} {Production} \ virtexu Production
{azynq} {Production}} \ kintexuplus Production
zynquplus Production
kintexu Production}\
[ipx::current_core] [ipx::current_core]
} }
proc adi_set_ports_dependency {port_prefix dependency} { proc adi_set_ports_dependency {port_prefix dependency} {
foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
set_property ENABLEMENT_DEPENDENCY $dependency $port set_property ENABLEMENT_DEPENDENCY $dependency $port
} }
} }
proc adi_set_bus_dependency {bus prefix dependency} { proc adi_set_bus_dependency {bus prefix dependency} {
set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
adi_set_ports_dependency $prefix $dependency adi_set_ports_dependency $prefix $dependency
} }
proc adi_add_port_map {bus phys logic} { proc adi_add_port_map {bus phys logic} {
set map [ipx::add_port_map $phys $bus] set map [ipx::add_port_map $phys $bus]
set_property "PHYSICAL_NAME" $phys $map set_property "PHYSICAL_NAME" $phys $map
set_property "LOGICAL_NAME" $logic $map set_property "LOGICAL_NAME" $logic $map
} }
proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
set_property "BUS_TYPE_VLNV" $bus_type $bus set_property "BUS_TYPE_VLNV" $bus_type $bus
set_property "INTERFACE_MODE" $mode $bus set_property "INTERFACE_MODE" $mode $bus
foreach port_map $port_maps { foreach port_map $port_maps {
adi_add_port_map $bus {*}$port_map adi_add_port_map $bus {*}$port_map
} }
} }
proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
set_property display_name $clock_inf_name $clock_inf set_property display_name $clock_inf_name $clock_inf
set clock_map [ipx::add_port_map "CLK" $clock_inf] set clock_map [ipx::add_port_map "CLK" $clock_inf]
set_property physical_name $clock_signal_name $clock_map set_property physical_name $clock_signal_name $clock_map
set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
set_property value $bus_inf_name $assoc_busif set_property value $bus_inf_name $assoc_busif
if { $reset_signal_name != "" } { if { $reset_signal_name != "" } {
set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
set_property value $reset_signal_name $assoc_reset set_property value $reset_signal_name $assoc_reset
set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
set_property display_name $reset_inf_name $reset_inf set_property display_name $reset_inf_name $reset_inf
set_property interface_mode $reset_signal_mode $reset_inf set_property interface_mode $reset_signal_mode $reset_inf
set reset_map [ipx::add_port_map "RST" $reset_inf] set reset_map [ipx::add_port_map "RST" $reset_inf]
set_property physical_name $reset_signal_name $reset_map set_property physical_name $reset_signal_name $reset_map
set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
set_property value "ACTIVE_LOW" $reset_polarity set_property value "ACTIVE_LOW" $reset_polarity
} }
} }
proc adi_ip_add_core_dependencies {vlnvs} { proc adi_ip_add_core_dependencies {vlnvs} {
foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
foreach vlnv $vlnvs { foreach vlnv $vlnvs {
ipx::add_subcore $vlnv $file_group ipx::add_subcore $vlnv $file_group
} }
} }
} }
proc adi_if_define {name} { proc adi_if_define {name} {