zcu102- updates
Rejeesh Kutty
parent
e1350018da
commit
aadb220a3f
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@ -77,31 +77,7 @@ proc adi_ip_bd {ip_name ip_bd_files} {
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proc adi_ip_properties {ip_name} {
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ipx::package_project -root_dir .
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set_property vendor {analog.com} [ipx::current_core]
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set_property library {user} [ipx::current_core]
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set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
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set_property vendor_display_name {Analog Devices} [ipx::current_core]
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set_property company_url {www.analog.com} [ipx::current_core]
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set_property supported_families \
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{{kintexu} {Pre-Production} \
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{virtexu} {Pre-Production} \
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{virtex7} {Production} \
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{qvirtex7} {Production} \
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{kintex7} {Production} \
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{kintex7l} {Production} \
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{qkintex7} {Production} \
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{qkintex7l} {Production} \
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{artix7} {Production} \
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{artix7l} {Production} \
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{aartix7} {Production} \
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{qartix7} {Production} \
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{zynq} {Production} \
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{qzynq} {Production} \
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{azynq} {Production}} \
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[ipx::current_core]
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adi_ip_properties_lite $ip_name
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ipx::remove_all_bus_interface [ipx::current_core]
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ipx::infer_bus_interface {\
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@ -139,10 +115,10 @@ proc adi_ip_properties {ip_name} {
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-of_objects [ipx::get_bus_interfaces s_axi_aclk \
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-of_objects [ipx::current_core]]]
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ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
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}
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proc adi_ip_properties_lite {ip_name} {
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@ -155,91 +131,93 @@ proc adi_ip_properties_lite {ip_name} {
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set_property vendor_display_name {Analog Devices} [ipx::current_core]
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set_property company_url {www.analog.com} [ipx::current_core]
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set_property supported_families \
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{{kintexu} {Pre-Production} \
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{virtexu} {Pre-Production} \
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{virtex7} {Production} \
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{qvirtex7} {Production} \
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{kintex7} {Production} \
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{kintex7l} {Production} \
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{qkintex7} {Production} \
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{qkintex7l} {Production} \
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{artix7} {Production} \
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{artix7l} {Production} \
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{aartix7} {Production} \
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{qartix7} {Production} \
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{zynq} {Production} \
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{qzynq} {Production} \
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{azynq} {Production}} \
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set_property supported_families {\
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virtex7 Production
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qvirtex7 Production
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kintex7 Production
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kintex7l Production
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qkintex7 Production
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qkintex7l Production
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artix7 Production
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artix7l Production
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aartix7 Production
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qartix7 Production
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zynq Production
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qzynq Production
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azynq Production
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virtexu Production
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kintexuplus Production
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zynquplus Production
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kintexu Production}\
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[ipx::current_core]
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}
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proc adi_set_ports_dependency {port_prefix dependency} {
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foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
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set_property ENABLEMENT_DEPENDENCY $dependency $port
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}
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foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
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set_property ENABLEMENT_DEPENDENCY $dependency $port
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}
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}
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proc adi_set_bus_dependency {bus prefix dependency} {
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set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
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adi_set_ports_dependency $prefix $dependency
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set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
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adi_set_ports_dependency $prefix $dependency
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}
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proc adi_add_port_map {bus phys logic} {
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set map [ipx::add_port_map $phys $bus]
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set_property "PHYSICAL_NAME" $phys $map
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set_property "LOGICAL_NAME" $logic $map
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set map [ipx::add_port_map $phys $bus]
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set_property "PHYSICAL_NAME" $phys $map
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set_property "LOGICAL_NAME" $logic $map
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}
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proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
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set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
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set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
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set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
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set_property "BUS_TYPE_VLNV" $bus_type $bus
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set_property "INTERFACE_MODE" $mode $bus
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set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
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set_property "BUS_TYPE_VLNV" $bus_type $bus
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set_property "INTERFACE_MODE" $mode $bus
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foreach port_map $port_maps {
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adi_add_port_map $bus {*}$port_map
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}
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foreach port_map $port_maps {
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adi_add_port_map $bus {*}$port_map
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}
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}
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proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
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set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
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set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
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set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
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set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
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set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
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set_property display_name $clock_inf_name $clock_inf
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set clock_map [ipx::add_port_map "CLK" $clock_inf]
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set_property physical_name $clock_signal_name $clock_map
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set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
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set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
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set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
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set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
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set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
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set_property display_name $clock_inf_name $clock_inf
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set clock_map [ipx::add_port_map "CLK" $clock_inf]
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set_property physical_name $clock_signal_name $clock_map
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set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
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set_property value $bus_inf_name $assoc_busif
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set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
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set_property value $bus_inf_name $assoc_busif
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if { $reset_signal_name != "" } {
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set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
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set_property value $reset_signal_name $assoc_reset
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if { $reset_signal_name != "" } {
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set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
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set_property value $reset_signal_name $assoc_reset
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set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
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set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
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set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
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set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
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set_property display_name $reset_inf_name $reset_inf
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set_property interface_mode $reset_signal_mode $reset_inf
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set reset_map [ipx::add_port_map "RST" $reset_inf]
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set_property physical_name $reset_signal_name $reset_map
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set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
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set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
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set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
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set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
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set_property display_name $reset_inf_name $reset_inf
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set_property interface_mode $reset_signal_mode $reset_inf
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set reset_map [ipx::add_port_map "RST" $reset_inf]
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set_property physical_name $reset_signal_name $reset_map
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set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
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set_property value "ACTIVE_LOW" $reset_polarity
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}
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set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
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set_property value "ACTIVE_LOW" $reset_polarity
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}
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}
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proc adi_ip_add_core_dependencies {vlnvs} {
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foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
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foreach vlnv $vlnvs {
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ipx::add_subcore $vlnv $file_group
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}
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}
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foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
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foreach vlnv $vlnvs {
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ipx::add_subcore $vlnv $file_group
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}
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}
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}
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proc adi_if_define {name} {
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