spi_engine_execution: Add echoed SCLK support
There are boards (e.g. AD4630-24) which take the SCLK and echo back to the FPGA through a level shifter - doing this removes the effect of round-trip timing delays from the level shifter. This is commonly done whenever isolators are used since they are very slow. By setting the ECHO_SCLK parameter to 1, the IP will use the incoming echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still synchronous to the SPI clock, and it's generated after the last valid SDI latch. The designer's responsibility is to time the SDI shift registers in order to respect the design requirements.main
Istvan Csomortani
István Csomortáni
parent
6f4053f3b0
commit
ab10bd136e
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@ -1,4 +1,4 @@
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proc spi_engine_create {{name "hier_spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {sdi_delay 2}} {
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proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {sdi_delay 0} {echo_sclk 0}} {
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create_bd_cell -type hier $name
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current_bd_instance /$name
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@ -6,6 +6,9 @@ proc spi_engine_create {{name "hier_spi_engine"} {data_width 32} {async_spi_clk
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if {$async_spi_clk == 1} {
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create_bd_pin -dir I -type clk spi_clk
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}
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if {$echo_sclk == 1} {
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create_bd_pin -dir I -type clk echo_sclk
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}
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I trigger
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@ -19,6 +22,7 @@ proc spi_engine_create {{name "hier_spi_engine"} {data_width 32} {async_spi_clk
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ad_ip_parameter execution CONFIG.NUM_OF_SDI $num_sdi
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ad_ip_parameter execution CONFIG.SDO_DEFAULT 1
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ad_ip_parameter execution CONFIG.SDI_DELAY $sdi_delay
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ad_ip_parameter execution CONFIG.ECHO_SCLK $echo_sclk
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ad_ip_instance axi_spi_engine axi_regmap
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ad_ip_parameter axi_regmap CONFIG.DATA_WIDTH $data_width
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@ -60,6 +64,10 @@ proc spi_engine_create {{name "hier_spi_engine"} {data_width 32} {async_spi_clk
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ad_connect clk interconnect/clk
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}
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if {$echo_sclk == 1} {
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ad_connect echo_sclk execution/echo_sclk
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}
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ad_connect axi_regmap/spi_resetn offload/spi_resetn
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ad_connect axi_regmap/spi_resetn execution/resetn
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ad_connect axi_regmap/spi_resetn interconnect/resetn
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@ -43,6 +43,7 @@ module spi_engine_execution #(
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parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
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parameter NUM_OF_SDI = 1,
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parameter [0:0] SDO_DEFAULT = 1'b0,
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parameter ECHO_SCLK = 0,
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parameter [1:0] SDI_DELAY = 2'b00) (
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input clk,
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@ -67,6 +68,7 @@ module spi_engine_execution #(
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output reg sync_valid,
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output [7:0] sync,
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input echo_sclk,
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output reg sclk,
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output reg sdo,
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output reg sdo_t,
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@ -107,7 +109,6 @@ reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
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wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
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wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
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wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];
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wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
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wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
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wire ntx_rx = counter[0];
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@ -127,8 +128,6 @@ wire end_of_word;
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reg [7:0] sdi_counter = 8'b0;
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assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length));
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assign last_bit = bit_counter == word_length - 1;
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assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
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reg [15:0] cmd_d1;
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@ -159,13 +158,13 @@ wire trigger_rx;
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wire sleep_counter_compare;
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wire cs_sleep_counter_compare;
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wire cs_sleep_counter_compare2;
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wire io_ready1;
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wire io_ready2;
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wire trigger_rx_s;
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wire last_sdi_bit;
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wire end_of_sdi_latch;
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assign cmd_ready = idle;
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@ -240,7 +239,6 @@ assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
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assign sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
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assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
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assign cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
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always @(posedge clk) begin
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if (idle == 1'b1) begin
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@ -263,11 +261,11 @@ always @(posedge clk) begin
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end else begin
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case (inst_d1)
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CMD_TRANSFER: begin
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if (transfer_active == 1'b0 && wait_for_io == 1'b0)
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if (transfer_active == 1'b0 && wait_for_io == 1'b0 && end_of_sdi_latch == 1'b1)
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idle <= 1'b1;
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end
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CMD_CHIPSELECT: begin
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if (cs_sleep_counter_compare2)
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if (cs_sleep_counter_compare)
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idle <= 1'b1;
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end
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CMD_MISC: begin
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@ -318,15 +316,6 @@ always @(posedge clk) begin
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sdo_data_ready <= 1'b0;
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end
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always @(posedge clk) begin
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if (resetn == 1'b0)
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sdi_data_valid <= 1'b0;
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else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
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sdi_data_valid <= 1'b1;
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else if (sdi_data_ready == 1'b1)
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sdi_data_valid <= 1'b0;
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end
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assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
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(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
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assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
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@ -404,10 +393,142 @@ assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1];
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// Load the serial data into SDI shift register(s), then link it to the output
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// register of the module
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// NOTE: ECHO_SCLK mode can be used when the SCLK line is looped back to the FPGA
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// through an other level shifter, in order to remove the round-trip timing delays
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// introduced by the level shifters. This can improve the timing significantly
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// on higher SCLK rates. Devices like ad4630 have an echod SCLK, which can be
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// used to latch the MISO lines, improving the overall timing margin of the
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// interface.
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wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
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genvar i;
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// NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point
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generate
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if (ECHO_SCLK == 1) begin : g_echo_sclk_miso_latch
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reg [7:0] sdi_counter_d = 8'b0;
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reg [7:0] sdi_transfer_counter = 8'b0;
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reg [7:0] num_of_transfers = 8'b0;
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reg [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data_latch = {(NUM_OF_SDI * DATA_WIDTH){1'b0}};
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if ((DEFAULT_SPI_CFG[1:0] == 2'b01) || (DEFAULT_SPI_CFG[1:0] == 2'b10)) begin : g_echo_miso_nshift_reg
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// MISO shift register runs on negative echo_sclk
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for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
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reg [DATA_WIDTH-1:0] data_sdi_shift;
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always @(negedge echo_sclk or posedge cs_active_s) begin
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if (cs_active_s) begin
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data_sdi_shift <= 0;
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end else begin
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data_sdi_shift <= {data_sdi_shift, sdi[i]};
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end
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end
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// intended LATCH
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always @(negedge echo_sclk) begin
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if (last_sdi_bit)
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sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= {data_sdi_shift, sdi[i]};
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end
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end
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always @(posedge echo_sclk or posedge cs_active_s) begin
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if (cs_active_s == 1'b1) begin
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sdi_counter <= 8'b0;
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sdi_counter_d <= 8'b0;
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end else begin
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sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
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sdi_counter_d <= sdi_counter;
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end
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end
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end else begin : g_echo_miso_pshift_reg
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// MISO shift register runs on positive echo_sclk
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for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
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reg [DATA_WIDTH-1:0] data_sdi_shift;
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always @(posedge echo_sclk or posedge cs_active_s) begin
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if (cs_active_s) begin
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data_sdi_shift <= 0;
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end else begin
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data_sdi_shift <= {data_sdi_shift, sdi[i]};
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end
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end
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// intended LATCH
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always @(posedge echo_sclk) begin
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if (last_sdi_bit)
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sdi_data_latch[i*DATA_WIDTH+:DATA_WIDTH] <= data_sdi_shift;
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end
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end
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always @(posedge echo_sclk or posedge cs_active_s) begin
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if (cs_active_s == 1'b1) begin
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sdi_counter <= 8'b0;
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sdi_counter_d <= 8'b0;
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end else begin
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sdi_counter <= (sdi_counter == word_length-1) ? 8'b0 : sdi_counter + 1'b1;
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sdi_counter_d <= sdi_counter;
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end
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end
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end
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assign sdi_data = sdi_data_latch;
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assign last_sdi_bit = (sdi_counter == 0) && (sdi_counter_d == word_length-1);
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// sdi_data_valid is synchronous to SPI clock, so synchronize the
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// last_sdi_bit to SPI clock
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reg [3:0] last_sdi_bit_m = 4'b0;
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always @(posedge clk) begin
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if (cs_active_s) begin
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last_sdi_bit_m <= 4'b0;
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end else begin
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last_sdi_bit_m <= {last_sdi_bit_m, last_sdi_bit};
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end
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end
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always @(posedge clk) begin
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if (cs_active_s) begin
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sdi_data_valid <= 1'b0;
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end else if (sdi_enabled == 1'b1 &&
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last_sdi_bit_m[3] == 1'b0 &&
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last_sdi_bit_m[2] == 1'b1) begin
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sdi_data_valid <= 1'b1;
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end else if (sdi_data_ready == 1'b1 && sdi_data_valid == 1'b1) begin
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sdi_data_valid <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (cs_active_s) begin
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num_of_transfers <= 8'b0;
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end else begin
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if (cmd_d1[15:12] == 4'b0) begin
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num_of_transfers <= cmd_d1[7:0] + 1'b1; // cmd_d1 contains the NUM_OF_TRANSFERS - 1
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end
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end
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end
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always @(posedge clk) begin
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if (cs_active_s) begin
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sdi_transfer_counter <= 0;
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end else if (last_sdi_bit_m[2] == 1'b0 &&
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last_sdi_bit_m[1] == 1'b1) begin
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sdi_transfer_counter <= sdi_transfer_counter + 1'b1;
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end
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end
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assign end_of_sdi_latch = last_sdi_bit_m[2] & (sdi_transfer_counter == num_of_transfers);
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end /* g_echo_sclk_miso_latch */
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else
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begin : g_sclk_miso_latch
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assign end_of_sdi_latch = 1'b1;
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for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
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reg [DATA_WIDTH-1:0] data_sdi_shift;
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@ -425,18 +546,35 @@ generate
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assign sdi_data[i*DATA_WIDTH+:DATA_WIDTH] = data_sdi_shift;
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end
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endgenerate
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assign last_sdi_bit = (sdi_counter == word_length-1);
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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sdi_counter <= 8'b0;
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end else begin
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if (trigger_rx_s == 1'b1) begin
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sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
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assign last_sdi_bit = (sdi_counter == word_length-1);
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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sdi_counter <= 8'b0;
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end else begin
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if (trigger_rx_s == 1'b1) begin
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sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
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end
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0)
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sdi_data_valid <= 1'b0;
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else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
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sdi_data_valid <= 1'b1;
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else if (sdi_data_ready == 1'b1)
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sdi_data_valid <= 1'b0;
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end
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end /* g_sclk_miso_latch */
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endgenerate
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// end_of_word will signal the end of a transaction, pushing the command
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// stream execution to the next command. end_of_word in normal mode can be
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// generated using the global bit_counter
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assign last_bit = bit_counter == word_length - 1;
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assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
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always @(posedge clk) begin
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if (transfer_active == 1'b1) begin
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@ -107,6 +107,21 @@ set_property -dict [list \
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] \
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[ipx::get_hdl_parameters SDI_DELAY -of_objects $cc]
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## ECHO SCLK
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set_property -dict [list \
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"value_format" "bool" \
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"value" "false" \
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] \
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[ipx::get_user_parameters ECHO_SCLK -of_objects $cc]
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set_property -dict [list \
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"value_format" "bool" \
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"value" "false" \
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] \
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[ipx::get_hdl_parameters ECHO_SCLK -of_objects $cc]
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## echo_sclk should be active only when ECHO_SCLK is set
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adi_set_ports_dependency echo_sclk ECHO_SCLK 0
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## Customize IP Layout
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## Remove the automatically generated GUI page
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@ -176,6 +191,15 @@ set_property -dict [list \
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"tooltip" "\[SDO_DEFAULT\] Define the default voltage level on MOSI"
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] [ipgui::get_guiparamspec -name "SDO_DEFAULT" -component $cc]
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set custom_clocking_group [ipgui::add_group -name "Custom clocking options" -component $cc \
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-parent $page0 -display_name "Custom clocking options" ]
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ipgui::add_param -name "ECHO_SCLK" -component $cc -parent $custom_clocking_group
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set_property -dict [list \
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"display_name" "Echoed SCLK" \
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"tooltip" "\[ECHO_SCLK\] Activate echo SCLK option (hardware support required)"
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] [ipgui::get_guiparamspec -name "ECHO_SCLK" -component $cc]
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## Create and save the XGUI file
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ipx::create_xgui_files $cc
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