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up_axi.v: fixed bus width definition 

fixed axi_dma_regmap.v bus width missmatch
main
Arpadi 2019-07-30 16:01:10 +03:00 committed by sarpadi
parent a78c95d8fb
commit ab3d43be71
4 changed files with 12 additions and 16 deletions
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4
library/axi_dmac/axi_dmac.v
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@ -69,7 +69,7 @@ module axi_dmac #(
input s_axi_aresetn,
input s_axi_awvalid,
input [11:0] s_axi_awaddr,
input [10:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
@ -80,7 +80,7 @@ module axi_dmac #(
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [11:0] s_axi_araddr,
input [10:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,

2
library/axi_dmac/axi_dmac_hw.tcl
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@ -194,7 +194,7 @@ foreach domain [list {*}$src_clks {*}$dest_clks] {
# axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 11
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint s_axi

6
library/axi_dmac/axi_dmac_regmap.v
View File

@ -56,7 +56,7 @@ module axi_dmac_regmap #(
input s_axi_awvalid,
output s_axi_awready,
input [11:0] s_axi_awaddr,
input [10:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
@ -70,7 +70,7 @@ module axi_dmac_regmap #(
input s_axi_arvalid,
output s_axi_arready,
input [11:0] s_axi_araddr,
input [10:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
@ -261,7 +261,7 @@ axi_dmac_regmap_request #(
);
up_axi #(
.AXI_ADDRESS_WIDTH (12)
.AXI_ADDRESS_WIDTH (11)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),

16
library/common/up_axi.v
View File

@ -67,18 +67,14 @@ module up_axi #(
// pcore interface
output up_wreq,
output [(ADDRESS_WIDTH-1):0] up_waddr,
output [(AXI_ADDRESS_WIDTH-3):0] up_waddr,
output [31:0] up_wdata,
input up_wack,
output up_rreq,
output [(ADDRESS_WIDTH-1):0] up_raddr,
output [(AXI_ADDRESS_WIDTH-3):0] up_raddr,
input [31:0] up_rdata,
input up_rack);
// local parameters
localparam ADDRESS_WIDTH = AXI_ADDRESS_WIDTH - 2;
// internal registers
reg up_axi_awready_int = 'd0;
@ -87,7 +83,7 @@ module up_axi #(
reg up_wack_d = 'd0;
reg up_wsel = 'd0;
reg up_wreq_int = 'd0;
reg [(ADDRESS_WIDTH-1):0] up_waddr_int = 'd0;
reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0;
reg [31:0] up_wdata_int = 'd0;
reg [ 4:0] up_wcount = 'd0;
reg up_axi_arready_int = 'd0;
@ -97,7 +93,7 @@ module up_axi #(
reg [31:0] up_rdata_d = 'd0;
reg up_rsel = 'd0;
reg up_rreq_int = 'd0;
reg [(ADDRESS_WIDTH-1):0] up_raddr_int = 'd0;
reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0;
reg [ 4:0] up_rcount = 'd0;
// internal signals
@ -160,7 +156,7 @@ module up_axi #(
end else begin
up_wsel <= up_axi_awvalid & up_axi_wvalid;
up_wreq_int <= up_axi_awvalid & up_axi_wvalid;
up_waddr_int <= up_axi_awaddr[(ADDRESS_WIDTH+1):2];
up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2];
up_wdata_int <= up_axi_wdata;
end
if (up_wack_s == 1'b1) begin
@ -225,7 +221,7 @@ module up_axi #(
end else begin
up_rsel <= up_axi_arvalid;
up_rreq_int <= up_axi_arvalid;
up_raddr_int <= up_axi_araddr[(ADDRESS_WIDTH+1):2];
up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2];
end
if (up_rack_s == 1'b1) begin
up_rcount <= 5'h00;