diff --git a/library/axi_pulsar_lvds/Makefile b/library/axi_pulsar_lvds/Makefile new file mode 100755 index 000000000..50042da03 --- /dev/null +++ b/library/axi_pulsar_lvds/Makefile @@ -0,0 +1,30 @@ +#################################################################################### +## Copyright (c) 2018 - 2024 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_pulsar_lvds + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_pulsar_lvds.v +GENERIC_DEPS += axi_pulsar_lvds_channel.v +GENERIC_DEPS += axi_pulsar_lvds_if.v + +XILINX_DEPS += ../xilinx/common/ad_data_clk.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_pulsar_lvds_ip.tcl + +include ../scripts/library.mk diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds.v b/library/axi_pulsar_lvds/axi_pulsar_lvds.v new file mode 100755 index 000000000..bbb775318 --- /dev/null +++ b/library/axi_pulsar_lvds/axi_pulsar_lvds.v @@ -0,0 +1,332 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_pulsar_lvds #( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter DELAY_REFCLK_FREQUENCY = 200, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter ADC_INIT_DELAY = 0, + parameter ADC_DATA_WIDTH = 16, + parameter BITS_PER_SAMPLE = 32 +) ( + input delay_clk, + + // adc interface + + input ref_clk, + input clk_gate, + input dco_p, + input dco_n, + input d_p, + input d_n, + + // dma interface + + output adc_valid, + output [BITS_PER_SAMPLE-1:0] adc_data, + input adc_dovf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal signals + + wire [(ADC_DATA_WIDTH-1):0] adc_data_s; + wire adc_or_s; + wire [ 1:0] up_dld_s; + wire [ 9:0] up_dwdata_s; + wire [ 9:0] up_drdata_s; + wire delay_locked_s; + wire up_status_pn_err_s; + wire up_status_pn_oos_s; + wire up_status_or_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:2]; + wire up_rack_s[0:2]; + wire up_wack_s[0:2]; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + + // internal registers + + reg up_wack = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + + // internal signals + + wire adc_rst; + wire adc_clk; + wire adc_enable; + wire up_clk; + wire up_rstn; + wire delay_rst; + wire adc_valid_ch_s; + wire [(ADC_DATA_WIDTH-1):0] adc_data_ch_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_clk = ref_clk; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (!up_rstn) begin + up_rdata <= 32'd0; + up_rack <= 1'd0; + up_wack <= 1'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; + end + end + + // main (device interface) + + axi_pulsar_lvds_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IODELAY_CTRL (IODELAY_CTRL), + .ADC_DATA_WIDTH (ADC_DATA_WIDTH) + ) axi_pulsar_lvds_if_inst ( + .up_clk(up_clk), + .up_dld(up_dld_s), + .up_dwdata(up_dwdata_s), + .up_drdata(up_drdata_s), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_locked(delay_locked_s), + .clk(ref_clk), + .clk_gate(clk_gate), + .dco_p(dco_p), + .dco_n(dco_n), + .d_p(d_p), + .d_n(d_n), + .adc_valid(adc_valid_ch_s), + .adc_data(adc_data_ch_s)); + + // channel + + axi_pulsar_lvds_channel #( + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .ADC_DATA_WIDTH (ADC_DATA_WIDTH), + .BITS_PER_SAMPLE (BITS_PER_SAMPLE) + ) i_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_in (adc_data_ch_s), + .adc_valid_in (adc_valid_ch_s), + .adc_enable (adc_enable), + .adc_valid (adc_valid), + .adc_data (adc_data), + .up_adc_pn_err (up_status_pn_err_s), + .up_adc_pn_oos (up_status_pn_oos_s), + .up_adc_or (up_status_or_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // adc delay control + + up_delay_cntrl #( + .INIT_DELAY (ADC_INIT_DELAY), + .DATA_WIDTH (2), + .BASE_ADDRESS (6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (0), + .COMMON_ID (6'h00), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .GPIO_DISABLE (0), + .START_CODE_DISABLE (0) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (delay_locked_s), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'b1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm(), + .adc_ext_sync_disarm(), + .adc_ext_sync_manual_req(), + .adc_num_lanes (), + .adc_custom_control(), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter (32'd0), + .up_pps_status (1'd0), + .up_pps_irq_mask (), + .up_adc_r1_mode (), + .up_adc_ce (), + .up_status_pn_err (up_status_pn_err_s), + .up_status_pn_oos (up_status_pn_oos_s), + .up_status_or (up_status_or_s), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'b0), + .up_drp_ready (1'b0), + .up_drp_locked (1'b1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v b/library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v new file mode 100755 index 000000000..742dc8437 --- /dev/null +++ b/library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v @@ -0,0 +1,168 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_pulsar_lvds_channel #( + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter ADC_DATA_WIDTH = 16, + parameter BITS_PER_SAMPLE = 32 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input adc_valid_in, + input [18:0] adc_data_in, + + // dma interface + + output adc_enable, + output adc_valid, + output [BITS_PER_SAMPLE-1:0] adc_data, + + // error monitoring + + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire adc_dfmt_valid_s; + wire [(ADC_DATA_WIDTH-1):0] adc_dfmt_data_s; + wire adc_dcfilter_valid_s; + wire adc_iqcor_enb_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire [ 3:0] adc_data_sel_s; + + ad_datafmt #( + .DATA_WIDTH (ADC_DATA_WIDTH), + .BITS_PER_SAMPLE (BITS_PER_SAMPLE), + .DISABLE (DATAFORMAT_DISABLE) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid_in), + .data (adc_data_in), + .valid_out (adc_valid), + .data_out (adc_data), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + + // adc channel regmap + + up_adc_channel #( + .CHANNEL_ID (0), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (1'b1), + .IQCORRECTION_DISABLE (1'b1) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (), + .adc_pn_oos (1'b0), + .adc_or (1'b0), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .adc_softspan (), + .up_adc_crc_err (), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds_if.v b/library/axi_pulsar_lvds/axi_pulsar_lvds_if.v new file mode 100755 index 000000000..1910ff9a9 --- /dev/null +++ b/library/axi_pulsar_lvds/axi_pulsar_lvds_if.v @@ -0,0 +1,132 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface, note that overrange is independent of data path, +// software will not be able to relate overrange to a specific sample! + +`timescale 1ns/100ps + +module axi_pulsar_lvds_if #( + + parameter FPGA_TECHNOLOGY = 1, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter DELAY_REFCLK_FREQUENCY = 200, + parameter ADC_DATA_WIDTH = 16 +) ( + + // delay interface + + input up_clk, + input [ 1:0] up_dld, + input [ 9:0] up_dwdata, + output [ 9:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + // adc interface + + input clk, + input clk_gate, + input dco_p, + input dco_n, + input d_p, + input d_n, + + output reg adc_valid, + output reg [(ADC_DATA_WIDTH-1):0] adc_data +); + + // internal wires + + wire d_p_int_s; + wire dco; + wire dco_s; + + // internal register + + reg [ 1:0] clk_gate_d = 'b0; + reg [(ADC_DATA_WIDTH-1):0] adc_data_int = 'b0; + + // adc_valid is 1 for the current sample that is sent + + always @(posedge clk) begin + adc_valid <= 1'b0; + clk_gate_d <= {clk_gate_d[0], clk_gate}; + if (clk_gate_d[1] == 1'b1 && clk_gate_d[0] == 1'b0) begin + adc_data <= adc_data_int; + adc_valid <= 1'b1; + end + end + + always @(posedge dco) begin + adc_data_int <= {adc_data_int[(ADC_DATA_WIDTH-2):0], d_p_int_s}; + end + + // data interface - differential to single ended + + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IDDR_CLK_EDGE ("OPPOSITE_EDGE"), + .IODELAY_CTRL (IODELAY_CTRL), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .DDR_SDR_N(0) + ) i_rx_da ( + .rx_clk (dco), + .rx_data_in_p (d_p), + .rx_data_in_n (d_n), + .rx_data_p (d_p_int_s), + .rx_data_n (), + .up_clk (up_clk), + .up_dld (up_dld[0]), + .up_dwdata (up_dwdata[4:0]), + .up_drdata (up_drdata[4:0]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // clock + + IBUFDS i_rx_clk_ibuf ( + .I (dco_p), + .IB(dco_n), + .O (dco_s)); + + BUFH i_clk_buf ( + .I (dco_s), + .O (dco)); + +endmodule diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl b/library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl new file mode 100755 index 000000000..0fecc6c75 --- /dev/null +++ b/library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl @@ -0,0 +1,55 @@ +############################################################################### +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_pulsar_lvds + +adi_ip_files axi_pulsar_lvds [list \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "axi_pulsar_lvds_if.v" \ + "axi_pulsar_lvds_channel.v" \ + "axi_pulsar_lvds.v" ] + +adi_ip_properties axi_pulsar_lvds + +adi_add_bus "fifo_wr" "master" \ + "analog.com:interface:fifo_wr_rtl:1.0" \ + "analog.com:interface:fifo_wr:1.0" \ + { \ + {"adc_valid" "EN"} \ + {"adc_data" "DATA"} \ + {"adc_dovf" "OVERFLOW"} \ + } +adi_add_bus_clock "fifo_wr_clk" "fifo_wr" + +adi_init_bd_tcl +adi_ip_bd axi_pulsar_lvds "bd/bd.tcl" + +set cc [ipx::current_core] + +ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 $cc +ipx::infer_bus_interface dco_p xilinx.com:signal:clock_rtl:1.0 $cc +ipx::infer_bus_interface dco_n xilinx.com:signal:clock_rtl:1.0 $cc + +adi_add_auto_fpga_spec_params + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/projects/pulsar_lvds_adc/Makefile b/projects/pulsar_lvds_adc/Makefile new file mode 100755 index 000000000..6667c4f44 --- /dev/null +++ b/projects/pulsar_lvds_adc/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2024 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/pulsar_lvds_adc/Readme.md b/projects/pulsar_lvds_adc/Readme.md new file mode 100755 index 000000000..eff1c69e6 --- /dev/null +++ b/projects/pulsar_lvds_adc/Readme.md @@ -0,0 +1,17 @@ +# PULSAR_LVDS_ADC HDL Project + +Here are some pointers to help you: + * [EVAL-AD7626 board Product Page ](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD7626.html) + * Parts: [AD7626: 16-Bit, 10 MSPS, PulSAR Differential ADC](https://www.analog.com/ad7626) + * Parts: [AD7625: 16-Bit, 6 MSPS, PulSAR Differential ADC](https://www.analog.com/ad7625) + * Parts: [AD7961: 16-Bit, 5 MSPS, PULSAR® Differential ADC](https://www.analog.com/ad7961) + * Parts: [AD7960: 18-Bit, 5 MSPS, PULSAR® Differential ADC](https://www.analog.com/ad7960) + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577/hdl + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577 + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ltc2387 + +How to use over-writable parameters from the environment: +``` +hdl/projects/pulsar_lvds_adc/zed> make RESOLUTION_16_18N=0 +RESOLUTION_16_18N - Defines the resolution of the ADC: 0 - 18 BITS, 1 - 16 BITS. +``` \ No newline at end of file diff --git a/projects/pulsar_lvds_adc/common/pulsar_lvds_adc_bd.tcl b/projects/pulsar_lvds_adc/common/pulsar_lvds_adc_bd.tcl new file mode 100755 index 000000000..ea559e058 --- /dev/null +++ b/projects/pulsar_lvds_adc/common/pulsar_lvds_adc_bd.tcl @@ -0,0 +1,94 @@ +############################################################################### +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set RESOLUTION_16_18N $ad_project_params(RESOLUTION_16_18N) +puts "build parameters: RESOLUTION_16_18N: $RESOLUTION_16_18N" + +set ADC_DATA_WIDTH [expr {$RESOLUTION_16_18N == 1 ? 16 : 18}] +set BITS_PER_SAMPLE [expr {$RESOLUTION_16_18N == 1 ? 16 : 32}] + +create_bd_port -dir O sampling_clk +create_bd_port -dir I dco_p +create_bd_port -dir I dco_n +create_bd_port -dir O cnv +create_bd_port -dir I d_p +create_bd_port -dir I d_n +create_bd_port -dir O clk_gate + +# adc peripheral + +ad_ip_instance axi_pulsar_lvds axi_pulsar_lvds +ad_ip_parameter axi_pulsar_lvds CONFIG.ADC_DATA_WIDTH $ADC_DATA_WIDTH +ad_ip_parameter axi_pulsar_lvds CONFIG.BITS_PER_SAMPLE $BITS_PER_SAMPLE + +# axi pwm gen + +ad_ip_instance axi_pwm_gen axi_pwm_gen +ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 2 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 25 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_WIDTH 5 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_PERIOD 25 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_OFFSET 0 + +# dma + +ad_ip_instance axi_dmac axi_pulsar_lvds_dma +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.DMA_DATA_WIDTH_SRC $BITS_PER_SAMPLE +ad_ip_parameter axi_pulsar_lvds_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +# axi clk_gen + +ad_ip_instance axi_clkgen reference_clkgen +ad_ip_parameter reference_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter reference_clkgen CONFIG.VCO_MUL 10 +ad_ip_parameter reference_clkgen CONFIG.CLK0_DIV 6 + +ad_connect reference_clkgen/clk $sys_cpu_clk +ad_connect reference_clkgen/clk_0 sampling_clk +ad_connect reference_clkgen/clk_0 axi_pulsar_lvds/ref_clk + +# connections + +ad_connect sys_200m_clk axi_pulsar_lvds/delay_clk + +ad_connect clk_gate axi_pulsar_lvds/clk_gate +ad_connect dco_p axi_pulsar_lvds/dco_p +ad_connect dco_n axi_pulsar_lvds/dco_n +ad_connect d_p axi_pulsar_lvds/d_p +ad_connect d_n axi_pulsar_lvds/d_n + +ad_connect reference_clkgen/clk_0 axi_pulsar_lvds_dma/fifo_wr_clk +ad_connect axi_pulsar_lvds/fifo_wr axi_pulsar_lvds_dma/fifo_wr + +ad_connect cnv axi_pwm_gen/pwm_0 +ad_connect clk_gate axi_pwm_gen/pwm_1 +ad_connect reference_clkgen/clk_0 axi_pwm_gen/ext_clk +ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn +ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk + +# address mapping + +ad_cpu_interconnect 0x44A00000 axi_pulsar_lvds +ad_cpu_interconnect 0x44A30000 axi_pulsar_lvds_dma +ad_cpu_interconnect 0x44A60000 axi_pwm_gen +ad_cpu_interconnect 0x44A80000 reference_clkgen + +# interconnect (adc) + +ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect $sys_cpu_clk axi_pulsar_lvds_dma/m_dest_axi +ad_connect $sys_cpu_resetn axi_pulsar_lvds_dma/m_dest_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-12 axi_pulsar_lvds_dma/irq diff --git a/projects/pulsar_lvds_adc/zed/Makefile b/projects/pulsar_lvds_adc/zed/Makefile new file mode 100755 index 000000000..439d2bd6f --- /dev/null +++ b/projects/pulsar_lvds_adc/zed/Makefile @@ -0,0 +1,29 @@ +#################################################################################### +## Copyright (c) 2018 - 2024 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := pulsar_lvds_adc_zed + +M_DEPS += ad7960_system_top.v +M_DEPS += ad7626_system_top.v +M_DEPS += ../common/pulsar_lvds_adc_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_data_clk.v +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_pulsar_lvds +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/pulsar_lvds_adc/zed/ad7626_system_top.v b/projects/pulsar_lvds_adc/zed/ad7626_system_top.v new file mode 100644 index 000000000..305e695c2 --- /dev/null +++ b/projects/pulsar_lvds_adc/zed/ad7626_system_top.v @@ -0,0 +1,261 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + output clk_p, + output clk_n, + input dco_p, + input dco_n, + input d_n, + input d_p, + + output cnv_p, + output cnv_n, + inout en0_fmc, + inout en1_fmc, + inout fpga_pll_cnv_p, + inout fpga_pll_cnv_n, + inout pll_sync_fmc +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + wire cnv_s; + wire cnv; + wire clk_gate; + wire sampling_clk_s; + wire gated_sampling_clk; + + assign gpio_i[63:36] = gpio_o[63:36]; + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf ( + .dio_t(gpio_t[33:32]), + .dio_i(gpio_o[33:32]), + .dio_o(gpio_i[33:32]), + .dio_p({en1_fmc, // 87 + en0_fmc})); // 86 + + // instantiations + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE") + ) i_tx_clk_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (sampling_clk_s), + .D1 (clk_gate), + .D2 (1'b0), + .Q (gated_sampling_clk)); + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE") + ) i_cnv_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (sampling_clk_s), + .D1 (cnv), + .D2 (cnv), + .Q (cnv_s)); + + OBUFDS i_tx_data_obuf ( + .I (gated_sampling_clk), + .O (clk_p), + .OB (clk_n)); + + OBUFDS OBUFDS_cnv ( + .O (cnv_p), + .OB (cnv_n), + .I (cnv_s)); + + ad_iobuf #( + .DATA_WIDTH (32) + ) iobuf_gpio_bd ( + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_t (gpio_t[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .sampling_clk (sampling_clk_s), + .dco_p (dco_p), + .dco_n (dco_n), + .d_n (d_n), + .d_p (d_p), + .cnv (cnv), + .clk_gate (clk_gate), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule diff --git a/projects/pulsar_lvds_adc/zed/ad7960_system_top.v b/projects/pulsar_lvds_adc/zed/ad7960_system_top.v new file mode 100755 index 000000000..6f560da9d --- /dev/null +++ b/projects/pulsar_lvds_adc/zed/ad7960_system_top.v @@ -0,0 +1,262 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + output clk_p, + output clk_n, + input dco_p, + input dco_n, + input d_n, + input d_p, + + output cnv_p, + output cnv_n, + inout en0_fmc, + inout en1_fmc, + inout en2_fmc, + inout en3_fmc +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + wire cnv_s; + wire cnv; + wire clk_gate; + wire sampling_clk_s; + wire gated_sampling_clk; + + assign gpio_i[63:36] = gpio_o[63:36]; + + ad_iobuf #( + .DATA_WIDTH(4) + ) i_iobuf ( + .dio_t(gpio_t[35:32]), + .dio_i(gpio_o[35:32]), + .dio_o(gpio_i[35:32]), + .dio_p({en3_fmc, // 89 + en2_fmc, // 88 + en1_fmc, // 87 + en0_fmc})); // 86 + + // instantiations + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE") + ) i_tx_clk_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (sampling_clk_s), + .D1 (clk_gate), + .D2 (1'b0), + .Q (gated_sampling_clk)); + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE") + ) i_cnv_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (sampling_clk_s), + .D1 (cnv), + .D2 (cnv), + .Q (cnv_s)); + + OBUFDS i_tx_data_obuf ( + .I (gated_sampling_clk), + .O (clk_p), + .OB (clk_n)); + + OBUFDS OBUFDS_cnv ( + .O (cnv_p), + .OB (cnv_n), + .I (cnv_s)); + + ad_iobuf #( + .DATA_WIDTH (32) + ) iobuf_gpio_bd ( + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_t (gpio_t[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .sampling_clk (sampling_clk_s), + .dco_p (dco_p), + .dco_n (dco_n), + .d_n (d_n), + .d_p (d_p), + .cnv (cnv), + .clk_gate (clk_gate), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule diff --git a/projects/pulsar_lvds_adc/zed/system_bd.tcl b/projects/pulsar_lvds_adc/zed/system_bd.tcl new file mode 100755 index 000000000..b5d8a65da --- /dev/null +++ b/projects/pulsar_lvds_adc/zed/system_bd.tcl @@ -0,0 +1,18 @@ +############################################################################### +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source ../common/pulsar_lvds_adc_bd.tcl + +set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "sys rom custom string placeholder" + +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/pulsar_lvds_adc/zed/system_constr.tcl b/projects/pulsar_lvds_adc/zed/system_constr.tcl new file mode 100644 index 000000000..b14cfac62 --- /dev/null +++ b/projects/pulsar_lvds_adc/zed/system_constr.tcl @@ -0,0 +1,59 @@ +############################################################################### +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +if {![info exists RESOLUTION_16_18N]} { + set RESOLUTION_16_18N $::env(RESOLUTION_16_18N) +} + +# clocks + +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p]; ## G06 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n]; ## G07 FMC_LPC_LA00_CC_N + +# cnv + +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p]; ## D08 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n]; ## D09 FMC_LPC_LA01_CC_N + +# dco, da + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_p]; ## H04 FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_n]; ## H05 FMC_LPC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_p]; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_n]; ## H08 FMC_LPC_LA02_N + +# control signals +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports en0_fmc]; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports en1_fmc]; ## G10 FMC_LPC_LA03_N + +switch $RESOLUTION_16_18N { + 0 { + + set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports en2_fmc]; ## H10 FMC_LPC_LA04_P + set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports en3_fmc]; ## H11 FMC_LPC_LA04_N + } + 1 { + + set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports fpga_pll_cnv_p]; ## H10 FMC_LPC_LA04_P + set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports fpga_pll_cnv_n]; ## H11 FMC_LPC_LA04_N + + set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports pll_sync_fmc]; ## D11 FMC_LPC_LA05_P + } +} + +# 166.66 MHz clock + +create_clock -period 6.000 -name dco [get_ports dco_p] +create_clock -period 6.000 -name out_clock [get_ports clk_p] + +set input_clock dco; # Name of input clock +set input_clock_period 6.000; # Period of input clock +set dv_bre 2.000; # Data valid before the rising clock edge +set dv_are 2.000; # Data valid after the rising clock edge +set input_ports d_p; # List of input ports + +# Input Delay Constraint +set_input_delay -clock $input_clock -max [expr $input_clock_period - $dv_bre] [get_ports $input_ports]; +set_input_delay -clock $input_clock -min $dv_are [get_ports $input_ports]; diff --git a/projects/pulsar_lvds_adc/zed/system_project.tcl b/projects/pulsar_lvds_adc/zed/system_project.tcl new file mode 100755 index 000000000..1a2d7b234 --- /dev/null +++ b/projects/pulsar_lvds_adc/zed/system_project.tcl @@ -0,0 +1,44 @@ +############################################################################### +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# load script +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# RESOLUTION_16_18N - The resolution of the ADC +# LEGEND: 18 BITS RESOLUTION AD7960 - 0 +# 16 BITS RESOLUTION AD7626 - 1 + +set RESOLUTION_16_18N 0 + +if {[info exists ::env(RESOLUTION_16_18N)]} { + set RESOLUTION_16_18N $::env(RESOLUTION_16_18N) +} else { + set env(RESOLUTION_16_18N) $RESOLUTION_16_18N +} + +adi_project pulsar_lvds_adc_zed 0 [list \ + RESOLUTION_16_18N $RESOLUTION_16_18N \ +] + +adi_project_files pulsar_lvds_adc_zed [list \ + "system_constr.tcl" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + + switch $RESOLUTION_16_18N { + 0 { + adi_project_files pulsar_lvds_adc_zed [list \ + "ad7960_system_top.v" ] + } + 1 { + adi_project_files pulsar_lvds_adc_zed [list \ + "ad7626_system_top.v" ] + } +} + +adi_project_run pulsar_lvds_adc_zed