ad_tdd_control: Redesign the state machine to prevent timing failure.
parent
052860cbc3
commit
ab8256cf92
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@ -145,7 +145,8 @@ module ad_tdd_control(
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reg [23:0] tdd_counter = 24'h0;
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reg [23:0] tdd_counter = 24'h0;
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reg [ 5:0] tdd_burst_counter = 6'h0;
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reg [ 5:0] tdd_burst_counter = 6'h0;
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reg tdd_counter_state = OFF;
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reg tdd_cstate = OFF;
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reg tdd_cstate_next = OFF;
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reg counter_at_tdd_vco_rx_on_1 = 1'b0;
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reg counter_at_tdd_vco_rx_on_1 = 1'b0;
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reg counter_at_tdd_vco_rx_off_1 = 1'b0;
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reg counter_at_tdd_vco_rx_off_1 = 1'b0;
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@ -169,6 +170,7 @@ module ad_tdd_control(
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reg counter_at_tdd_tx_dp_off_2 = 1'b0;
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reg counter_at_tdd_tx_dp_off_2 = 1'b0;
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reg tdd_enable_d = 1'h0;
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reg tdd_enable_d = 1'h0;
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reg tdd_last_burst = 1'b0;
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// internal signals
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// internal signals
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@ -176,7 +178,8 @@ module ad_tdd_control(
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wire [23:0] tdd_tx_dp_on_2_s;
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wire [23:0] tdd_tx_dp_on_2_s;
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire tdd_endof_frame;
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wire tdd_endof_burst;
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wire tdd_txrx_only_en_s;
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wire tdd_txrx_only_en_s;
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assign tdd_counter_status = tdd_counter;
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assign tdd_counter_status = tdd_counter;
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@ -186,49 +189,60 @@ module ad_tdd_control(
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// ***************************************************************************
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// ***************************************************************************
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always @(posedge clk) begin
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always @(posedge clk) begin
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// sync reset
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if (rst == 1'b1) begin
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if (rst == 1'b1) begin
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tdd_counter <= 24'h0;
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tdd_cstate <= OFF;
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tdd_counter_state <= OFF;
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tdd_enable_d <= 0;
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end else begin
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end else begin
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tdd_cstate <= tdd_cstate_next;
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tdd_enable_d <= tdd_enable;
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tdd_enable_d <= tdd_enable;
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end
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end
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// counter reset
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always @* begin
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if (tdd_enable == 1'b0) begin
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tdd_cstate_next <= tdd_cstate;
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tdd_counter_state <= OFF;
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end else
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// start counter on the positive edge of the tdd_enable
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case (tdd_cstate)
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if ((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin
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ON : begin
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if ((tdd_enable == 1'b0) || (tdd_endof_burst == 1'b1)) begin
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tdd_cstate_next <= OFF;
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end
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end
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OFF : begin
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if((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin
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tdd_cstate_next <= ON;
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end
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end
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endcase
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end
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assign tdd_endof_frame = (tdd_counter == tdd_frame_length) ? 1'b1 : 1'b0;
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assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_counter == tdd_frame_length)) ? 1'b1 : 1'b0;
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// tdd free running counter
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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tdd_counter <= tdd_counter_init;
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tdd_counter <= tdd_counter_init;
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tdd_burst_counter <= tdd_burst_count;
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end else begin
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tdd_counter_state <= ON;
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if (tdd_cstate == ON) begin
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end else
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tdd_counter <= (tdd_counter < tdd_frame_length) ? tdd_counter + 1 : 24'b0;
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end else begin
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tdd_counter <= tdd_counter_init;
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end
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end
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end
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// free running counter
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// tdd burst counter
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if (tdd_counter_state == ON) begin
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always @(posedge clk) begin
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if (tdd_counter == tdd_frame_length) begin
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if (rst == 1'b1) begin
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tdd_counter <= 22'h0;
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tdd_burst_counter <= tdd_burst_count;
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if (tdd_burst_counter > 1) begin // inside a burst
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end else begin
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tdd_burst_counter <= tdd_burst_counter - 1;
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if (tdd_cstate == ON) begin
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tdd_counter_state <= ON;
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tdd_burst_counter <= ((tdd_burst_counter > 0) && (tdd_endof_frame == 1'b1)) ? tdd_burst_counter - 1 : tdd_burst_counter;
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end
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end else begin
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else
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tdd_burst_counter <= tdd_burst_count;
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if ( tdd_burst_counter == 1) begin // end of burst
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tdd_burst_counter <= 6'h0;
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tdd_counter_state <= OFF;
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end
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else begin // contiuous mode
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tdd_burst_counter <= 6'h0;
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tdd_counter_state <= ON;
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end
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end
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else begin
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tdd_counter <= tdd_counter + 1;
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end
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end
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end
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tdd_last_burst <= (tdd_burst_counter == 6'b1) ? 1'b1 : 1'b0;
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end
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end
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end
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end
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@ -539,13 +553,13 @@ module ad_tdd_control(
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if(rst == 1'b1) begin
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if(rst == 1'b1) begin
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tdd_rx_vco_en <= 1'b0;
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tdd_rx_vco_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin
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else if((tdd_cstate == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin
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tdd_rx_vco_en <= 1'b0;
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tdd_rx_vco_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin
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else if((tdd_cstate == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin
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tdd_rx_vco_en <= 1'b1;
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tdd_rx_vco_en <= 1'b1;
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end
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end
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else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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tdd_rx_vco_en <= tdd_rx_only;
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tdd_rx_vco_en <= tdd_rx_only;
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end
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end
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else begin
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else begin
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@ -557,13 +571,13 @@ module ad_tdd_control(
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if(rst == 1'b1) begin
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if(rst == 1'b1) begin
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tdd_tx_vco_en <= 1'b0;
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tdd_tx_vco_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin
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else if((tdd_cstate == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin
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tdd_tx_vco_en <= 1'b0;
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tdd_tx_vco_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin
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else if((tdd_cstate == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin
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tdd_tx_vco_en <= 1'b1;
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tdd_tx_vco_en <= 1'b1;
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end
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end
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else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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tdd_tx_vco_en <= tdd_tx_only;
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tdd_tx_vco_en <= tdd_tx_only;
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end
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end
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else begin
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else begin
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@ -575,13 +589,13 @@ module ad_tdd_control(
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if(rst == 1'b1) begin
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if(rst == 1'b1) begin
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tdd_rx_rf_en <= 1'b0;
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tdd_rx_rf_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
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else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
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tdd_rx_rf_en <= 1'b0;
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tdd_rx_rf_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
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else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
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tdd_rx_rf_en <= 1'b1;
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tdd_rx_rf_en <= 1'b1;
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end
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end
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else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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tdd_rx_rf_en <= tdd_rx_only;
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tdd_rx_rf_en <= tdd_rx_only;
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end
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end
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else begin
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else begin
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@ -593,13 +607,13 @@ module ad_tdd_control(
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if(rst == 1'b1) begin
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if(rst == 1'b1) begin
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tdd_tx_rf_en <= 1'b0;
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tdd_tx_rf_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
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else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
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tdd_tx_rf_en <= 1'b0;
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tdd_tx_rf_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
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else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
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tdd_tx_rf_en <= 1'b1;
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tdd_tx_rf_en <= 1'b1;
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end
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end
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else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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tdd_tx_rf_en <= tdd_tx_only;
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tdd_tx_rf_en <= tdd_tx_only;
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end
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end
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else begin
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else begin
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@ -611,13 +625,13 @@ module ad_tdd_control(
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if(rst == 1'b1) begin
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if(rst == 1'b1) begin
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tdd_tx_dp_en <= 1'b0;
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tdd_tx_dp_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
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else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
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tdd_tx_dp_en <= 1'b0;
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tdd_tx_dp_en <= 1'b0;
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end
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end
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else if((tdd_counter_state == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
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else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
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tdd_tx_dp_en <= 1'b1;
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tdd_tx_dp_en <= 1'b1;
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end
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end
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else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
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tdd_tx_dp_en <= tdd_tx_only;
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tdd_tx_dp_en <= tdd_tx_only;
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end
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end
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else begin
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else begin
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