From ab8627e669366778918d444fab022a924780aed5 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 17 Mar 2014 15:43:16 +0200 Subject: [PATCH] fmcomms1: Changed ILA data capture and sys constraints The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO. The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16 period so the constraints were modified accordingly. --- projects/fmcomms1/common/fmcomms1_bd.tcl | 32 +++++++++++++++++++---- projects/fmcomms1/zc702/system_constr.xdc | 6 ++--- projects/fmcomms1/zc706/system_constr.xdc | 2 ++ projects/fmcomms1/zed/system_constr.xdc | 9 ++++--- 4 files changed, 37 insertions(+), 12 deletions(-) diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index 8460b0216..656da00d0 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -28,9 +28,11 @@ set ref_clk [create_bd_port -dir O ref_clk] set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122] set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9122_dma set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma -set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {4}] $axi_ad9122_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma +set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9122_dma set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {64}] $axi_ad9122_dma set axi_ad9122_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9122_dma_interconnect] @@ -54,6 +56,10 @@ set_property -dict [list CONFIG.S_DATA_WIDTH {64}] $sys_ad9643_util_wfifo set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma] set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9643_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma +set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma +set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9643_dma set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {64}] $axi_ad9643_dma set axi_ad9643_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9643_dma_interconnect] @@ -184,15 +190,31 @@ connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/ connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn] -# ila (adc) +# ila (adc) - need a fifo, zed ila can not run at 250MHz + +set ila_adc_fifo [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:11.0 ila_adc_fifo] +set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $ila_adc_fifo +set_property -dict [list CONFIG.Input_Data_Width {28}] $ila_adc_fifo +set_property -dict [list CONFIG.Input_Depth {32}] $ila_adc_fifo +set_property -dict [list CONFIG.Output_Data_Width {56}] $ila_adc_fifo +set_property -dict [list CONFIG.Overflow_Flag {true}] $ila_adc_fifo +set_property -dict [list CONFIG.Reset_Pin {false}] $ila_adc_fifo set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc] set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE0_WIDTH {28}] $ila_adc +set_property -dict [list CONFIG.C_PROBE0_WIDTH {56}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc -connect_bd_net -net adc_clk [get_bd_pins ila_adc/clk] -connect_bd_net -net axi_ad9643_adc_mon_data [get_bd_pins axi_ad9643/adc_mon_data] [get_bd_pins ila_adc/probe0] +set ila_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 ila_constant_1] + + +connect_bd_net -net axi_ad9643_adc_mon_data [get_bd_pins axi_ad9643/adc_mon_data] [get_bd_pins ila_adc_fifo/din] +connect_bd_net -net adc_clk [get_bd_pins axi_ad9643/adc_clk] [get_bd_pins ila_adc_fifo/wr_clk] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc_fifo/rd_clk] +connect_bd_net -net xlconstant_0_const [get_bd_pins ila_adc_fifo/rd_en] [get_bd_pins ila_adc_fifo/wr_en] [get_bd_pins ila_constant_1/const] + +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc/clk] +connect_bd_net -net ila_adc_fifo_dout [get_bd_pins ila_adc_fifo/dout] [get_bd_pins ila_adc/probe0] # reference clock diff --git a/projects/fmcomms1/zc702/system_constr.xdc b/projects/fmcomms1/zc702/system_constr.xdc index a81ceca98..78e3da6f6 100644 --- a/projects/fmcomms1/zc702/system_constr.xdc +++ b/projects/fmcomms1/zc702/system_constr.xdc @@ -82,10 +82,10 @@ set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_p # clocks -create_clock -name dac_clk_in -period 2.10 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.06 [get_ports adc_clk_in_p] +create_clock -name dac_clk_in -period 2.16 [get_ports dac_clk_in_p] +create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] create_clock -name dac_div_clk -period 8.40 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk] -create_clock -name adc_clk -period 4.06 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] +create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] create_clock -name fmc_dma_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] set_clock_groups -asynchronous -group {dac_div_clk} diff --git a/projects/fmcomms1/zc706/system_constr.xdc b/projects/fmcomms1/zc706/system_constr.xdc index b48ff6501..9e19d5482 100644 --- a/projects/fmcomms1/zc706/system_constr.xdc +++ b/projects/fmcomms1/zc706/system_constr.xdc @@ -86,7 +86,9 @@ create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p] create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] create_clock -name dac_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk] create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] +create_clock -name fmc_dma_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] set_clock_groups -asynchronous -group {dac_div_clk} set_clock_groups -asynchronous -group {adc_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} diff --git a/projects/fmcomms1/zed/system_constr.xdc b/projects/fmcomms1/zed/system_constr.xdc index 9b35b4324..1d8c0e188 100644 --- a/projects/fmcomms1/zed/system_constr.xdc +++ b/projects/fmcomms1/zed/system_constr.xdc @@ -82,11 +82,12 @@ set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_p # clocks -create_clock -name dac_clk_in -period 2.10 [get_ports dac_clk_in_p] -create_clock -name adc_clk_in -period 4.06 [get_ports adc_clk_in_p] +create_clock -name dac_clk_in -period 2.16 [get_ports dac_clk_in_p] +create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] create_clock -name dac_div_clk -period 8.40 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk] -create_clock -name adc_clk -period 4.06 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] +create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk] +create_clock -name fmc_dma_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] set_clock_groups -asynchronous -group {dac_div_clk} set_clock_groups -asynchronous -group {adc_clk} - +set_clock_groups -asynchronous -group {fmc_dma_clk}