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axi_dacfifo: Counters must use 1'b1 for incrementation

main
Istvan Csomortani 2018-06-12 16:34:14 +01:00
parent a2fc1f25ca
commit aba355b4ce
2 changed files with 3 additions and 3 deletions
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4
library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v
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@ -57,8 +57,8 @@ module axi_dacfifo_address_buffer #(
waddr <= 0;
raddr <= 0;
end else begin
waddr <= (wea == 1'b1) ? waddr + 1 : waddr;
raddr <= (rea == 1'b1) ? raddr + 1 : raddr;
waddr <= (wea == 1'b1) ? waddr + 1'b1 : waddr;
raddr <= (rea == 1'b1) ? raddr + 1'b1 : raddr;
end
end

2
library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
View File

@ -437,7 +437,7 @@ module axi_dacfifo_rd #(
(dac_mem_raddr == (dac_mem_laddr_b + dac_last_beats - 1))) begin
dac_mem_raddr <= dac_mem_raddr + (MEM_RATIO - (dac_last_beats - 1));
end else begin
dac_mem_raddr <= dac_mem_raddr + 1;
dac_mem_raddr <= dac_mem_raddr + 1'b1;
end
end
dac_mem_raddr_g <= dac_mem_raddr_b2g_s;