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fmcadc2_zc706: Connect PLDDR rst to external push button

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Istvan Csomortani 2014-12-18 10:04:01 +02:00
parent 31a95042cf
commit abdb59a28e
2 changed files with 7 additions and 1 deletions
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3
projects/fmcadc2/zc706/system_bd.tcl
View File

@ -4,8 +4,11 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
p_plddr3_fifo [current_bd_instance .] axi_ad9625_fifo 256
create_bd_port -dir I -type rst sys_rst
set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9680_fifo/sys_rst]
connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9625_fifo/DDR3]
connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9625_fifo/sys_clk]
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_fifo/axi_fifo2s/axi] \

5
projects/fmcadc2/zc706/system_top.v
View File

@ -84,6 +84,7 @@ module system_top (
sys_clk_p,
sys_clk_n,
sys_rst,
hdmi_out_clk,
hdmi_vsync,
@ -159,6 +160,7 @@ module system_top (
input sys_clk_p;
input sys_clk_n;
input sys_rst;
output hdmi_out_clk;
output hdmi_vsync;
@ -323,7 +325,8 @@ module system_top (
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p));
.sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst));
endmodule