usdrx1: initial checkin
Rejeesh Kutty
parent
dc7b3e085c
commit
ac1c145a61
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module usdrx1_spi (
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spi_fout_csn,
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spi_afe_csn,
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spi_clk_csn,
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spi_clk,
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spi_mosi,
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spi_miso,
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spi_fout_sdio,
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spi_afe_sdio,
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spi_clk_sdio);
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// 4 wire
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input [ 5:0] spi_fout_csn;
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input [ 3:0] spi_afe_csn;
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input spi_clk_csn;
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input spi_clk;
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input spi_mosi;
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output spi_miso;
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// 3 wire
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inout spi_fout_sdio;
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inout spi_afe_sdio;
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input spi_clk_sdio;
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// internal signals
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wire [ 2:0] spi_csn_3_s;
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wire spi_csn_s;
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wire spi_enable_s;
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wire spi_fout_miso_s;
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wire spi_afe_miso_s;
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wire spi_clk_miso_s;
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// check on rising edge and change on falling edge
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assign spi_csn_3_s[2] = & spi_fout_csn;
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assign spi_csn_3_s[1] = & spi_afe_csn;
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assign spi_csn_3_s[0] = spi_clk_csn;
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assign spi_csn_s = & spi_csn_3_s;
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assign spi_enable_s = spi_enable & ~spi_csn_s;
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always @(posedge spi_clk) begin
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if (spi_csn_s == 1'b1) begin
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spi_count <= 6'd0;
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spi_rd_wr_n <= 1'd0;
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end else begin
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spi_count <= spi_count + 1'b1;
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if (spi_count == 6'd0) begin
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spi_rd_wr_n <= spi_mosi;
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end
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end
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end
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always @(negedge spi_clk) begin
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if (spi_csn_s == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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if (((spi_count == 6'd16) && (spi_csn_3_s[1] == 1'b0)) ||
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((spi_count == 6'd16) && (spi_csn_3_s[0] == 1'b0))) begin
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spi_enable <= spi_rd_wr_n;
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end
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end
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end
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assign spi_miso = ((spi_fout_miso_s & ~spi_csn_3_s[2]) |
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(spi_afe_miso_s & ~spi_csn_3_s[1]) |
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(spi_clk_miso_s & ~spi_csn_3_s[0]));
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// io buffers
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IOBUF i_iobuf_fout_sdio (
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.T (spi_enable_s),
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.I (spi_mosi),
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.O (spi_fout_miso_s),
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.IO (spi_fout_sdio));
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IOBUF i_iobuf_afe_sdio (
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.T (spi_enable_s),
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.I (spi_mosi),
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.O (spi_afe_miso_s),
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.IO (spi_afe_sdio));
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IOBUF i_iobuf_clk_sdio (
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.T (spi_enable_s),
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.I (spi_mosi),
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.O (spi_clk_miso_s),
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.IO (spi_clk_sdio));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,434 @@
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# create board design
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# interface ports
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set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR]
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set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO]
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set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN]
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set GPIO_I [create_bd_port -dir I -from 43 -to 0 GPIO_I]
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set GPIO_O [create_bd_port -dir O -from 43 -to 0 GPIO_O]
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set GPIO_T [create_bd_port -dir O -from 43 -to 0 GPIO_T]
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# interface ports
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set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
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set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
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set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
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set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
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set hdmi_data [create_bd_port -dir O -from 23 -to 0 hdmi_data]
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set hdmi_int [create_bd_port -dir I hdmi_int]
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set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
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set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p]
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set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n]
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set rx_sync [create_bd_port -dir O rx_sync]
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set rx_sysref [create_bd_port -dir O rx_sysref]
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set mlo_clk [create_bd_port -dir O mlo_clk]
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set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i]
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set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o]
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
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set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
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set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
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# instance: processing_system7_1
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set processing_system7_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 processing_system7_1]
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set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC706}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $processing_system7_1
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $processing_system7_1
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set axi_iic_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_1]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_1
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set xlconcat_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 xlconcat_1]
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set_property -dict [list CONFIG.NUM_PORTS {5}] $xlconcat_1
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set axi_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1]
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set_property -dict [list CONFIG.NUM_MI {12}] $axi_interconnect_1
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# hdmi peripherals
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect
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# ultrasound
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set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] [get_bd_cells axi_usdrx1_gt]
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set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_usdrx1_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
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set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0]
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set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_0]
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set axi_ad9671_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_1]
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set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_1]
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set axi_ad9671_core_2 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_2]
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set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_2]
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set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_3]
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set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_3]
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set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {512}] $axi_usdrx1_dma
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set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi
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set axi_usdrx1_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_gt_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_gt_interconnect
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set axi_usdrx1_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect
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set dma_concat_data [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 dma_concat_data]
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set_property -dict [list CONFIG.NUM_PORTS {4}] $dma_concat_data
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set_property -dict [list CONFIG.IN0_WIDTH {128}] $dma_concat_data
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set_property -dict [list CONFIG.IN1_WIDTH {128}] $dma_concat_data
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set_property -dict [list CONFIG.IN2_WIDTH {128}] $dma_concat_data
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set_property -dict [list CONFIG.IN3_WIDTH {128}] $dma_concat_data
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set dma_concat_sync [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 dma_concat_sync]
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set_property -dict [list CONFIG.NUM_PORTS {4}] $dma_concat_sync
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set_property -dict [list CONFIG.IN0_WIDTH {1}] $dma_concat_sync
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set_property -dict [list CONFIG.IN1_WIDTH {1}] $dma_concat_sync
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set_property -dict [list CONFIG.IN2_WIDTH {1}] $dma_concat_sync
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set_property -dict [list CONFIG.IN3_WIDTH {1}] $dma_concat_sync
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set dma_concat_wr [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 dma_concat_wr]
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set_property -dict [list CONFIG.NUM_PORTS {4}] $dma_concat_wr
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set_property -dict [list CONFIG.IN0_WIDTH {1}] $dma_concat_wr
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set_property -dict [list CONFIG.IN1_WIDTH {1}] $dma_concat_wr
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set_property -dict [list CONFIG.IN2_WIDTH {1}] $dma_concat_wr
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set_property -dict [list CONFIG.IN3_WIDTH {1}] $dma_concat_wr
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set dma_concat_sync_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:1.0 dma_concat_sync_or]
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set_property -dict [list CONFIG.C_SIZE {4}] $dma_concat_sync_or
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set_property -dict [list CONFIG.C_OPERATION {or}] $dma_concat_sync_or
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set dma_concat_wr_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:1.0 dma_concat_wr_or]
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set_property -dict [list CONFIG.C_SIZE {4}] $dma_concat_wr_or
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set_property -dict [list CONFIG.C_OPERATION {or}] $dma_concat_wr_or
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set gt_slice_data_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gt_slice_data_0]
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set_property -dict [list CONFIG.DIN_WIDTH {256}] $gt_slice_data_0
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set_property -dict [list CONFIG.DIN_FROM {63}] $gt_slice_data_0
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set_property -dict [list CONFIG.DIN_TO {0}] $gt_slice_data_0
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set gt_slice_data_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gt_slice_data_1]
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set_property -dict [list CONFIG.DIN_WIDTH {256}] $gt_slice_data_1
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set_property -dict [list CONFIG.DIN_FROM {127}] $gt_slice_data_1
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set_property -dict [list CONFIG.DIN_TO {64}] $gt_slice_data_1
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set gt_slice_data_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gt_slice_data_2]
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set_property -dict [list CONFIG.DIN_WIDTH {256}] $gt_slice_data_2
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set_property -dict [list CONFIG.DIN_FROM {191}] $gt_slice_data_2
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set_property -dict [list CONFIG.DIN_TO {128}] $gt_slice_data_2
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set gt_slice_data_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gt_slice_data_3]
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set_property -dict [list CONFIG.DIN_WIDTH {256}] $gt_slice_data_3
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set_property -dict [list CONFIG.DIN_FROM {255}] $gt_slice_data_3
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set_property -dict [list CONFIG.DIN_TO {192}] $gt_slice_data_3
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|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon]
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon
|
||||
|
||||
# interface connections
|
||||
|
||||
connect_bd_intf_net -intf_net processing_system7_1_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_1/DDR]
|
||||
connect_bd_net -net processing_system7_1_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins processing_system7_1/GPIO_I]
|
||||
connect_bd_net -net processing_system7_1_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins processing_system7_1/GPIO_O]
|
||||
connect_bd_net -net processing_system7_1_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins processing_system7_1/GPIO_T]
|
||||
connect_bd_intf_net -intf_net processing_system7_1_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_1/FIXED_IO]
|
||||
connect_bd_intf_net -intf_net axi_iic_1_iic [get_bd_intf_ports IIC_MAIN] [get_bd_intf_pins axi_iic_1/iic]
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk1 [get_bd_pins processing_system7_1/FCLK_CLK1]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins processing_system7_1/FCLK_CLK2]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk3 [get_bd_pins processing_system7_1/FCLK_CLK3] [get_bd_ports mlo_clk]
|
||||
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins processing_system7_1/FCLK_RESET2_N]
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins processing_system7_1/M_AXI_GP0_ACLK]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_s00_axi [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins processing_system7_1/M_AXI_GP0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m00_axi [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins axi_iic_1/s_axi]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_iic_1/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_iic_1/s_axi_aresetn]
|
||||
connect_bd_net -net xlconcat_din_0 [get_bd_pins xlconcat_1/In0] [get_bd_pins axi_iic_1/iic2intc_irpt]
|
||||
|
||||
connect_bd_net -net processing_system7_1_interrupt [get_bd_pins xlconcat_1/dout] [get_bd_pins processing_system7_1/IRQ_F2P]
|
||||
|
||||
# hdmi
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_clk1 [get_bd_pins axi_hdmi_clkgen/clk]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m01_axi [get_bd_intf_pins axi_interconnect_1/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m02_axi [get_bd_intf_pins axi_interconnect_1/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m03_axi [get_bd_intf_pins axi_interconnect_1/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
||||
connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_HP0]
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M02_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M03_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_interconnect/ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_interconnect/S00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_interconnect/M00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins processing_system7_1/S_AXI_HP0_ACLK]
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M02_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M03_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_interconnect/ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||
|
||||
connect_bd_net -net axi_hdmi_tx_1_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0]
|
||||
connect_bd_net -net axi_hdmi_tx_1_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk]
|
||||
connect_bd_net -net axi_hdmi_tx_1_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_24_hsync] [get_bd_ports hdmi_hsync]
|
||||
connect_bd_net -net axi_hdmi_tx_1_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_24_vsync] [get_bd_ports hdmi_vsync]
|
||||
connect_bd_net -net axi_hdmi_tx_1_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_24_data_e] [get_bd_ports hdmi_data_e]
|
||||
connect_bd_net -net axi_hdmi_tx_1_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_24_data] [get_bd_ports hdmi_data]
|
||||
connect_bd_net -net axi_hdmi_tx_1_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
|
||||
connect_bd_net -net axi_hdmi_tx_1_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]
|
||||
connect_bd_net -net axi_hdmi_tx_1_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]
|
||||
connect_bd_net -net axi_hdmi_tx_1_mm2s_tlast [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]
|
||||
connect_bd_net -net axi_hdmi_tx_1_mm2s_tready [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
|
||||
connect_bd_net -net axi_hdmi_tx_1_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync]
|
||||
connect_bd_net -net axi_hdmi_tx_1_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
|
||||
|
||||
connect_bd_net -net xlconcat_din_1 [get_bd_pins xlconcat_1/In1] [get_bd_ports hdmi_int]
|
||||
connect_bd_net -net xlconcat_din_2 [get_bd_pins xlconcat_1/In2] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||
|
||||
# Ultrasound
|
||||
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m04_axi [get_bd_intf_pins axi_interconnect_1/M04_AXI] [get_bd_intf_pins axi_usdrx1_gt/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m05_axi [get_bd_intf_pins axi_interconnect_1/M05_AXI] [get_bd_intf_pins axi_usdrx1_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m06_axi [get_bd_intf_pins axi_interconnect_1/M06_AXI] [get_bd_intf_pins axi_ad9671_core_0/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m07_axi [get_bd_intf_pins axi_interconnect_1/M07_AXI] [get_bd_intf_pins axi_ad9671_core_1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m08_axi [get_bd_intf_pins axi_interconnect_1/M08_AXI] [get_bd_intf_pins axi_ad9671_core_2/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m09_axi [get_bd_intf_pins axi_interconnect_1/M09_AXI] [get_bd_intf_pins axi_ad9671_core_3/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m10_axi [get_bd_intf_pins axi_interconnect_1/M10_AXI] [get_bd_intf_pins axi_usdrx1_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_1_m11_axi [get_bd_intf_pins axi_interconnect_1/M11_AXI] [get_bd_intf_pins axi_usdrx1_spi/axi_lite]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_gt/m_axi]
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_HP2]
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_HP3]
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M04_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M05_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M06_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M07_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M08_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M09_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M10_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M11_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt_interconnect/ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt_interconnect/S00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt_interconnect/M00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins processing_system7_1/S_AXI_HP2_ACLK]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt/m_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt/drp_clk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_jesd/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_ad9671_core_0/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_ad9671_core_1/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_ad9671_core_2/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_ad9671_core_3/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_dma/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_spi/s_axi_aclk]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] [get_bd_pins processing_system7_1/FCLK_CLK2]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK2]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK2]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins processing_system7_1/S_AXI_HP3_ACLK]
|
||||
connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk]
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M04_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M05_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M06_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M07_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M08_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M09_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M10_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M11_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt_interconnect/ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt_interconnect/S00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt_interconnect/M00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt/m_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_ad9671_core_0/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_ad9671_core_1/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_ad9671_core_2/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_ad9671_core_3/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_dma/s_axi_aresetn]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_spi/s_axi_aresetn]
|
||||
|
||||
connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET2_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET2_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET2_N]
|
||||
connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn]
|
||||
|
||||
connect_bd_net -net xlconcat_din_3 [get_bd_pins xlconcat_1/In3] [get_bd_pins axi_usdrx1_dma/irq]
|
||||
connect_bd_net -net xlconcat_din_4 [get_bd_pins xlconcat_1/In4] [get_bd_pins axi_usdrx1_spi/ip2intc_irpt]
|
||||
|
||||
connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core_0/adc_clk] [get_bd_pins axi_usdrx1_dma/fifo_wr_clk]
|
||||
connect_bd_net -net axi_ad9671_core_0_adc_dwr [get_bd_pins axi_ad9671_core_0/adc_dwr] [get_bd_pins dma_concat_wr/In0]
|
||||
connect_bd_net -net axi_ad9671_core_1_adc_dwr [get_bd_pins axi_ad9671_core_1/adc_dwr] [get_bd_pins dma_concat_wr/In1]
|
||||
connect_bd_net -net axi_ad9671_core_2_adc_dwr [get_bd_pins axi_ad9671_core_2/adc_dwr] [get_bd_pins dma_concat_wr/In2]
|
||||
connect_bd_net -net axi_ad9671_core_3_adc_dwr [get_bd_pins axi_ad9671_core_3/adc_dwr] [get_bd_pins dma_concat_wr/In3]
|
||||
connect_bd_net -net axi_ad9671_core_0_adc_dsync [get_bd_pins axi_ad9671_core_0/adc_dsync] [get_bd_pins dma_concat_sync/In0]
|
||||
connect_bd_net -net axi_ad9671_core_1_adc_dsync [get_bd_pins axi_ad9671_core_1/adc_dsync] [get_bd_pins dma_concat_sync/In1]
|
||||
connect_bd_net -net axi_ad9671_core_2_adc_dsync [get_bd_pins axi_ad9671_core_2/adc_dsync] [get_bd_pins dma_concat_sync/In2]
|
||||
connect_bd_net -net axi_ad9671_core_3_adc_dsync [get_bd_pins axi_ad9671_core_3/adc_dsync] [get_bd_pins dma_concat_sync/In3]
|
||||
connect_bd_net -net axi_ad9671_core_0_adc_ddata [get_bd_pins axi_ad9671_core_0/adc_ddata] [get_bd_pins dma_concat_data/In0]
|
||||
connect_bd_net -net axi_ad9671_core_1_adc_ddata [get_bd_pins axi_ad9671_core_1/adc_ddata] [get_bd_pins dma_concat_data/In1]
|
||||
connect_bd_net -net axi_ad9671_core_2_adc_ddata [get_bd_pins axi_ad9671_core_2/adc_ddata] [get_bd_pins dma_concat_data/In2]
|
||||
connect_bd_net -net axi_ad9671_core_3_adc_ddata [get_bd_pins axi_ad9671_core_3/adc_ddata] [get_bd_pins dma_concat_data/In3]
|
||||
connect_bd_net -net dma_concat_wr_dout [get_bd_pins dma_concat_wr/dout] [get_bd_pins dma_concat_wr_or/Op1]
|
||||
connect_bd_net -net dma_concat_sync_dout [get_bd_pins dma_concat_sync/dout] [get_bd_pins dma_concat_sync_or/Op1]
|
||||
connect_bd_net -net dma_concat_wr_or_res [get_bd_pins dma_concat_wr_or/Res] [get_bd_pins axi_usdrx1_dma/fifo_wr_en]
|
||||
connect_bd_net -net dma_concat_sync_or_res [get_bd_pins dma_concat_sync_or/Res] [get_bd_pins axi_usdrx1_dma/fifo_wr_sync]
|
||||
connect_bd_net -net dma_concat_wr_adc_ddata [get_bd_pins dma_concat_data/dout] [get_bd_pins axi_usdrx1_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_ad9671_core_0/adc_dovf]
|
||||
connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_ad9671_core_1/adc_dovf]
|
||||
connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_ad9671_core_2/adc_dovf]
|
||||
connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_ad9671_core_3/adc_dovf]
|
||||
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk] [get_bd_pins axi_usdrx1_jesd/rx_core_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_pins axi_usdrx1_jesd/rx_sysref]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_gt_charisk [get_bd_pins axi_usdrx1_gt/rx_gt_charisk] [get_bd_pins axi_usdrx1_jesd/gt_rxcharisk_in]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_gt_disperr [get_bd_pins axi_usdrx1_gt/rx_gt_disperr] [get_bd_pins axi_usdrx1_jesd/gt_rxdisperr_in]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_gt_notintable [get_bd_pins axi_usdrx1_gt/rx_gt_notintable] [get_bd_pins axi_usdrx1_jesd/gt_rxnotintable_in]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_gt_data [get_bd_pins axi_usdrx1_gt/rx_gt_data] [get_bd_pins axi_usdrx1_jesd/gt_rxdata_in]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_rst_done [get_bd_pins axi_usdrx1_gt/rx_rst_done] [get_bd_pins axi_usdrx1_jesd/rx_reset_done]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_ip_comma_align [get_bd_pins axi_usdrx1_gt/rx_ip_comma_align] [get_bd_pins axi_usdrx1_jesd/rxencommaalign_out]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_ip_sync [get_bd_pins axi_usdrx1_gt/rx_ip_sync] [get_bd_pins axi_usdrx1_jesd/rx_sync]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_ip_sof [get_bd_pins axi_usdrx1_gt/rx_ip_sof] [get_bd_pins axi_usdrx1_jesd/rx_start_of_frame]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_ip_data [get_bd_pins axi_usdrx1_gt/rx_ip_data] [get_bd_pins axi_usdrx1_jesd/rx_tdata]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk]
|
||||
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins axi_usdrx1_gt/rx_data]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins gt_slice_data_0/Din]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins gt_slice_data_1/Din]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins gt_slice_data_2/Din]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins gt_slice_data_3/Din]
|
||||
connect_bd_net -net gt_slice_data_0_dout [get_bd_pins axi_ad9671_core_0/rx_data] [get_bd_pins gt_slice_data_0/Dout]
|
||||
connect_bd_net -net gt_slice_data_1_dout [get_bd_pins axi_ad9671_core_1/rx_data] [get_bd_pins gt_slice_data_1/Dout]
|
||||
connect_bd_net -net gt_slice_data_2_dout [get_bd_pins axi_ad9671_core_2/rx_data] [get_bd_pins gt_slice_data_2/Dout]
|
||||
connect_bd_net -net gt_slice_data_3_dout [get_bd_pins axi_ad9671_core_3/rx_data] [get_bd_pins gt_slice_data_3/Dout]
|
||||
|
||||
connect_bd_net -net axi_usdrx1_gt_ref_clk_q [get_bd_pins axi_usdrx1_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_ports rx_sysref]
|
||||
|
||||
connect_bd_net -net axi_spi_1_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_usdrx1_spi/ss_i]
|
||||
connect_bd_net -net axi_spi_1_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_usdrx1_spi/ss_o]
|
||||
connect_bd_net -net axi_spi_1_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_usdrx1_spi/sck_i]
|
||||
connect_bd_net -net axi_spi_1_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_usdrx1_spi/sck_o]
|
||||
connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_usdrx1_spi/io0_i]
|
||||
connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o]
|
||||
connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i]
|
||||
|
||||
# ila
|
||||
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins axi_usdrx1_gt/rx_mon_data] [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins axi_usdrx1_gt/rx_mon_trigger] [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40800000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_iic_1/s_axi/Reg] SEG_data_iic_1
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a20000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a80000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44a50000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43c70000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_gt/s_axi/axi_lite] SEG_data_usdrx1_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x43c80000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_jesd/s_axi/Reg] SEG_data_usdrx1_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43c00000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43c10000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_1/s_axi/axi_lite] SEG_data_ad9671_core_1
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43c20000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_2/s_axi/axi_lite] SEG_data_ad9671_core_2
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43c30000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_3/s_axi/axi_lite] SEG_data_ad9671_core_3
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43c40000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_dma/s_axi/axi_lite] SEG_data_usdrx1_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41e00000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_spi/axi_lite/Reg] SEG_data_usdrx1_spi
|
||||
|
||||
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs processing_system7_1/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_1_HP0_DDR_LOWOCM
|
||||
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_dma/m_dest_axi] [get_bd_addr_segs processing_system7_1/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_1_HP3_DDR_LOWOCM
|
||||
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_gt/m_axi] [get_bd_addr_segs processing_system7_1/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_1_HP2_DDR_LOWOCM
|
||||
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
|
||||
# constraints
|
||||
# hdmi
|
||||
|
||||
set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk]
|
||||
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS25} [get_ports hdmi_vsync]
|
||||
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS25} [get_ports hdmi_hsync]
|
||||
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS25} [get_ports hdmi_data_e]
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS25} [get_ports hdmi_data[0]]
|
||||
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS25} [get_ports hdmi_data[1]]
|
||||
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[2]]
|
||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports hdmi_data[3]]
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[4]]
|
||||
set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[5]]
|
||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports hdmi_data[6]]
|
||||
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS25} [get_ports hdmi_data[7]]
|
||||
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports hdmi_data[8]]
|
||||
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports hdmi_data[9]]
|
||||
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[10]]
|
||||
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports hdmi_data[11]]
|
||||
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25} [get_ports hdmi_data[12]]
|
||||
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS25} [get_ports hdmi_data[13]]
|
||||
set_property -dict {PACKAGE_PIN AA29 IOSTANDARD LVCMOS25} [get_ports hdmi_data[14]]
|
||||
set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVCMOS25} [get_ports hdmi_data[15]]
|
||||
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[16]]
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[17]]
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS25} [get_ports hdmi_data[18]]
|
||||
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVCMOS25} [get_ports hdmi_data[19]]
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS25} [get_ports hdmi_data[20]]
|
||||
set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[21]]
|
||||
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS25} [get_ports hdmi_data[22]]
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports hdmi_data[23]]
|
||||
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports hdmi_int]
|
||||
|
||||
# iic
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]
|
||||
set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]
|
||||
|
||||
# gpio (switches, leds and such)
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0
|
||||
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1
|
||||
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2
|
||||
set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3
|
||||
set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## GPIO_SW_LEFT
|
||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]] ; ## GPIO_SW_CENTER
|
||||
set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## GPIO_SW_RIGHT
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## GPIO_LED_LEFT
|
||||
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]] ; ## GPIO_LED_CENTER
|
||||
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## GPIO_LED_RIGHT
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]] ; ## GPIO_LED_0
|
||||
|
||||
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]] ; ## XADC_GPIO_0
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]] ; ## XADC_GPIO_1
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]] ; ## XADC_GPIO_2
|
||||
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]] ; ## XADC_GPIO_3
|
||||
|
||||
# ultrasound
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD9} [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AH9} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AJ8} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AJ7} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG8} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AG7} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AE8} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AE7} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AH6} [get_ports rx_data_p[4]] ; ## A14 FMC_HPC_DP4_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AH5} [get_ports rx_data_n[4]] ; ## A15 FMC_HPC_DP4_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG4} [get_ports rx_data_p[5]] ; ## A18 FMC_HPC_DP5_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AG3} [get_ports rx_data_n[5]] ; ## A19 FMC_HPC_DP5_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AF6} [get_ports rx_data_p[6]] ; ## B16 FMC_HPC_DP6_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AF5} [get_ports rx_data_n[6]] ; ## B17 FMC_HPC_DP6_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AD6} [get_ports rx_data_p[7]] ; ## B12 FMC_HPC_DP7_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD5} [get_ports rx_data_n[7]] ; ## B13 FMC_HPC_DP7_M2C_N
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## D23 FMC_HPC_LA23_P
|
||||
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D24 FMC_HPC_LA23_N
|
||||
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D26 FMC_HPC_LA26_P
|
||||
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D27 FMC_HPC_LA26_N
|
||||
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports afe_mlo_p] ; ## D20 FMC_HPC_LA17_CC_P
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports afe_mlo_n] ; ## D21 FMC_HPC_LA17_CC_N
|
||||
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports afe_rst_p] ; ## G27 FMC_HPC_LA25_P
|
||||
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports afe_rst_n] ; ## G28 FMC_HPC_LA25_N
|
||||
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25} [get_ports afe_trig_p] ; ## H28 FMC_HPC_LA24_P
|
||||
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVDS_25} [get_ports afe_trig_n] ; ## H29 FMC_HPC_LA24_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_clk] ; ## C14 FMC_HPC_LA10_P
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_mlo] ; ## C15 FMC_HPC_LA10_N
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_rst] ; ## C18 FMC_HPC_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_sync] ; ## C19 FMC_HPC_LA14_N
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_sysref] ; ## C22 FMC_HPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_trig] ; ## C23 FMC_HPC_LA18_CC_N
|
||||
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_fout_clk] ; ## C10 FMC_HPC_LA06_P
|
||||
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_fout_sdio] ; ## C11 FMC_HPC_LA06_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[0]] ; ## D11 FMC_HPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[1]] ; ## D12 FMC_HPC_LA05_N
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[2]] ; ## D14 FMC_HPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[3]] ; ## D15 FMC_HPC_LA09_N
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_afe_clk] ; ## D08 FMC_HPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports spi_afe_sdio] ; ## D09 FMC_HPC_LA01_CC_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports spi_clk_csn] ; ## G10 FMC_HPC_LA03_N
|
||||
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports spi_clk_clk] ; ## G13 FMC_HPC_LA08_N
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_clk_sdio] ; ## G12 FMC_HPC_LA08_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_pdn] ; ## D17 FMC_HPC_LA13_P
|
||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_stby] ; ## D18 FMC_HPC_LA13_N
|
||||
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports clk_resetn] ; ## G16 FMC_HPC_LA12_N
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports clk_syncn] ; ## G15 FMC_HPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports clk_status] ; ## G18 FMC_HPC_LA16_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports amp_disbn] ; ## G19 FMC_HPC_LA16_N
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports prc_sck] ; ## G21 FMC_HPC_LA20_P
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports prc_cnv] ; ## G22 FMC_HPC_LA20_N
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports prc_sdo_i] ; ## G24 FMC_HPC_LA22_P
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports prc_sdo_q] ; ## G25 FMC_HPC_LA22_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports dac_sleep] ; ## G09 FMC_HPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports dac_data[0]] ; ## H26 FMC_HPC_LA21_N
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports dac_data[1]] ; ## H25 FMC_HPC_LA21_P
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports dac_data[2]] ; ## H23 FMC_HPC_LA19_N
|
||||
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports dac_data[3]] ; ## H22 FMC_HPC_LA19_P
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports dac_data[4]] ; ## H20 FMC_HPC_LA15_N
|
||||
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports dac_data[5]] ; ## H19 FMC_HPC_LA15_P
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports dac_data[6]] ; ## H17 FMC_HPC_LA11_N
|
||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports dac_data[7]] ; ## H16 FMC_HPC_LA11_P
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports dac_data[8]] ; ## H14 FMC_HPC_LA07_N
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports dac_data[9]] ; ## H13 FMC_HPC_LA07_P
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports dac_data[10]] ; ## H11 FMC_HPC_LA04_N
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports dac_data[11]] ; ## H10 FMC_HPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports dac_data[12]] ; ## H08 FMC_HPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data[13]] ; ## H07 FMC_HPC_LA02_P
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/processing_system7_1/FCLK_CLK0]
|
||||
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/processing_system7_1/FCLK_CLK1]
|
||||
create_clock -name dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/processing_system7_1/FCLK_CLK2]
|
||||
create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/processing_system7_1/FCLK_CLK3]
|
||||
create_clock -name hdmi_clk -period 6.73 [get_nets i_system_wrapper/system_i/axi_clkgen_1/inst/i_mmcm_drp/mmcm_clk_0_s]
|
||||
|
||||
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
|
||||
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk]
|
||||
|
||||
set_clock_groups -asynchronous -group {cpu_clk}
|
||||
set_clock_groups -asynchronous -group {dma_clk}
|
||||
set_clock_groups -asynchronous -group {hdmi_clk}
|
||||
set_clock_groups -asynchronous -group {rx_div_clk}
|
||||
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
|
||||
create_project ad_usdrx1_zc706 . -part xc7z045ffg900-2 -force
|
||||
set_property board xilinx.com:zynq:zc706:1.1 [current_project]
|
||||
set_property ip_repo_paths ../../../library [current_fileset]
|
||||
update_ip_catalog
|
||||
|
||||
create_bd_design "system"
|
||||
source system_bd.tcl
|
||||
|
||||
generate_target {synthesis implementation} \
|
||||
[get_files ./ad_usdrx1_zc706.srcs/sources_1/bd/system/system.bd]
|
||||
|
||||
make_wrapper -files [get_files ./ad_usdrx1_zc706.srcs/sources_1/bd/system/system.bd] -top
|
||||
import_files -force -norecurse -fileset sources_1 ./ad_usdrx1_zc706.srcs/sources_1/bd/system/hdl/system_wrapper.v
|
||||
add_files -norecurse -fileset sources_1 ../../../library/misc/usdrx1_spi.v
|
||||
add_files -norecurse -fileset sources_1 system_top.v
|
||||
add_files -norecurse -fileset constrs_1 system_constr.xdc
|
||||
|
||||
set_property top system_top [current_fileset]
|
||||
|
||||
launch_runs synth_1
|
||||
wait_on_run synth_1
|
||||
open_run synth_1
|
||||
report_timing_summary -file report_timing_summary_synth_1.log
|
||||
|
||||
launch_runs impl_1 -to_step write_bitstream
|
||||
wait_on_run impl_1
|
||||
open_run impl_1
|
||||
report_timing_summary -file report_timing_summary_impl_1.log
|
||||
|
||||
export_hardware [get_files ./ad_usdrx1_zc706.srcs/sources_1/bd/system/system.bd] \
|
||||
[get_runs impl_1] -bitstream
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
hdmi_out_clk,
|
||||
hdmi_vsync,
|
||||
hdmi_hsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
hdmi_int,
|
||||
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
|
||||
rx_ref_clk_p,
|
||||
rx_ref_clk_n,
|
||||
rx_data_p,
|
||||
rx_data_n,
|
||||
rx_sysref_p,
|
||||
rx_sysref_n,
|
||||
rx_sync_p,
|
||||
rx_sync_n,
|
||||
|
||||
spi_fout_enb_clk,
|
||||
spi_fout_enb_mlo,
|
||||
spi_fout_enb_rst,
|
||||
spi_fout_enb_sync,
|
||||
spi_fout_enb_sysref,
|
||||
spi_fout_enb_trig,
|
||||
spi_fout_clk,
|
||||
spi_fout_sdio,
|
||||
spi_afe_csn,
|
||||
spi_afe_clk,
|
||||
spi_afe_sdio,
|
||||
spi_clk_csn,
|
||||
spi_clk_clk,
|
||||
spi_clk_sdio,
|
||||
|
||||
afe_mlo_p,
|
||||
afe_mlo_n,
|
||||
afe_rst_p,
|
||||
afe_rst_n,
|
||||
afe_trig_p,
|
||||
afe_trig_n,
|
||||
|
||||
dac_sleep,
|
||||
dac_data,
|
||||
afe_pdn,
|
||||
afe_stby,
|
||||
clk_resetn,
|
||||
clk_syncn,
|
||||
clk_status,
|
||||
amp_disbn,
|
||||
prc_sck,
|
||||
prc_cnv,
|
||||
prc_sdo_i,
|
||||
prc_sdo_q);
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
inout [ 2:0] DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [ 3:0] DDR_dm;
|
||||
inout [31:0] DDR_dq;
|
||||
inout [ 3:0] DDR_dqs_n;
|
||||
inout [ 3:0] DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
|
||||
inout [14:0] gpio_bd;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_vsync;
|
||||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [23:0] hdmi_data;
|
||||
input hdmi_int;
|
||||
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
input rx_ref_clk_p;
|
||||
input rx_ref_clk_n;
|
||||
input [ 7:0] rx_data_p;
|
||||
input [ 7:0] rx_data_n;
|
||||
output rx_sysref_p;
|
||||
output rx_sysref_n;
|
||||
output rx_sync_p;
|
||||
output rx_sync_n;
|
||||
|
||||
output spi_fout_enb_clk;
|
||||
output spi_fout_enb_mlo;
|
||||
output spi_fout_enb_rst;
|
||||
output spi_fout_enb_sync;
|
||||
output spi_fout_enb_sysref;
|
||||
output spi_fout_enb_trig;
|
||||
output spi_fout_clk;
|
||||
inout spi_fout_sdio;
|
||||
output [ 3:0] spi_afe_csn;
|
||||
output spi_afe_clk;
|
||||
inout spi_afe_sdio;
|
||||
output spi_clk_csn;
|
||||
output spi_clk_clk;
|
||||
inout spi_clk_sdio;
|
||||
|
||||
output afe_mlo_p;
|
||||
output afe_mlo_n;
|
||||
output afe_rst_p;
|
||||
output afe_rst_n;
|
||||
output afe_trig_p;
|
||||
output afe_trig_n;
|
||||
|
||||
inout dac_sleep;
|
||||
inout [13:0] dac_data;
|
||||
inout afe_pdn;
|
||||
inout afe_stby;
|
||||
inout clk_resetn;
|
||||
inout clk_syncn;
|
||||
inout clk_status;
|
||||
inout amp_disbn;
|
||||
inout prc_sck;
|
||||
inout prc_cnv;
|
||||
inout prc_sdo_i;
|
||||
inout prc_sdo_q;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [43:0] gpio_i;
|
||||
wire [43:0] gpio_o;
|
||||
wire [43:0] gpio_t;
|
||||
wire [10:0] spi_csn;
|
||||
wire afe_mlo;
|
||||
wire rx_ref_clk;
|
||||
wire rx_sysref;
|
||||
wire rx_sync;
|
||||
wire [ 1:0] gpio_open;
|
||||
|
||||
// spi assignments
|
||||
|
||||
assign spi_fout_enb_clk = spi_csn[10:10];
|
||||
assign spi_fout_enb_mlo = spi_csn[ 9: 9];
|
||||
assign spi_fout_enb_rst = spi_csn[ 8: 8];
|
||||
assign spi_fout_enb_sync = spi_csn[ 7: 7];
|
||||
assign spi_fout_enb_sysref = spi_csn[ 6: 6];
|
||||
assign spi_fout_enb_trig = spi_csn[ 5: 5];
|
||||
assign spi_afe_csn = spi_csn[ 4: 1];
|
||||
assign spi_clk_csn = spi_csn[ 0: 0];
|
||||
|
||||
assign spi_fout_clk = spi_clk;
|
||||
assign spi_afe_clk = spi_clk;
|
||||
assign spi_clk_clk = spi_clk;
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (rx_ref_clk_p),
|
||||
.IB (rx_ref_clk_n),
|
||||
.O (rx_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
OBUFDS i_obufds_rx_sysref (
|
||||
.I (rx_sysref),
|
||||
.O (rx_sysref_p),
|
||||
.OB (rx_sysref_n));
|
||||
|
||||
OBUFDS i_obufds_rx_sync (
|
||||
.I (rx_sync),
|
||||
.O (rx_sync_p),
|
||||
.OB (rx_sync_n));
|
||||
|
||||
OBUFDS i_obufds_mlo (
|
||||
.I (afe_mlo),
|
||||
.O (afe_mlo_p),
|
||||
.OB (afe_mlo_n));
|
||||
|
||||
IOBUF i_iobuf_gpio_prc_sdo_q (
|
||||
.I (gpio_o[43]),
|
||||
.O (gpio_i[43]),
|
||||
.T (gpio_t[43]),
|
||||
.IO (prc_sdo_q));
|
||||
|
||||
IOBUF i_iobuf_gpio_prc_sdo_i (
|
||||
.I (gpio_o[42]),
|
||||
.O (gpio_i[42]),
|
||||
.T (gpio_t[42]),
|
||||
.IO (prc_sdo_i));
|
||||
|
||||
IOBUF i_iobuf_gpio_prc_cnv (
|
||||
.I (gpio_o[41]),
|
||||
.O (gpio_i[41]),
|
||||
.T (gpio_t[41]),
|
||||
.IO (prc_cnv));
|
||||
|
||||
IOBUF i_iobuf_gpio_prc_sck (
|
||||
.I (gpio_o[40]),
|
||||
.O (gpio_i[40]),
|
||||
.T (gpio_t[40]),
|
||||
.IO (prc_sck));
|
||||
|
||||
IOBUF i_iobuf_gpio_amp_disbn (
|
||||
.I (gpio_o[39]),
|
||||
.O (gpio_i[39]),
|
||||
.T (gpio_t[39]),
|
||||
.IO (amp_disbn));
|
||||
|
||||
IOBUF i_iobuf_gpio_clk_status (
|
||||
.I (gpio_o[38]),
|
||||
.O (gpio_i[38]),
|
||||
.T (gpio_t[38]),
|
||||
.IO (clk_status));
|
||||
|
||||
IOBUF i_iobuf_gpio_clk_syncn (
|
||||
.I (gpio_o[37]),
|
||||
.O (gpio_i[37]),
|
||||
.T (gpio_t[37]),
|
||||
.IO (clk_syncn));
|
||||
|
||||
IOBUF i_iobuf_gpio_clk_resetn (
|
||||
.I (gpio_o[36]),
|
||||
.O (gpio_i[36]),
|
||||
.T (gpio_t[36]),
|
||||
.IO (clk_resetn));
|
||||
|
||||
IOBUF i_iobuf_gpio_afe_stby (
|
||||
.I (gpio_o[35]),
|
||||
.O (gpio_i[35]),
|
||||
.T (gpio_t[35]),
|
||||
.IO (afe_stby));
|
||||
|
||||
IOBUF i_iobuf_gpio_afe_pdn (
|
||||
.I (gpio_o[34]),
|
||||
.O (gpio_i[34]),
|
||||
.T (gpio_t[34]),
|
||||
.IO (afe_pdn));
|
||||
|
||||
OBUFDS i_obufds_gpio_afe_trig (
|
||||
.I (gpio_o[33]),
|
||||
.O (afe_trig_p),
|
||||
.OB (afe_trig_n));
|
||||
|
||||
OBUFDS i_obufds_gpio_afe_rst (
|
||||
.I (gpio_o[32]),
|
||||
.O (afe_rst_p),
|
||||
.OB (afe_rst_n));
|
||||
|
||||
IOBUF i_iobuf_gpio_dac_sleep (
|
||||
.I (gpio_o[30]),
|
||||
.O (gpio_i[30]),
|
||||
.T (gpio_t[30]),
|
||||
.IO (dac_sleep));
|
||||
|
||||
genvar n;
|
||||
generate
|
||||
for (n = 0; n <= 13; n = n + 1) begin: g_iobuf_gpio_dac_data
|
||||
IOBUF i_iobuf_gpio_dac_data (
|
||||
.I (gpio_o[16+n]),
|
||||
.O (gpio_i[16+n]),
|
||||
.T (gpio_t[16+n]),
|
||||
.IO (dac_data[n]));
|
||||
end
|
||||
for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
|
||||
IOBUF i_iobuf_gpio_bd (
|
||||
.I (gpio_o[n]),
|
||||
.O (gpio_i[n]),
|
||||
.T (gpio_t[n]),
|
||||
.IO (gpio_bd[n]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
usdrx1_spi i_spi (
|
||||
.spi_fout_csn (spi_csn[10:5]),
|
||||
.spi_afe_csn (spi_csn[4:1]),
|
||||
.spi_clk_csn (spi_csn[0]),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
.spi_miso (spi_miso),
|
||||
.spi_fout_sdio (spi_fout_sdio),
|
||||
.spi_afe_sdio (spi_afe_sdio),
|
||||
.spi_clk_sdio (spi_clk_sdio));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr (DDR_addr),
|
||||
.DDR_ba (DDR_ba),
|
||||
.DDR_cas_n (DDR_cas_n),
|
||||
.DDR_ck_n (DDR_ck_n),
|
||||
.DDR_ck_p (DDR_ck_p),
|
||||
.DDR_cke (DDR_cke),
|
||||
.DDR_cs_n (DDR_cs_n),
|
||||
.DDR_dm (DDR_dm),
|
||||
.DDR_dq (DDR_dq),
|
||||
.DDR_dqs_n (DDR_dqs_n),
|
||||
.DDR_dqs_p (DDR_dqs_p),
|
||||
.DDR_odt (DDR_odt),
|
||||
.DDR_ras_n (DDR_ras_n),
|
||||
.DDR_reset_n (DDR_reset_n),
|
||||
.DDR_we_n (DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio (FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_int (hdmi_int),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.mlo_clk (afe_mlo),
|
||||
.rx_data_n (rx_data_n),
|
||||
.rx_data_p (rx_data_p),
|
||||
.rx_ref_clk (rx_ref_clk),
|
||||
.rx_sync (rx_sync),
|
||||
.rx_sysref (rx_sysref),
|
||||
.spi_clk_i (spi_clk),
|
||||
.spi_clk_o (spi_clk),
|
||||
.spi_csn_i (spi_csn),
|
||||
.spi_csn_o (spi_csn),
|
||||
.spi_sdi_i (spi_miso),
|
||||
.spi_sdo_i (spi_mosi),
|
||||
.spi_sdo_o (spi_mosi));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue