ad_datafmt: Add support for 8 bit data width
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2f68c546f1
commit
ac4d78b95d
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@ -41,6 +41,7 @@ module ad_datafmt #(
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// data bus width
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// data bus width
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parameter DATA_WIDTH = 16,
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parameter DATA_WIDTH = 16,
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parameter OCTETS_PER_SAMPLE = 2,
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parameter DISABLE = 0) (
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parameter DISABLE = 0) (
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// data path
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// data path
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@ -49,7 +50,7 @@ module ad_datafmt #(
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input valid,
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input valid,
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input [(DATA_WIDTH-1):0] data,
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input [(DATA_WIDTH-1):0] data,
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output valid_out,
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output valid_out,
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output [15:0] data_out,
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output [(8*OCTETS_PER_SAMPLE-1):0] data_out,
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// control signals
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// control signals
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@ -60,12 +61,12 @@ module ad_datafmt #(
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// internal registers
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// internal registers
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reg valid_int = 'd0;
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reg valid_int = 'd0;
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reg [15:0] data_int = 'd0;
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reg [(8*OCTETS_PER_SAMPLE-1):0] data_int = 'd0;
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// internal signals
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// internal signals
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wire type_s;
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wire type_s;
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wire [15:0] data_out_s;
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wire [(8*OCTETS_PER_SAMPLE-1):0] data_out_s;
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// data-path disable
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// data-path disable
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@ -84,13 +85,13 @@ module ad_datafmt #(
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assign type_s = dfmt_enable & dfmt_type;
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assign type_s = dfmt_enable & dfmt_type;
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generate
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generate
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if (DATA_WIDTH < 16) begin
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if (DATA_WIDTH < 8*OCTETS_PER_SAMPLE) begin
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wire signext_s;
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wire signext_s;
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wire sign_s;
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wire sign_s;
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assign signext_s = dfmt_enable & dfmt_se;
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assign signext_s = dfmt_enable & dfmt_se;
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assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
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assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]);
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assign data_out_s[15:DATA_WIDTH] = {(16-DATA_WIDTH){sign_s}};
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assign data_out_s[(8*OCTETS_PER_SAMPLE-1):DATA_WIDTH] = {((8*OCTETS_PER_SAMPLE)-DATA_WIDTH){sign_s}};
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end
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end
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endgenerate
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endgenerate
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@ -99,7 +100,7 @@ module ad_datafmt #(
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always @(posedge clk) begin
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always @(posedge clk) begin
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valid_int <= valid;
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valid_int <= valid;
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data_int <= data_out_s[15:0];
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data_int <= data_out_s;
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end
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end
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endmodule
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endmodule
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