zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase

main
Adrian Costina 2017-04-13 10:03:44 +03:00 committed by Lars-Peter Clausen
parent 8549420af5
commit ac5efc9adc
12 changed files with 474 additions and 474 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

278
library/axi_i2s_adi/axi_i2s_adi.vhd
View File

@ -38,72 +38,72 @@ entity axi_i2s_adi is
port port
( (
-- Serial Data interface -- Serial Data interface
DATA_CLK_I : in std_logic; data_clk_i : in std_logic;
BCLK_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0); bclk_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
LRCLK_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0); lrclk_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
SDATA_O : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0); sdata_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
SDATA_I : in std_logic_vector(NUM_OF_CHANNEL - 1 downto 0); sdata_i : in std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
-- AXI Streaming DMA TX interface -- AXI Streaming DMA TX interface
S_AXIS_ACLK : in std_logic; s_axis_aclk : in std_logic;
S_AXIS_ARESETN : in std_logic; s_axis_aresetn : in std_logic;
S_AXIS_TREADY : out std_logic; s_axis_tready : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0); s_axis_tdata : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic; s_axis_tlast : in std_logic;
S_AXIS_TVALID : in std_logic; s_axis_tvalid : in std_logic;
-- AXI Streaming DMA RX interface -- AXI Streaming DMA RX interface
M_AXIS_ACLK : in std_logic; m_axis_aclk : in std_logic;
M_AXIS_TREADY : in std_logic; m_axis_tready : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0); m_axis_tdata : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic; m_axis_tlast : out std_logic;
M_AXIS_TVALID : out std_logic; m_axis_tvalid : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0); m_axis_tkeep : out std_logic_vector(3 downto 0);
--PL330 DMA TX interface --PL330 DMA TX interface
DMA_REQ_TX_ACLK : in std_logic; dma_req_tx_aclk : in std_logic;
DMA_REQ_TX_RSTN : in std_logic; dma_req_tx_rstn : in std_logic;
DMA_REQ_TX_DAVALID : in std_logic; dma_req_tx_davalid : in std_logic;
DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0); dma_req_tx_datype : in std_logic_vector(1 downto 0);
DMA_REQ_TX_DAREADY : out std_logic; dma_req_tx_daready : out std_logic;
DMA_REQ_TX_DRVALID : out std_logic; dma_req_tx_drvalid : out std_logic;
DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0); dma_req_tx_drtype : out std_logic_vector(1 downto 0);
DMA_REQ_TX_DRLAST : out std_logic; dma_req_tx_drlast : out std_logic;
DMA_REQ_TX_DRREADY : in std_logic; dma_req_tx_drready : in std_logic;
-- PL330 DMA RX interface -- PL330 DMA RX interface
DMA_REQ_RX_ACLK : in std_logic; dma_req_rx_aclk : in std_logic;
DMA_REQ_RX_RSTN : in std_logic; dma_req_rx_rstn : in std_logic;
DMA_REQ_RX_DAVALID : in std_logic; dma_req_rx_davalid : in std_logic;
DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0); dma_req_rx_datype : in std_logic_vector(1 downto 0);
DMA_REQ_RX_DAREADY : out std_logic; dma_req_rx_daready : out std_logic;
DMA_REQ_RX_DRVALID : out std_logic; dma_req_rx_drvalid : out std_logic;
DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0); dma_req_rx_drtype : out std_logic_vector(1 downto 0);
DMA_REQ_RX_DRLAST : out std_logic; dma_req_rx_drlast : out std_logic;
DMA_REQ_RX_DRREADY : in std_logic; dma_req_rx_drready : in std_logic;
-- AXI bus interface -- AXI bus interface
S_AXI_ACLK : in std_logic; s_axi_aclk : in std_logic;
S_AXI_ARESETN : in std_logic; s_axi_aresetn : in std_logic;
S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic; s_axi_awvalid : in std_logic;
S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic; s_axi_wvalid : in std_logic;
S_AXI_BREADY : in std_logic; s_axi_bready : in std_logic;
S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic; s_axi_arvalid : in std_logic;
S_AXI_RREADY : in std_logic; s_axi_rready : in std_logic;
S_AXI_ARREADY : out std_logic; s_axi_arready : out std_logic;
S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic; s_axi_rvalid : out std_logic;
S_AXI_WREADY : out std_logic; s_axi_wready : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic; s_axi_bvalid : out std_logic;
S_AXI_AWREADY : out std_logic; s_axi_awready : out std_logic;
S_AXI_AWPROT : in std_logic_vector(2 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0) s_axi_arprot : in std_logic_vector(2 downto 0)
); );
end entity axi_i2s_adi; end entity axi_i2s_adi;
@ -167,10 +167,10 @@ begin
const_1 <= '1'; const_1 <= '1';
process (S_AXI_ACLK) process (s_axi_aclk)
begin begin
if rising_edge(S_AXI_ACLK) then if rising_edge(s_axi_aclk) then
if S_AXI_ARESETN = '0' then if s_axi_aresetn = '0' then
cnt <= 0; cnt <= 0;
else else
cnt <= (cnt + 1) mod 2**16; cnt <= (cnt + 1) mod 2**16;
@ -185,16 +185,16 @@ begin
FIFO_DWIDTH => 24 FIFO_DWIDTH => 24
) )
port map( port map(
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
fifo_reset => tx_fifo_reset, fifo_reset => tx_fifo_reset,
enable => tx_enable, enable => tx_enable,
S_AXIS_ACLK => S_AXIS_ACLK, s_axis_aclk => s_axis_aclk,
S_AXIS_TREADY => S_AXIS_TREADY, s_axis_tready => s_axis_tready,
S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8), s_axis_tdata => s_axis_tdata(31 downto 8),
S_AXIS_TLAST => S_AXIS_TLAST, s_axis_tlast => s_axis_tlast,
S_AXIS_TVALID => S_AXIS_TVALID, s_axis_tvalid => s_axis_tvalid,
out_stb => tx_stb, out_stb => tx_stb,
out_ack => tx_ack, out_ack => tx_ack,
@ -203,7 +203,7 @@ begin
end generate; end generate;
no_streaming_dma_tx_gen: if DMA_TYPE /= 0 or HAS_TX /= 1 generate no_streaming_dma_tx_gen: if DMA_TYPE /= 0 or HAS_TX /= 1 generate
S_AXIS_TREADY <= '0'; s_axis_tready <= '0';
end generate; end generate;
streaming_dma_rx_gen: if DMA_TYPE = 0 and HAS_RX = 1 generate streaming_dma_rx_gen: if DMA_TYPE = 0 and HAS_RX = 1 generate
@ -213,8 +213,8 @@ begin
FIFO_DWIDTH => 24 FIFO_DWIDTH => 24
) )
port map( port map(
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
fifo_reset => tx_fifo_reset, fifo_reset => tx_fifo_reset,
enable => tx_enable, enable => tx_enable,
@ -224,22 +224,22 @@ begin
in_ack => rx_ack, in_ack => rx_ack,
in_data => rx_data, in_data => rx_data,
M_AXIS_ACLK => M_AXIS_ACLK, m_axis_aclk => m_axis_aclk,
M_AXIS_TREADY => M_AXIS_TREADY, m_axis_tready => m_axis_tready,
M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8), m_axis_tdata => m_axis_tdata(31 downto 8),
M_AXIS_TLAST => M_AXIS_TLAST, m_axis_tlast => m_axis_tlast,
M_AXIS_TVALID => M_AXIS_TVALID, m_axis_tvalid => m_axis_tvalid,
M_AXIS_TKEEP => M_AXIS_TKEEP m_axis_tkeep => m_axis_tkeep
); );
M_AXIS_TDATA(7 downto 0) <= (others => '0'); m_axis_tdata(7 downto 0) <= (others => '0');
end generate; end generate;
no_streaming_dma_rx_gen: if DMA_TYPE /= 0 or HAS_RX /= 1 generate no_streaming_dma_rx_gen: if DMA_TYPE /= 0 or HAS_RX /= 1 generate
M_AXIS_TDATA <= (others => '0'); m_axis_tdata <= (others => '0');
M_AXIS_TLAST <= '0'; m_axis_tlast <= '0';
M_AXIS_TVALID <= '0'; m_axis_tvalid <= '0';
M_AXIS_TKEEP <= (others => '0'); m_axis_tkeep <= (others => '0');
end generate; end generate;
@ -254,8 +254,8 @@ begin
FIFO_DIRECTION => 0 FIFO_DIRECTION => 0
) )
port map ( port map (
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
fifo_reset => tx_fifo_reset, fifo_reset => tx_fifo_reset,
enable => tx_enable, enable => tx_enable,
@ -266,23 +266,23 @@ begin
out_stb => tx_stb, out_stb => tx_stb,
out_data => tx_data, out_data => tx_data,
dclk => DMA_REQ_TX_ACLK, dclk => dma_req_tx_aclk,
dresetn => DMA_REQ_TX_RSTN, dresetn => dma_req_tx_rstn,
davalid => DMA_REQ_TX_DAVALID, davalid => dma_req_tx_davalid,
daready => DMA_REQ_TX_DAREADY, daready => dma_req_tx_daready,
datype => DMA_REQ_TX_DATYPE, datype => dma_req_tx_datype,
drvalid => DMA_REQ_TX_DRVALID, drvalid => dma_req_tx_drvalid,
drready => DMA_REQ_TX_DRREADY, drready => dma_req_tx_drready,
drtype => DMA_REQ_TX_DRTYPE, drtype => dma_req_tx_drtype,
drlast => DMA_REQ_TX_DRLAST drlast => dma_req_tx_drlast
); );
end generate; end generate;
no_pl330_dma_tx_gen: if DMA_TYPE /= 1 or HAS_TX /= 1 generate no_pl330_dma_tx_gen: if DMA_TYPE /= 1 or HAS_TX /= 1 generate
DMA_REQ_TX_DAREADY <= '0'; dma_req_tx_daready <= '0';
DMA_REQ_TX_DRVALID <= '0'; dma_req_tx_drvalid <= '0';
DMA_REQ_TX_DRTYPE <= (others => '0'); dma_req_tx_drtype <= (others => '0');
DMA_REQ_TX_DRLAST <= '0'; dma_req_tx_drlast <= '0';
end generate; end generate;
pl330_dma_rx_gen: if DMA_TYPE = 1 and HAS_RX = 1 generate pl330_dma_rx_gen: if DMA_TYPE = 1 and HAS_RX = 1 generate
@ -295,8 +295,8 @@ begin
FIFO_DIRECTION => 1 FIFO_DIRECTION => 1
) )
port map ( port map (
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
fifo_reset => rx_fifo_reset, fifo_reset => rx_fifo_reset,
enable => rx_enable, enable => rx_enable,
@ -307,24 +307,24 @@ begin
out_data => rx_sample, out_data => rx_sample,
out_ack => rx_fifo_ack, out_ack => rx_fifo_ack,
dclk => DMA_REQ_RX_ACLK, dclk => dma_req_rx_aclk,
dresetn => DMA_REQ_RX_RSTN, dresetn => dma_req_rx_rstn,
davalid => DMA_REQ_RX_DAVALID, davalid => dma_req_rx_davalid,
daready => DMA_REQ_RX_DAREADY, daready => dma_req_rx_daready,
datype => DMA_REQ_RX_DATYPE, datype => dma_req_rx_datype,
drvalid => DMA_REQ_RX_DRVALID, drvalid => dma_req_rx_drvalid,
drready => DMA_REQ_RX_DRREADY, drready => dma_req_rx_drready,
drtype => DMA_REQ_RX_DRTYPE, drtype => dma_req_rx_drtype,
drlast => DMA_REQ_RX_DRLAST drlast => dma_req_rx_drlast
); );
end generate; end generate;
no_pl330_dma_rx_gen: if DMA_TYPE /= 1 or HAS_RX /= 1 generate no_pl330_dma_rx_gen: if DMA_TYPE /= 1 or HAS_RX /= 1 generate
DMA_REQ_RX_DAREADY <= '0'; dma_req_rx_daready <= '0';
DMA_REQ_RX_DRVALID <= '0'; dma_req_rx_drvalid <= '0';
DMA_REQ_RX_DRTYPE <= (others => '0'); dma_req_rx_drtype <= (others => '0');
DMA_REQ_RX_DRLAST <= '0'; dma_req_rx_drlast <= '0';
end generate; end generate;
ctrl : entity i2s_controller ctrl : entity i2s_controller
@ -337,14 +337,14 @@ begin
C_HAS_RX => HAS_RX C_HAS_RX => HAS_RX
) )
port map ( port map (
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
data_clk => DATA_CLK_I, data_clk => data_clk_i,
BCLK_O => BCLK_O, bclk_o => bclk_o,
LRCLK_O => LRCLK_O, lrclk_o => lrclk_o,
SDATA_O => SDATA_O, sdata_o => sdata_o,
SDATA_I => SDATA_I, sdata_i => sdata_i,
tx_enable => tx_enable, tx_enable => tx_enable,
tx_ack => tx_ack, tx_ack => tx_ack,
@ -376,25 +376,25 @@ begin
C_NUM_REG => 12 C_NUM_REG => 12
) )
port map( port map(
S_AXI_ACLK => S_AXI_ACLK, s_axi_aclk => s_axi_aclk,
S_AXI_ARESETN => S_AXI_ARESETN, s_axi_aresetn => s_axi_aresetn,
S_AXI_AWADDR => S_AXI_AWADDR, s_axi_awaddr => s_axi_awaddr,
S_AXI_AWVALID => S_AXI_AWVALID, s_axi_awvalid => s_axi_awvalid,
S_AXI_WDATA => S_AXI_WDATA, s_axi_wdata => s_axi_wdata,
S_AXI_WSTRB => S_AXI_WSTRB, s_axi_wstrb => s_axi_wstrb,
S_AXI_WVALID => S_AXI_WVALID, s_axi_wvalid => s_axi_wvalid,
S_AXI_BREADY => S_AXI_BREADY, s_axi_bready => s_axi_bready,
S_AXI_ARADDR => S_AXI_ARADDR, s_axi_araddr => s_axi_araddr,
S_AXI_ARVALID => S_AXI_ARVALID, s_axi_arvalid => s_axi_arvalid,
S_AXI_RREADY => S_AXI_RREADY, s_axi_rready => s_axi_rready,
S_AXI_ARREADY => S_AXI_ARREADY, s_axi_arready => s_axi_arready,
S_AXI_RDATA => S_AXI_RDATA, s_axi_rdata => s_axi_rdata,
S_AXI_RRESP => S_AXI_RRESP, s_axi_rresp => s_axi_rresp,
S_AXI_RVALID => S_AXI_RVALID, s_axi_rvalid => s_axi_rvalid,
S_AXI_WREADY => S_AXI_WREADY, s_axi_wready => s_axi_wready,
S_AXI_BRESP => S_AXI_BRESP, s_axi_bresp => s_axi_bresp,
S_AXI_BVALID => S_AXI_BVALID, s_axi_bvalid => s_axi_bvalid,
S_AXI_AWREADY => S_AXI_AWREADY, s_axi_awready => s_axi_awready,
rd_addr => rd_addr, rd_addr => rd_addr,
rd_data => rd_data, rd_data => rd_data,
@ -418,10 +418,10 @@ begin
end case; end case;
end process; end process;
process(S_AXI_ACLK) is process(s_axi_aclk) is
begin begin
if rising_edge(S_AXI_ACLK) then if rising_edge(s_axi_aclk) then
if S_AXI_ARESETN = '0' then if s_axi_aresetn = '0' then
I2S_RESET_REG <= (others => '0'); I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0'); I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0'); I2S_CLK_CONTROL_REG <= (others => '0');

4
library/axi_i2s_adi/axi_i2s_adi_constr.xdc
View File

@ -1,5 +1,5 @@
set ctrl_clk [get_clocks -of_objects [get_ports S_AXI_ACLK]] set ctrl_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set data_clk [get_clocks -of_objects [get_ports DATA_CLK_I]] set data_clk [get_clocks -of_objects [get_ports data_clk_i]]
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier cdc_sync_stage1_*_reg] \ [get_cells -hier cdc_sync_stage1_*_reg] \

88
library/axi_i2s_adi/axi_i2s_adi_ip.tcl
View File

@ -22,91 +22,91 @@ adi_ip_files axi_i2s_adi [list \
adi_ip_properties axi_i2s_adi adi_ip_properties axi_i2s_adi
adi_ip_infer_streaming_interfaces axi_i2s_adi adi_ip_infer_streaming_interfaces axi_i2s_adi
adi_add_bus "DMA_ACK_RX" "slave" \ adi_add_bus "dma_ack_rx" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ \ { \
{"DMA_REQ_RX_DAVALID" "TVALID"} \ {"dma_req_rx_davalid" "TVALID"} \
{"DMA_REQ_RX_DAREADY" "TREADY"} \ {"dma_req_rx_daready" "TREADY"} \
{"DMA_REQ_RX_DATYPE" "TUSER"} \ {"dma_req_rx_datype" "TUSER"} \
} }
adi_add_bus "DMA_REQ_RX" "master" \ adi_add_bus "dma_req_rx" "master" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ \ { \
{"DMA_REQ_RX_DRVALID" "TVALID"} \ {"dma_req_rx_drvalid" "TVALID"} \
{"DMA_REQ_RX_DRREADY" "TREADY"} \ {"dma_req_rx_drready" "TREADY"} \
{"DMA_REQ_RX_DRTYPE" "TUSER"} \ {"dma_req_rx_drtype" "TUSER"} \
{"DMA_REQ_RX_DRLAST" "TLAST"} \ {"dma_req_rx_drlast" "TLAST"} \
} }
# Clock and reset are for both DMA_REQ and DMA_ACK # Clock and reset are for both dma_req and dma_ack
adi_add_bus_clock "DMA_REQ_RX_ACLK" "DMA_REQ_RX:DMA_ACK_RX" "DMA_REQ_RX_RSTN" adi_add_bus_clock "dma_req_rx_aclk" "dma_req_rx:dma_ack_rx" "dma_req_rx_rstn"
adi_add_bus "DMA_ACK_TX" "slave" \ adi_add_bus "dma_ack_tx" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ \ { \
{"DMA_REQ_TX_DAVALID" "TVALID"} \ {"dma_req_tx_davalid" "TVALID"} \
{"DMA_REQ_TX_DAREADY" "TREADY"} \ {"dma_req_tx_daready" "TREADY"} \
{"DMA_REQ_TX_DATYPE" "TUSER"} \ {"dma_req_tx_datype" "TUSER"} \
} }
adi_add_bus "DMA_REQ_TX" "master" \ adi_add_bus "dma_req_tx" "master" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ \ { \
{"DMA_REQ_TX_DRVALID" "TVALID"} \ {"dma_req_tx_drvalid" "TVALID"} \
{"DMA_REQ_TX_DRREADY" "TREADY"} \ {"dma_req_tx_drready" "TREADY"} \
{"DMA_REQ_TX_DRTYPE" "TUSER"} \ {"dma_req_tx_drtype" "TUSER"} \
{"DMA_REQ_TX_DRLAST" "TLAST"} \ {"dma_req_tx_drlast" "TLAST"} \
} }
# Clock and reset are for both DMA_REQ and DMA_ACK # Clock and reset are for both dma_req and dma_ack
adi_add_bus_clock "DMA_REQ_TX_ACLK" "DMA_REQ_TX:DMA_ACK_TX" "DMA_REQ_TX_RSTN" adi_add_bus_clock "dma_req_tx_aclk" "dma_req_tx:dma_ack_tx" "dma_req_tx_rstn"
adi_add_bus "I2S" "master" \ adi_add_bus "i2s" "master" \
"analog.com:interface:i2s_rtl:1.0" \ "analog.com:interface:i2s_rtl:1.0" \
"analog.com:interface:i2s:1.0" \ "analog.com:interface:i2s:1.0" \
{ \ { \
{"BCLK_O" "BCLK"} \ {"bclk_o" "BCLK"} \
{"LRCLK_O" "LRCLK"} \ {"lrclk_o" "LRCLK"} \
{"SDATA_O" "SDATA_OUT"} \ {"sdata_o" "SDATA_OUT"} \
{"SDATA_I" "SDATA_IN"} \ {"sdata_i" "SDATA_IN"} \
} }
adi_add_bus_clock "DATA_CLK_I" "i2s" adi_add_bus_clock "data_clk_i" "i2s"
adi_set_bus_dependency "S_AXIS" "S_AXIS" \ adi_set_bus_dependency "s_axis" "s_axis" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
adi_set_bus_dependency "M_AXIS" "M_AXIS" \ adi_set_bus_dependency "m_axis" "m_axis" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
adi_set_bus_dependency "DMA_ACK_TX" "DMA_REQ_TX_DA" \ adi_set_bus_dependency "dma_ack_tx" "dma_req_tx_da" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_REQ_TX" "DMA_REQ_TX_DR" \ adi_set_bus_dependency "dma_req_tx" "dma_req_tx_dr" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_TX_ACLK" \ adi_set_ports_dependency "dma_req_tx_aclk" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_TX_RSTN" \ adi_set_ports_dependency "dma_req_tx_rstn" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_ACK_RX" "DMA_REQ_RX_DA" \ adi_set_bus_dependency "dma_ack_rx" "dma_req_rx_da" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_REQ_RX" "DMA_REQ_RX_DR" \ adi_set_bus_dependency "dma_req_rx" "dma_req_rx_dr" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_RX_ACLK" \ adi_set_ports_dependency "dma_req_rx_aclk" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_RX_RSTN" \ adi_set_ports_dependency "dma_req_rx_rstn" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axis_aresetn -clear [ipx::current_core]
# Tie-off optional inputs to 0 # Tie-off optional inputs to 0
set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}" -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}" -of_objects [ipx::current_core]]
# Incorrectly inferred interfaces # Incorrectly inferred interfaces
ipx::remove_bus_interface DMA_REQ_TX_RSTN [ipx::current_core] ipx::remove_bus_interface dma_req_tx_rstn [ipx::current_core]
ipx::remove_bus_interface DMA_REQ_RX_RSTN [ipx::current_core] ipx::remove_bus_interface dma_req_rx_rstn [ipx::current_core]
ipx::remove_bus_interface DMA_REQ_TX_ACLK [ipx::current_core] ipx::remove_bus_interface dma_req_tx_aclk [ipx::current_core]
ipx::remove_bus_interface DMA_REQ_RX_ACLK [ipx::current_core] ipx::remove_bus_interface dma_req_rx_aclk [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

26
library/axi_i2s_adi/i2s_controller.vhd
View File

@ -59,10 +59,10 @@ entity i2s_controller is
resetn : in std_logic; -- System reset resetn : in std_logic; -- System reset
data_clk : in std_logic; -- Data clock should be less than clk / 4 data_clk : in std_logic; -- Data clock should be less than clk / 4
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock bclk_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock lrclk_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output sdata_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input sdata_i : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input
tx_enable : in Boolean; -- Enable TX tx_enable : in Boolean; -- Enable TX
tx_ack : out std_logic; -- Request new Slot Data tx_ack : out std_logic; -- Request new Slot Data
@ -164,29 +164,29 @@ begin
begin begin
if rising_edge(data_clk) then if rising_edge(data_clk) then
if data_resetn = '0' then if data_resetn = '0' then
BCLK_O <= (others => '1'); bclk_o <= (others => '1');
LRCLK_O <= (others => '1'); lrclk_o <= (others => '1');
SDATA_O <= (others => '0'); sdata_o <= (others => '0');
else else
if C_BCLK_POL = 0 then if C_BCLK_POL = 0 then
BCLK_O <= (others => tx_sync_fifo_out(2)); bclk_o <= (others => tx_sync_fifo_out(2));
else else
BCLK_O <= (others => not tx_sync_fifo_out(2)); bclk_o <= (others => not tx_sync_fifo_out(2));
end if; end if;
if C_LRCLK_POL = 0 then if C_LRCLK_POL = 0 then
LRCLK_O <= (others => tx_sync_fifo_out(3)); lrclk_o <= (others => tx_sync_fifo_out(3));
else else
LRCLK_O <= (others => not tx_sync_fifo_out(3)); lrclk_o <= (others => not tx_sync_fifo_out(3));
end if; end if;
if C_HAS_TX = 1 then if C_HAS_TX = 1 then
SDATA_O <= tx_sync_fifo_out(3 + NUM_TX downto 4); sdata_o <= tx_sync_fifo_out(3 + NUM_TX downto 4);
end if; end if;
if C_HAS_RX = 1 then if C_HAS_RX = 1 then
rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0); rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0);
rx_sync_fifo_in(3 + NUM_RX downto 4) <= SDATA_I; rx_sync_fifo_in(3 + NUM_RX downto 4) <= sdata_i;
end if; end if;
end if; end if;
end if; end if;

174
library/axi_spdif_rx/axi_spdif_rx.vhd
View File

@ -65,47 +65,47 @@ entity axi_spdif_rx is
spdif_rx_i_dbg : out std_logic; spdif_rx_i_dbg : out std_logic;
--AXI Lite inter face --AXI Lite inter face
S_AXI_ACLK : in std_logic; s_axi_aclk : in std_logic;
S_AXI_ARESETN : in std_logic; s_axi_aresetn : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic; s_axi_awvalid : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic; s_axi_wvalid : in std_logic;
S_AXI_BREADY : in std_logic; s_axi_bready : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic; s_axi_arvalid : in std_logic;
S_AXI_RREADY : in std_logic; s_axi_rready : in std_logic;
S_AXI_ARREADY : out std_logic; s_axi_arready : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic; s_axi_rvalid : out std_logic;
S_AXI_WREADY : out std_logic; s_axi_wready : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic; s_axi_bvalid : out std_logic;
S_AXI_AWREADY : out std_logic; s_axi_awready : out std_logic;
S_AXI_AWPROT : in std_logic_vector(2 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0);
--AXI STREAM interface --AXI STREAM interface
M_AXIS_ACLK : in std_logic; m_axis_aclk : in std_logic;
M_AXIS_TREADY : in std_logic; m_axis_tready : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0); m_axis_tdata : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic; m_axis_tlast : out std_logic;
M_AXIS_TVALID : out std_logic; m_axis_tvalid : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0); m_axis_tkeep : out std_logic_vector(3 downto 0);
--PL330 DMA interface --PL330 DMA interface
DMA_REQ_ACLK : in std_logic; dma_req_aclk : in std_logic;
DMA_REQ_RSTN : in std_logic; dma_req_rstn : in std_logic;
DMA_REQ_DAVALID : in std_logic; dma_req_davalid : in std_logic;
DMA_REQ_DATYPE : in std_logic_vector(1 downto 0); dma_req_datype : in std_logic_vector(1 downto 0);
DMA_REQ_DAREADY : out std_logic; dma_req_daready : out std_logic;
DMA_REQ_DRVALID : out std_logic; dma_req_drvalid : out std_logic;
DMA_REQ_DRTYPE : out std_logic_vector(1 downto 0); dma_req_drtype : out std_logic_vector(1 downto 0);
DMA_REQ_DRLAST : out std_logic; dma_req_drlast : out std_logic;
DMA_REQ_DRREADY : in std_logic dma_req_drready : in std_logic
); );
end entity axi_spdif_rx; end entity axi_spdif_rx;
@ -214,19 +214,19 @@ begin
FIFO_DWIDTH => 32 FIFO_DWIDTH => 32
) )
port map ( port map (
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
fifo_reset => fifo_reset, fifo_reset => fifo_reset,
enable => enable, enable => enable,
period_len => 11, period_len => 11,
M_AXIS_ACLK => M_AXIS_ACLK, m_axis_aclk => m_axis_aclk,
M_AXIS_TREADY => M_AXIS_TREADY, m_axis_tready => m_axis_tready,
M_AXIS_TDATA => M_AXIS_TDATA, m_axis_tdata => m_axis_tdata,
M_AXIS_TLAST => M_AXIS_TLAST, m_axis_tlast => m_axis_tlast,
M_AXIS_TVALID => M_AXIS_TVALID, m_axis_tvalid => m_axis_tvalid,
M_AXIS_TKEEP => M_AXIS_TKEEP, m_axis_tkeep => m_axis_tkeep,
-- Write port -- Write port
in_stb => sample_wr, in_stb => sample_wr,
@ -236,9 +236,9 @@ begin
end generate; end generate;
no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate
M_AXIS_TVALID <= '0'; m_axis_tvalid <= '0';
M_AXIS_TLAST <= '0'; m_axis_tlast <= '0';
M_AXIS_TKEEP <= "0000"; m_axis_tkeep <= "0000";
end generate; end generate;
pl330_dma_gen: if C_DMA_TYPE = 1 generate pl330_dma_gen: if C_DMA_TYPE = 1 generate
@ -251,8 +251,8 @@ begin
FIFO_DIRECTION => 0 FIFO_DIRECTION => 0
) )
port map ( port map (
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
fifo_reset => fifo_reset, fifo_reset => fifo_reset,
enable => enable, enable => enable,
@ -262,23 +262,23 @@ begin
out_ack => tx_fifo_stb, out_ack => tx_fifo_stb,
out_data => sampled_data, out_data => sampled_data,
dclk => DMA_REQ_ACLK, dclk => dma_req_aclk,
dresetn => DMA_REQ_RSTN, dresetn => dma_req_rstn,
davalid => DMA_REQ_DAVALID, davalid => dma_req_davalid,
daready => DMA_REQ_DAREADY, daready => dma_req_daready,
datype => DMA_REQ_DATYPE, datype => dma_req_datype,
drvalid => DMA_REQ_DRVALID, drvalid => dma_req_drvalid,
drready => DMA_REQ_DRREADY, drready => dma_req_drready,
drtype => DMA_REQ_DRTYPE, drtype => dma_req_drtype,
drlast => DMA_REQ_DRLAST drlast => dma_req_drlast
); );
end generate; end generate;
no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate
DMA_REQ_DAREADY <= '0'; dma_req_daready <= '0';
DMA_REQ_DRVALID <= '0'; dma_req_drvalid <= '0';
DMA_REQ_DRTYPE <= (others => '0'); dma_req_drtype <= (others => '0');
DMA_REQ_DRLAST <= '0'; dma_req_drlast <= '0';
end generate; end generate;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
@ -291,7 +291,7 @@ begin
) )
port map port map
( (
up_clk => S_AXI_ACLK, up_clk => s_axi_aclk,
status_rd => rd_ack, status_rd => rd_ack,
lock => lock, lock => lock,
chas => conf_chas, chas => conf_chas,
@ -313,7 +313,7 @@ begin
) )
port map port map
( (
up_clk => S_AXI_ACLK, up_clk => s_axi_aclk,
rxen => conf_rxen, rxen => conf_rxen,
spdif => spdif_rx_i, spdif => spdif_rx_i,
lock => lock, lock => lock,
@ -343,7 +343,7 @@ begin
) )
port map port map
( (
up_clk => S_AXI_ACLK, up_clk => s_axi_aclk,
conf_rxen => conf_rxen, conf_rxen => conf_rxen,
conf_sample => conf_sample, conf_sample => conf_sample,
conf_valid => conf_valid, conf_valid => conf_valid,
@ -376,25 +376,25 @@ begin
C_NUM_REG => 4 C_NUM_REG => 4
) )
port map( port map(
S_AXI_ACLK => S_AXI_ACLK, s_axi_aclk => s_axi_aclk,
S_AXI_ARESETN => S_AXI_ARESETN, s_axi_aresetn => s_axi_aresetn,
S_AXI_AWADDR => S_AXI_AWADDR, s_axi_awaddr => s_axi_awaddr,
S_AXI_AWVALID => S_AXI_AWVALID, s_axi_awvalid => s_axi_awvalid,
S_AXI_WDATA => S_AXI_WDATA, s_axi_wdata => s_axi_wdata,
S_AXI_WSTRB => S_AXI_WSTRB, s_axi_wstrb => s_axi_wstrb,
S_AXI_WVALID => S_AXI_WVALID, s_axi_wvalid => s_axi_wvalid,
S_AXI_BREADY => S_AXI_BREADY, s_axi_bready => s_axi_bready,
S_AXI_ARADDR => S_AXI_ARADDR, s_axi_araddr => s_axi_araddr,
S_AXI_ARVALID => S_AXI_ARVALID, s_axi_arvalid => s_axi_arvalid,
S_AXI_RREADY => S_AXI_RREADY, s_axi_rready => s_axi_rready,
S_AXI_ARREADY => S_AXI_ARREADY, s_axi_arready => s_axi_arready,
S_AXI_RDATA => S_AXI_RDATA, s_axi_rdata => s_axi_rdata,
S_AXI_RRESP => S_AXI_RRESP, s_axi_rresp => s_axi_rresp,
S_AXI_RVALID => S_AXI_RVALID, s_axi_rvalid => s_axi_rvalid,
S_AXI_WREADY => S_AXI_WREADY, s_axi_wready => s_axi_wready,
S_AXI_BRESP => S_AXI_BRESP, s_axi_bresp => s_axi_bresp,
S_AXI_BVALID => S_AXI_BVALID, s_axi_bvalid => s_axi_bvalid,
S_AXI_AWREADY => S_AXI_AWREADY, s_axi_awready => s_axi_awready,
rd_addr => rd_addr, rd_addr => rd_addr,
rd_data => rd_data, rd_data => rd_data,
@ -407,10 +407,10 @@ begin
wr_stb => wr_stb wr_stb => wr_stb
); );
process (S_AXI_ACLK) process (s_axi_aclk)
begin begin
if rising_edge(S_AXI_ACLK) then if rising_edge(s_axi_aclk) then
if S_AXI_ARESETN = '0' then if s_axi_aresetn = '0' then
control_reg <= (others => '0'); control_reg <= (others => '0');
else else
if wr_stb = '1' then if wr_stb = '1' then

34
library/axi_spdif_rx/axi_spdif_rx_ip.tcl
View File

@ -19,35 +19,35 @@ adi_ip_files axi_spdif_rx [list \
adi_ip_properties axi_spdif_rx adi_ip_properties axi_spdif_rx
adi_ip_infer_streaming_interfaces axi_spdif_rx adi_ip_infer_streaming_interfaces axi_spdif_rx
adi_add_bus "DMA_ACK" "slave" \ adi_add_bus "dma_ack" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
[list {"DMA_REQ_DAVALID" "TVALID"} \ [list {"dma_req_davalid" "TVALID"} \
{"DMA_REQ_DAREADY" "TREADY"} \ {"dma_req_daready" "TREADY"} \
{"DMA_REQ_DATYPE" "TUSER"} ] {"dma_req_datype" "TUSER"} ]
adi_add_bus "DMA_REQ" "master" \ adi_add_bus "dma_req" "master" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
[list {"DMA_REQ_DRVALID" "TVALID"} \ [list {"dma_req_drvalid" "TVALID"} \
{"DMA_REQ_DRREADY" "TREADY"} \ {"dma_req_drready" "TREADY"} \
{"DMA_REQ_DRTYPE" "TUSER"} \ {"dma_req_drtype" "TUSER"} \
{"DMA_REQ_DRLAST" "TLAST"} ] {"dma_req_drlast" "TLAST"} ]
# Clock and reset are for both DMA_REQ and DMA_ACK # Clock and reset are for both dma_req and dma_ack
adi_add_bus_clock "DMA_REQ_ACLK" "DMA_REQ:DMA_ACK" "DMA_REQ_RSTN" adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
adi_set_bus_dependency "M_AXIS" "M_AXIS" \ adi_set_bus_dependency "m_axis" "m_axis" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)" "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
adi_set_bus_dependency "DMA_ACK" "DMA_REQ_DA" \ adi_set_bus_dependency "dma_ack" "dma_req_da" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_REQ" "DMA_REQ_DR" \ adi_set_bus_dependency "dma_req" "dma_req_dr" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_ACLK" \ adi_set_ports_dependency "dma_req_aclk" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_RSTN" \ adi_set_ports_dependency "dma_req_rstn" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]

168
library/axi_spdif_tx/axi_spdif_tx.vhd
View File

@ -60,46 +60,46 @@ entity axi_spdif_tx is
spdif_tx_o : out std_logic; spdif_tx_o : out std_logic;
--AXI Lite interface --AXI Lite interface
S_AXI_ACLK : in std_logic; s_axi_aclk : in std_logic;
S_AXI_ARESETN : in std_logic; s_axi_aresetn : in std_logic;
S_AXI_AWADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic; s_axi_awvalid : in std_logic;
S_AXI_WDATA : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic; s_axi_wvalid : in std_logic;
S_AXI_BREADY : in std_logic; s_axi_bready : in std_logic;
S_AXI_ARADDR : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic; s_axi_arvalid : in std_logic;
S_AXI_RREADY : in std_logic; s_axi_rready : in std_logic;
S_AXI_ARREADY : out std_logic; s_axi_arready : out std_logic;
S_AXI_RDATA : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic; s_axi_rvalid : out std_logic;
S_AXI_WREADY : out std_logic; s_axi_wready : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic; s_axi_bvalid : out std_logic;
S_AXI_AWREADY : out std_logic; s_axi_awready : out std_logic;
--AXI streaming interface --axi streaming interface
S_AXIS_ACLK : in std_logic; s_axis_aclk : in std_logic;
S_AXIS_ARESETN : in std_logic; s_axis_aresetn : in std_logic;
S_AXIS_TREADY : out std_logic; s_axis_tready : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0); s_axis_tdata : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic; s_axis_tlast : in std_logic;
S_AXIS_TVALID : in std_logic; s_axis_tvalid : in std_logic;
--PL330 DMA interface --PL330 DMA interface
DMA_REQ_ACLK : in std_logic; dma_req_aclk : in std_logic;
DMA_REQ_RSTN : in std_logic; dma_req_rstn : in std_logic;
DMA_REQ_DAVALID : in std_logic; dma_req_davalid : in std_logic;
DMA_REQ_DATYPE : in std_logic_vector(1 downto 0); dma_req_datype : in std_logic_vector(1 downto 0);
DMA_REQ_DAREADY : out std_logic; dma_req_daready : out std_logic;
DMA_REQ_DRVALID : out std_logic; dma_req_drvalid : out std_logic;
DMA_REQ_DRTYPE : out std_logic_vector(1 downto 0); dma_req_drtype : out std_logic_vector(1 downto 0);
DMA_REQ_DRLAST : out std_logic; dma_req_drlast : out std_logic;
DMA_REQ_DRREADY : in std_logic dma_req_drready : in std_logic
); );
end entity axi_spdif_tx; end entity axi_spdif_tx;
@ -149,15 +149,15 @@ begin
FIFO_DWIDTH => 32 FIFO_DWIDTH => 32
) )
port map ( port map (
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
fifo_reset => fifo_reset, fifo_reset => fifo_reset,
enable => enable, enable => enable,
S_AXIS_ACLK => S_AXIS_ACLK, s_axis_aclk => s_axis_aclk,
S_AXIS_TREADY => S_AXIS_TREADY, s_axis_tready => s_axis_tready,
S_AXIS_TDATA => S_AXIS_TDATA, s_axis_tdata => s_axis_tdata,
S_AXIS_TVALID => S_AXIS_TLAST, s_axis_tvalid => s_axis_tlast,
S_AXIS_TLAST => S_AXIS_TVALID, s_axis_tlast => s_axis_tvalid,
out_ack => fifo_data_ack, out_ack => fifo_data_ack,
out_data => fifo_data_out out_data => fifo_data_out
@ -165,7 +165,7 @@ begin
end generate; end generate;
no_streaming_dma_gen: if DMA_TYPE /= 0 generate no_streaming_dma_gen: if DMA_TYPE /= 0 generate
S_AXIS_TREADY <= '0'; s_axis_tready <= '0';
end generate; end generate;
pl330_dma_gen: if DMA_TYPE = 1 generate pl330_dma_gen: if DMA_TYPE = 1 generate
@ -178,8 +178,8 @@ begin
FIFO_DIRECTION => 0 FIFO_DIRECTION => 0
) )
port map ( port map (
clk => S_AXI_ACLK, clk => s_axi_aclk,
resetn => S_AXI_ARESETN, resetn => s_axi_aresetn,
fifo_reset => fifo_reset, fifo_reset => fifo_reset,
enable => enable, enable => enable,
@ -189,23 +189,23 @@ begin
out_ack => fifo_data_ack, out_ack => fifo_data_ack,
out_data => fifo_data_out, out_data => fifo_data_out,
dclk => DMA_REQ_ACLK, dclk => dma_req_aclk,
dresetn => DMA_REQ_RSTN, dresetn => dma_req_rstn,
davalid => DMA_REQ_DAVALID, davalid => dma_req_davalid,
daready => DMA_REQ_DAREADY, daready => dma_req_daready,
datype => DMA_REQ_DATYPE, datype => dma_req_datype,
drvalid => DMA_REQ_DRVALID, drvalid => dma_req_drvalid,
drready => DMA_REQ_DRREADY, drready => dma_req_drreadY,
drtype => DMA_REQ_DRTYPE, drtype => dma_req_drtype,
drlast => DMA_REQ_DRLAST drlast => dma_req_drlast
); );
end generate; end generate;
no_pl330_dma_gen: if DMA_TYPE /= 1 generate no_pl330_dma_gen: if DMA_TYPE /= 1 generate
DMA_REQ_DAREADY <= '0'; dma_req_daready <= '0';
DMA_REQ_DRVALID <= '0'; dma_req_drvalid <= '0';
DMA_REQ_DRTYPE <= (others => '0'); dma_req_drtype <= (others => '0');
DMA_REQ_DRLAST <= '0'; dma_req_drlast <= '0';
end generate; end generate;
sample_data_mux: process (fifo_data_out, channel) is sample_data_mux: process (fifo_data_out, channel) is
@ -237,9 +237,9 @@ begin
DATA_WIDTH => 16 DATA_WIDTH => 16
) )
port map ( port map (
up_clk => S_AXI_ACLK, up_clk => s_axi_aclk,
data_clk => spdif_data_clk, -- data clock data_clk => spdif_data_clk, -- data clock
resetn => S_AXI_ARESETN, -- resetn resetn => s_axi_aresetn, -- resetn
conf_mode => conf_mode, -- sample format conf_mode => conf_mode, -- sample format
conf_ratio => conf_ratio, -- clock divider conf_ratio => conf_ratio, -- clock divider
conf_txdata => conf_txdata, -- sample data enable conf_txdata => conf_txdata, -- sample data enable
@ -262,25 +262,25 @@ begin
C_NUM_REG => 4 C_NUM_REG => 4
) )
port map( port map(
S_AXI_ACLK => S_AXI_ACLK, s_axi_aclk => s_axi_aclk,
S_AXI_ARESETN => S_AXI_ARESETN, s_axi_aresetn => s_axi_aresetn,
S_AXI_AWADDR => S_AXI_AWADDR, s_axi_awaddr => s_axi_awaddr,
S_AXI_AWVALID => S_AXI_AWVALID, s_axi_awvalid => s_axi_awvalid,
S_AXI_WDATA => S_AXI_WDATA, s_axi_wdata => s_axi_wdata,
S_AXI_WSTRB => S_AXI_WSTRB, s_axi_wstrb => s_axi_wstrb,
S_AXI_WVALID => S_AXI_WVALID, s_axi_wvalid => s_axi_wvalid,
S_AXI_BREADY => S_AXI_BREADY, s_axi_bready => s_axi_bready,
S_AXI_ARADDR => S_AXI_ARADDR, s_axi_araddr => s_axi_araddr,
S_AXI_ARVALID => S_AXI_ARVALID, s_axi_arvalid => s_axi_arvalid,
S_AXI_RREADY => S_AXI_RREADY, s_axi_rready => s_axi_rready,
S_AXI_ARREADY => S_AXI_ARREADY, s_axi_arready => s_axi_arready,
S_AXI_RDATA => S_AXI_RDATA, s_axi_rdata => s_axi_rdata,
S_AXI_RRESP => S_AXI_RRESP, s_axi_rresp => s_axi_rresp,
S_AXI_RVALID => S_AXI_RVALID, s_axi_rvalid => s_axi_rvalid,
S_AXI_WREADY => S_AXI_WREADY, s_axi_wready => s_axi_wready,
S_AXI_BRESP => S_AXI_BRESP, s_axi_bresp => s_axi_bresp,
S_AXI_BVALID => S_AXI_BVALID, s_axi_bvalid => s_axi_bvalid,
S_AXI_AWREADY => S_AXI_AWREADY, s_axi_awready => s_axi_awready,
rd_addr => rd_addr, rd_addr => rd_addr,
rd_data => rd_data, rd_data => rd_data,
@ -293,10 +293,10 @@ begin
wr_stb => wr_stb wr_stb => wr_stb
); );
process (S_AXI_ACLK) process (s_axi_aclk)
begin begin
if rising_edge(S_AXI_ACLK) then if rising_edge(s_axi_aclk) then
if S_AXI_ARESETN = '0' then if s_axi_aresetn = '0' then
config_reg <= (others => '0'); config_reg <= (others => '0');
chstatus_reg <= (others => '0'); chstatus_reg <= (others => '0');
else else

36
library/axi_spdif_tx/axi_spdif_tx_ip.tcl
View File

@ -17,36 +17,36 @@ adi_ip_files axi_spdif_tx [list \
adi_ip_properties axi_spdif_tx adi_ip_properties axi_spdif_tx
adi_ip_infer_streaming_interfaces axi_spdif_tx adi_ip_infer_streaming_interfaces axi_spdif_tx
adi_add_bus "DMA_ACK" "slave" \ adi_add_bus "dma_ack" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
[list {"DMA_REQ_DAVALID" "TVALID"} \ [list {"dma_req_davalid" "TVALID"} \
{"DMA_REQ_DAREADY" "TREADY"} \ {"dma_req_daready" "TREADY"} \
{"DMA_REQ_DATYPE" "TUSER"} ] {"dma_req_datype" "TUSER"} ]
adi_add_bus "DMA_REQ" "master" \ adi_add_bus "dma_req" "master" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
[list {"DMA_REQ_DRVALID" "TVALID"} \ [list {"dma_req_drvalid" "TVALID"} \
{"DMA_REQ_DRREADY" "TREADY"} \ {"dma_req_drready" "TREADY"} \
{"DMA_REQ_DRTYPE" "TUSER"} \ {"dma_req_drtype" "TUSER"} \
{"DMA_REQ_DRLAST" "TLAST"} ] {"dma_req_drlast" "TLAST"} ]
# Clock and reset are for both DMA_REQ and DMA_ACK # Clock and reset are for both dma_req and dma_ack
adi_add_bus_clock "DMA_REQ_ACLK" "DMA_REQ:DMA_ACK" "DMA_REQ_RSTN" adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
adi_set_bus_dependency "S_AXIS" "S_AXIS" \ adi_set_bus_dependency "s_axis" "s_axis" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)"
adi_set_bus_dependency "DMA_ACK" "DMA_REQ_DA" \ adi_set_bus_dependency "dma_ack" "dma_req_da" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_bus_dependency "DMA_REQ" "DMA_REQ_DR" \ adi_set_bus_dependency "dma_req" "dma_req_dr" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_ACLK" \ adi_set_ports_dependency "dma_req_aclk" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
adi_set_ports_dependency "DMA_REQ_RSTN" \ adi_set_ports_dependency "dma_req_rstn" \
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core] ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axis_aresetn -clear [ipx::current_core]
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core] ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

84
library/common/axi_ctrlif.vhd
View File

@ -51,25 +51,25 @@ entity axi_ctrlif is
port port
( (
-- AXI bus interface -- AXI bus interface
S_AXI_ACLK : in std_logic; s_axi_aclk : in std_logic;
S_AXI_ARESETN : in std_logic; s_axi_aresetn : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic; s_axi_awvalid : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic; s_axi_wvalid : in std_logic;
S_AXI_BREADY : in std_logic; s_axi_bready : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic; s_axi_arvalid : in std_logic;
S_AXI_RREADY : in std_logic; s_axi_rready : in std_logic;
S_AXI_ARREADY : out std_logic; s_axi_arready : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic; s_axi_rvalid : out std_logic;
S_AXI_WREADY : out std_logic; s_axi_wready : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic; s_axi_bvalid : out std_logic;
S_AXI_AWREADY : out std_logic; s_axi_awready : out std_logic;
rd_addr : out integer range 0 to C_NUM_REG - 1; rd_addr : out integer range 0 to C_NUM_REG - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
@ -89,20 +89,20 @@ architecture Behavioral of axi_ctrlif is
signal rd_state : state_type; signal rd_state : state_type;
signal wr_state : state_type; signal wr_state : state_type;
begin begin
process (S_AXI_ACLK) process (s_axi_aclk)
begin begin
if rising_edge(S_AXI_ACLK) then if rising_edge(s_axi_aclk) then
if S_AXI_ARESETN = '0' then if s_axi_aresetn = '0' then
rd_state <= IDLE; rd_state <= IDLE;
else else
case rd_state is case rd_state is
when IDLE => when IDLE =>
if S_AXI_ARVALID = '1' then if s_axi_arvalid = '1' then
rd_state <= RESP; rd_state <= RESP;
rd_addr <= to_integer(unsigned(S_AXI_ARADDR((C_S_AXI_ADDR_WIDTH-1) downto 2))); rd_addr <= to_integer(unsigned(s_axi_araddr((C_S_AXI_ADDR_WIDTH-1) downto 2)));
end if; end if;
when RESP => when RESP =>
if rd_stb = '1' and S_AXI_RREADY = '1' then if rd_stb = '1' and s_axi_rready = '1' then
rd_state <= IDLE; rd_state <= IDLE;
end if; end if;
when others => null; when others => null;
@ -111,27 +111,27 @@ begin
end if; end if;
end process; end process;
S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; s_axi_arready <= '1' when rd_state = IDLE else '0';
S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; s_axi_rvalid <= '1' when rd_state = RESP and rd_stb = '1' else '0';
S_AXI_RRESP <= "00"; s_axi_rresp <= "00";
rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; rd_ack <= '1' when rd_state = RESP and s_axi_rready = '1' else '0';
S_AXI_RDATA <= rd_data; s_axi_rdata <= rd_data;
process (S_AXI_ACLK) process (s_axi_aclk)
begin begin
if rising_edge(S_AXI_ACLK) then if rising_edge(s_axi_aclk) then
if S_AXI_ARESETN = '0' then if s_axi_aresetn = '0' then
wr_state <= IDLE; wr_state <= IDLE;
else else
case wr_state is case wr_state is
when IDLE => when IDLE =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then if s_axi_awvalid = '1' and s_axi_wvalid = '1' and wr_ack = '1' then
wr_state <= ACK; wr_state <= ACK;
end if; end if;
when ACK => when ACK =>
wr_state <= RESP; wr_state <= RESP;
when RESP => when RESP =>
if S_AXI_BREADY = '1' then if s_axi_bready = '1' then
wr_state <= IDLE; wr_state <= IDLE;
end if; end if;
end case; end case;
@ -139,13 +139,13 @@ begin
end if; end if;
end process; end process;
wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; wr_stb <= '1' when s_axi_awvalid = '1' and s_axi_wvalid = '1' and wr_state = IDLE else '0';
wr_data <= S_AXI_WDATA; wr_data <= s_axi_wdata;
wr_addr <= to_integer(unsigned(S_AXI_AWADDR((C_S_AXI_ADDR_WIDTH-1) downto 2))); wr_addr <= to_integer(unsigned(s_axi_awaddr((C_S_AXI_ADDR_WIDTH-1) downto 2)));
S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; s_axi_awready <= '1' when wr_state = ACK else '0';
S_AXI_WREADY <= '1' when wr_state = ACK else '0'; s_axi_wready <= '1' when wr_state = ACK else '0';
S_AXI_BRESP <= "00"; s_axi_bresp <= "00";
S_AXI_BVALID <= '1' when wr_state = RESP else '0'; s_axi_bvalid <= '1' when wr_state = RESP else '0';
end; end;

26
library/common/axi_streaming_dma_rx_fifo.vhd
View File

@ -20,12 +20,12 @@ entity axi_streaming_dma_rx_fifo is
period_len : in integer range 0 to 65535; period_len : in integer range 0 to 65535;
-- Read port -- Read port
M_AXIS_ACLK : in std_logic; m_axis_aclk : in std_logic;
M_AXIS_TREADY : in std_logic; m_axis_tready : in std_logic;
M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0); m_axis_tdata : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
M_AXIS_TLAST : out std_logic; m_axis_tlast : out std_logic;
M_AXIS_TVALID : out std_logic; m_axis_tvalid : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0); m_axis_tkeep : out std_logic_vector(3 downto 0);
-- Write port -- Write port
in_stb : in std_logic; in_stb : in std_logic;
@ -41,7 +41,7 @@ architecture imp of axi_streaming_dma_rx_fifo is
signal last : std_logic; signal last : std_logic;
begin begin
M_AXIS_TVALID <= out_stb; m_axis_tvalid <= out_stb;
fifo: entity dma_fifo fifo: entity dma_fifo
generic map ( generic map (
@ -56,19 +56,19 @@ begin
in_ack => in_ack, in_ack => in_ack,
in_data => in_data, in_data => in_data,
out_stb => out_stb, out_stb => out_stb,
out_ack => M_AXIS_TREADY, out_ack => m_axis_tready,
out_data => M_AXIS_TDATA out_data => m_axis_tdata
); );
M_AXIS_TKEEP <= "1111"; m_axis_tkeep <= "1111";
M_AXIS_TLAST <= '1' when period_count = 0 else '0'; m_axis_tlast <= '1' when period_count = 0 else '0';
period_counter: process(M_AXIS_ACLK) is period_counter: process(m_axis_aclk) is
begin begin
if resetn = '0' then if resetn = '0' then
period_count <= period_len; period_count <= period_len;
else else
if out_stb = '1' and M_AXIS_TREADY = '1' then if out_stb = '1' and m_axis_tready = '1' then
if period_count = 0 then if period_count = 0 then
period_count <= period_len; period_count <= period_len;
else else

22
library/common/axi_streaming_dma_tx_fifo.vhd
View File

@ -18,11 +18,11 @@ entity axi_streaming_dma_tx_fifo is
enable : in Boolean; enable : in Boolean;
-- Write port -- Write port
S_AXIS_ACLK : in std_logic; s_axis_aclk : in std_logic;
S_AXIS_TREADY : out std_logic; s_axis_tready : out std_logic;
S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0); s_axis_tdata : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
S_AXIS_TLAST : in std_logic; s_axis_tlast : in std_logic;
S_AXIS_TVALID : in std_logic; s_axis_tvalid : in std_logic;
-- Read port -- Read port
out_stb : out std_logic; out_stb : out std_logic;
@ -45,22 +45,22 @@ begin
clk => clk, clk => clk,
resetn => resetn, resetn => resetn,
fifo_reset => fifo_reset, fifo_reset => fifo_reset,
in_stb => S_AXIS_TVALID, in_stb => s_axis_tvalid,
in_ack => in_ack, in_ack => in_ack,
in_data => S_AXIS_TDATA, in_data => s_axis_tdata,
out_stb => out_stb, out_stb => out_stb,
out_ack => out_ack, out_ack => out_ack,
out_data => out_data out_data => out_data
); );
drain_process: process (S_AXIS_ACLK) is drain_process: process (s_axis_aclk) is
variable enable_d1 : Boolean; variable enable_d1 : Boolean;
begin begin
if rising_edge(S_AXIS_ACLK) then if rising_edge(s_axis_aclk) then
if resetn = '0' then if resetn = '0' then
drain_dma <= False; drain_dma <= False;
else else
if S_AXIS_TLAST = '1' then if s_axis_tlast = '1' then
drain_dma <= False; drain_dma <= False;
elsif enable_d1 and enable then elsif enable_d1 and enable then
drain_dma <= True; drain_dma <= True;
@ -70,5 +70,5 @@ begin
end if; end if;
end process; end process;
S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0'; s_axis_tready <= '1' when in_ack = '1' or drain_dma else '0';
end; end;

8
library/util_axis_fifo/util_axis_fifo_ip.tcl
View File

@ -14,7 +14,7 @@ adi_ip_files util_axis_fifo [list \
adi_ip_properties_lite util_axis_fifo adi_ip_properties_lite util_axis_fifo
adi_add_bus "S_AXIS" "slave" \ adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ {
@ -23,7 +23,7 @@ adi_add_bus "S_AXIS" "slave" \
{"s_axis_data" "TDATA"} \ {"s_axis_data" "TDATA"} \
} }
adi_add_bus "M_AXIS" "master" \ adi_add_bus "m_axis" "master" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ {
@ -32,7 +32,7 @@ adi_add_bus "M_AXIS" "master" \
{"m_axis_data" "TDATA"} \ {"m_axis_data" "TDATA"} \
} }
adi_add_bus_clock "m_axis_aclk" "M_AXIS" "m_axis_aresetn" adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn"
adi_add_bus_clock "s_axis_aclk" "S_AXIS" "m_axis_aresetn" adi_add_bus_clock "s_axis_aclk" "s_axis" "m_axis_aresetn"
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]