library/common: add altera signaltap

main
Rejeesh Kutty 2015-06-19 14:30:21 -04:00
parent 51e6a74a3d
commit ac6e28c461
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module sld_signaltap (
acq_clk,
acq_trigger_in,
acq_data_in);
// parameters
parameter sld_sample_depth = 1024;
parameter sld_data_bits = 32;
parameter sld_trigger_bits = 1;
parameter sld_trigger_level = 1;
parameter sld_trigger_in_enabled = 0;
parameter sld_enable_advanced_trigger = 0;
// data interface
input acq_clk;
input [(sld_trigger_bits-1):0] acq_trigger_in;
input [(sld_data_bits-1):0] acq_data_in;
endmodule
// ***************************************************************************
// ***************************************************************************