Merge branch 'hdl_2016_r1' into master
Istvan Csomortani
commit
ace09eb26e
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@ -55,6 +55,7 @@ clean:
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make -C util_axis_resize clean
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make -C util_bsplit clean
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make -C util_ccat clean
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make -C util_clkdiv clean
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make -C util_cpack clean
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make -C util_dac_unpack clean
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make -C util_dacfifo clean
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@ -121,6 +122,7 @@ lib:
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-make -C util_axis_resize
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-make -C util_bsplit
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-make -C util_ccat
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-make -C util_clkdiv
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-make -C util_cpack
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-make -C util_dac_unpack
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-make -C util_dacfifo
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@ -65,6 +65,7 @@ module axi_ad9152 (
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awprot,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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@ -75,6 +76,7 @@ module axi_ad9152 (
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arprot,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rdata,
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@ -110,6 +112,7 @@ module axi_ad9152 (
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [ 31:0] s_axi_awaddr;
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input [ 2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_wvalid;
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input [ 31:0] s_axi_wdata;
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@ -120,6 +123,7 @@ module axi_ad9152 (
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input s_axi_bready;
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input s_axi_arvalid;
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input [ 31:0] s_axi_araddr;
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input [ 2:0] s_axi_arprot;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 31:0] s_axi_rdata;
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@ -0,0 +1,97 @@
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package require -exact qsys 13.0
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME axi_ad9152
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set_module_property DESCRIPTION "AXI AD9152 Interface"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_ad9152
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL axi_ad9152
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add_fileset_file MULT_MACRO.v VERILOG PATH $ad_hdl_dir/library/common/altera/MULT_MACRO.v
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add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/common/ad_mul.v
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add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
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add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
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add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
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add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
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add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
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add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
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add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
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add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
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add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
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add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
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add_fileset_file axi_ad9152_channel.v VERILOG PATH axi_ad9152_channel.v
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add_fileset_file axi_ad9152_core.v VERILOG PATH axi_ad9152_core.v
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add_fileset_file axi_ad9152_if.v VERILOG PATH axi_ad9152_if.v
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add_fileset_file axi_ad9152.v VERILOG PATH axi_ad9152.v TOP_LEVEL_FILE
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add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID TYPE INTEGER
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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# axi4 slave
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add_interface s_axi_clock clock end
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add_interface_port s_axi_clock s_axi_aclk clk Input 1
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add_interface s_axi_reset reset end
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set_interface_property s_axi_reset associatedClock s_axi_clock
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add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
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add_interface s_axi axi4lite end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input 16
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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add_interface_port s_axi s_axi_wdata wdata Input 32
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add_interface_port s_axi s_axi_wstrb wstrb Input 4
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add_interface_port s_axi s_axi_wready wready Output 1
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add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input 16
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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# transceiver interface
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ad_alt_intf clock tx_clk input 1
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ad_alt_intf signal tx_data output 128 data
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# dma interface
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ad_alt_intf clock dac_clk output 1
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add_interface fifo_ch_0_out conduit end
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add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1
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add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1
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add_interface_port fifo_ch_0_out dac_ddata_0 data Input 64
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add_interface fifo_ch_1_out conduit end
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add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1
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add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1
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add_interface_port fifo_ch_1_out dac_ddata_1 data Input 64
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ad_alt_intf signal dac_dovf input 1 ovf
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ad_alt_intf signal dac_dunf input 1 unf
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@ -11,10 +11,12 @@ set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
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set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
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<: if {$async_req_src || $async_src_dest || $async_dest_req} { :>
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
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[get_cells -quiet -hier *cdc_sync_stage2_reg*]
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<: } :>
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<: if {$async_req_src} { :>
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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@ -68,6 +68,8 @@ parameter ID_WIDTH = 3;
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parameter DATA_WIDTH = 64;
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parameter DISABLE_WAIT_FOR_ID = 1;
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parameter BEATS_PER_BURST_WIDTH = 4;
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parameter LAST = 0; /* 0 = last asserted at the end of each burst, 1 = last only asserted at the end of the transfer */
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localparam MAX_BEATS_PER_BURST = 2**(BEATS_PER_BURST_WIDTH);
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`include "inc_id.h"
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@ -94,7 +96,7 @@ assign last = eot ? last_eot : last_non_eot;
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assign s_axi_ready = m_axi_ready & pending_burst & active;
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assign m_axi_valid = s_axi_valid & pending_burst & active;
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assign m_axi_data = s_axi_data;
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assign m_axi_last = last;
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assign m_axi_last = LAST ? (last_eot & eot) : last;
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// If we want to support zero delay between transfers we have to assert
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// req_ready on the same cycle on which the last load happens.
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@ -100,7 +100,8 @@ dmac_data_mover # (
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.ID_WIDTH(ID_WIDTH),
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.DATA_WIDTH(S_AXIS_DATA_WIDTH),
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.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
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.DISABLE_WAIT_FOR_ID(0)
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.DISABLE_WAIT_FOR_ID(0),
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.LAST(1)
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) i_data_mover (
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.clk(s_axis_aclk),
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.resetn(s_axis_aresetn),
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@ -202,6 +202,8 @@ module axi_hdmi_tx (
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wire [15:0] hdmi_vs_width_s;
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wire [15:0] hdmi_ve_max_s;
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wire [15:0] hdmi_ve_min_s;
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wire [31:0] hdmi_clip_max_s;
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wire [31:0] hdmi_clip_min_s;
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wire hdmi_fs_toggle_s;
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wire [ 8:0] hdmi_raddr_g_s;
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wire hdmi_tpm_oos_s;
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@ -271,6 +273,8 @@ module axi_hdmi_tx (
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.hdmi_vs_width (hdmi_vs_width_s),
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.hdmi_ve_max (hdmi_ve_max_s),
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.hdmi_ve_min (hdmi_ve_min_s),
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.hdmi_clip_max (hdmi_clip_max_s),
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.hdmi_clip_min (hdmi_clip_min_s),
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.hdmi_status (hdmi_status_s),
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.hdmi_tpm_oos (hdmi_tpm_oos_s),
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.hdmi_clk_ratio (32'd1),
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@ -356,7 +360,9 @@ module axi_hdmi_tx (
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.hdmi_vf_width (hdmi_vf_width_s),
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.hdmi_vs_width (hdmi_vs_width_s),
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.hdmi_ve_max (hdmi_ve_max_s),
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.hdmi_ve_min (hdmi_ve_min_s));
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.hdmi_ve_min (hdmi_ve_min_s),
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.hdmi_clip_max (hdmi_clip_max_s),
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.hdmi_clip_min (hdmi_clip_min_s));
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// hdmi output clock
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@ -97,7 +97,9 @@ module axi_hdmi_tx_core (
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hdmi_vf_width,
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hdmi_vs_width,
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hdmi_ve_max,
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hdmi_ve_min);
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hdmi_ve_min,
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hdmi_clip_max,
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hdmi_clip_min);
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// parameters
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@ -164,6 +166,8 @@ module axi_hdmi_tx_core (
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input [15:0] hdmi_vs_width;
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input [15:0] hdmi_ve_max;
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input [15:0] hdmi_ve_min;
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input [23:0] hdmi_clip_max;
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input [23:0] hdmi_clip_min;
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// internal registers
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@ -205,12 +209,24 @@ module axi_hdmi_tx_core (
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reg hdmi_vsync_data_e = 'd0;
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reg hdmi_data_e = 'd0;
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reg [23:0] hdmi_data = 'd0;
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reg hdmi_24_csc_hsync = 'd0;
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reg hdmi_24_csc_vsync = 'd0;
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reg hdmi_24_csc_hsync_data_e = 'd0;
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reg hdmi_24_csc_vsync_data_e = 'd0;
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reg hdmi_24_csc_data_e = 'd0;
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reg [23:0] hdmi_24_csc_data = 'd0;
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reg hdmi_24_hsync = 'd0;
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reg hdmi_24_vsync = 'd0;
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reg hdmi_24_hsync_data_e = 'd0;
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reg hdmi_24_vsync_data_e = 'd0;
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reg hdmi_24_data_e = 'd0;
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reg [23:0] hdmi_24_data = 'd0;
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reg hdmi_24_hsync_ss = 'd0;
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reg hdmi_24_vsync_ss = 'd0;
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reg hdmi_24_hsync_data_e_ss = 'd0;
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reg hdmi_24_vsync_data_e_ss = 'd0;
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reg hdmi_24_data_e_ss = 'd0;
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reg [23:0] hdmi_24_data_ss = 'd0;
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reg hdmi_16_hsync = 'd0;
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reg hdmi_16_vsync = 'd0;
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reg hdmi_16_hsync_data_e = 'd0;
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@ -220,6 +236,12 @@ module axi_hdmi_tx_core (
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reg hdmi_es_hs_de = 'd0;
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reg hdmi_es_vs_de = 'd0;
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reg [15:0] hdmi_es_data = 'd0;
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reg [23:0] hdmi_clip_data = 'd0;
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reg hdmi_clip_hs_de_d = 'd0;
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reg hdmi_clip_vs_de_d = 'd0;
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reg hdmi_clip_hs_d = 'd0;
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reg hdmi_clip_vs_d = 'd0;
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reg hdmi_clip_de_d = 'd0;
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// internal wires
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@ -245,6 +267,10 @@ module axi_hdmi_tx_core (
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wire hdmi_ss_vsync_data_e_s;
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wire hdmi_ss_data_e_s;
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wire [15:0] hdmi_ss_data_s;
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wire hdmi_clip_hs_de_s;
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wire hdmi_clip_vs_de_s;
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wire hdmi_clip_de_s;
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wire [23:0] hdmi_clip_data_s;
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wire hdmi_es_hs_de_s;
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wire hdmi_es_vs_de_s;
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wire hdmi_es_de_s;
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@ -453,6 +479,68 @@ module axi_hdmi_tx_core (
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endcase
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end
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// Color space conversion bypass (RGB/YCbCr)
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always @(posedge hdmi_clk) begin
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if (hdmi_csc_bypass == 1'b1) begin
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hdmi_24_csc_hsync <= hdmi_hsync;
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hdmi_24_csc_vsync <= hdmi_vsync;
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hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e;
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hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e;
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hdmi_24_csc_data_e <= hdmi_data_e;
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hdmi_24_csc_data <= hdmi_data;
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end else begin
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hdmi_24_csc_hsync <= hdmi_csc_hsync_s;
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hdmi_24_csc_vsync <= hdmi_csc_vsync_s;
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hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s;
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hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s;
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hdmi_24_csc_data_e <= hdmi_csc_data_e_s;
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hdmi_24_csc_data <= hdmi_csc_data_s;
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end
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end
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// hdmi clipping
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||||
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assign hdmi_clip_data_s = hdmi_24_csc_data;
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always @(posedge hdmi_clk) begin
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hdmi_clip_hs_d <= hdmi_24_csc_hsync;
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hdmi_clip_vs_d <= hdmi_24_csc_vsync;
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hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e;
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hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e;
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hdmi_clip_de_d <= hdmi_24_csc_data_e;
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// Cr (red-diff) / red
|
||||
|
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if (hdmi_clip_data_s[23:16] > hdmi_clip_max[23:16]) begin
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hdmi_clip_data[23:16] <= hdmi_clip_max[23:16];
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end else if (hdmi_clip_data_s[23:16] < hdmi_clip_min[23:16]) begin
|
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hdmi_clip_data[23:16] <= hdmi_clip_min[23:16];
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end else begin
|
||||
hdmi_clip_data[23:16] <= hdmi_clip_data_s[23:16];
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end
|
||||
|
||||
// Y (luma) / green
|
||||
|
||||
if (hdmi_clip_data_s[15:8] > hdmi_clip_max[15:8]) begin
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hdmi_clip_data[15:8] <= hdmi_clip_max[15:8];
|
||||
end else if (hdmi_clip_data_s[15:8] < hdmi_clip_min[15:8]) begin
|
||||
hdmi_clip_data[15:8] <= hdmi_clip_min[15:8];
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end else begin
|
||||
hdmi_clip_data[15:8] <= hdmi_clip_data_s[15:8];
|
||||
end
|
||||
|
||||
// Cb (blue-diff) / blue
|
||||
|
||||
if (hdmi_clip_data_s[7:0] > hdmi_clip_max[7:0]) begin
|
||||
hdmi_clip_data[7:0] <= hdmi_clip_max[7:0];
|
||||
end else if (hdmi_clip_data_s[7:0] < hdmi_clip_min[7:0]) begin
|
||||
hdmi_clip_data[7:0] <= hdmi_clip_min[7:0];
|
||||
end else begin
|
||||
hdmi_clip_data[7:0] <= hdmi_clip_data_s[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
// hdmi csc 16, 24 and 36 outputs
|
||||
|
||||
assign hdmi_36_hsync = hdmi_24_hsync;
|
||||
|
|
@ -463,21 +551,14 @@ module axi_hdmi_tx_core (
|
|||
assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]};
|
||||
|
||||
always @(posedge hdmi_clk) begin
|
||||
if (hdmi_csc_bypass == 1'b1) begin
|
||||
hdmi_24_hsync <= hdmi_hsync;
|
||||
hdmi_24_vsync <= hdmi_vsync;
|
||||
hdmi_24_hsync_data_e <= hdmi_hsync_data_e;
|
||||
hdmi_24_vsync_data_e <= hdmi_vsync_data_e;
|
||||
hdmi_24_data_e <= hdmi_data_e;
|
||||
hdmi_24_data <= hdmi_data;
|
||||
end else begin
|
||||
hdmi_24_hsync <= hdmi_csc_hsync_s;
|
||||
hdmi_24_vsync <= hdmi_csc_vsync_s;
|
||||
hdmi_24_hsync_data_e <= hdmi_csc_hsync_data_e_s;
|
||||
hdmi_24_vsync_data_e <= hdmi_csc_vsync_data_e_s;
|
||||
hdmi_24_data_e <= hdmi_csc_data_e_s;
|
||||
hdmi_24_data <= hdmi_csc_data_s;
|
||||
end
|
||||
|
||||
hdmi_24_hsync <= hdmi_clip_hs_d;
|
||||
hdmi_24_vsync <= hdmi_clip_vs_d;
|
||||
hdmi_24_hsync_data_e <= hdmi_clip_hs_de_d;
|
||||
hdmi_24_vsync_data_e <= hdmi_clip_vs_de_d;
|
||||
hdmi_24_data_e <= hdmi_clip_de_d;
|
||||
hdmi_24_data <= hdmi_clip_data;
|
||||
|
||||
if (hdmi_ss_bypass == 1'b1) begin
|
||||
hdmi_16_hsync <= hdmi_24_hsync;
|
||||
hdmi_16_vsync <= hdmi_24_vsync;
|
||||
|
|
@ -495,7 +576,7 @@ module axi_hdmi_tx_core (
|
|||
end
|
||||
end
|
||||
|
||||
// hdmi embedded sync clipping
|
||||
// hdmi embedded sync
|
||||
|
||||
assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e;
|
||||
assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e;
|
||||
|
|
@ -507,31 +588,11 @@ module axi_hdmi_tx_core (
|
|||
hdmi_es_vs_de <= hdmi_es_vs_de_s;
|
||||
if (hdmi_es_de_s == 1'b0) begin
|
||||
hdmi_es_data[15:8] <= 8'h80;
|
||||
end else if ((hdmi_full_range == 1'b0) &&
|
||||
(hdmi_es_data_s[15:8] > 8'heb)) begin
|
||||
hdmi_es_data[15:8] <= 8'heb;
|
||||
end else if ((hdmi_full_range == 1'b0) &&
|
||||
(hdmi_es_data_s[15:8] < 8'h10)) begin
|
||||
hdmi_es_data[15:8] <= 8'h10;
|
||||
end else if (hdmi_es_data_s[15:8] > 8'hfe) begin
|
||||
hdmi_es_data[15:8] <= 8'hfe;
|
||||
end else if (hdmi_es_data_s[15:8] < 8'h01) begin
|
||||
hdmi_es_data[15:8] <= 8'h01;
|
||||
end else begin
|
||||
hdmi_es_data[15:8] <= hdmi_es_data_s[15:8];
|
||||
end
|
||||
if (hdmi_es_de_s == 1'b0) begin
|
||||
hdmi_es_data[7:0] <= 8'h80;
|
||||
end else if ((hdmi_full_range == 1'b0) &&
|
||||
(hdmi_es_data_s[7:0] > 8'heb)) begin
|
||||
hdmi_es_data[7:0] <= 8'heb;
|
||||
end else if ((hdmi_full_range == 1'b0) &&
|
||||
(hdmi_es_data_s[7:0] < 8'h10)) begin
|
||||
hdmi_es_data[7:0] <= 8'h10;
|
||||
end else if (hdmi_es_data_s[7:0] > 8'hfe) begin
|
||||
hdmi_es_data[7:0] <= 8'hfe;
|
||||
end else if (hdmi_es_data_s[7:0] < 8'h01) begin
|
||||
hdmi_es_data[7:0] <= 8'h01;
|
||||
end else begin
|
||||
hdmi_es_data[7:0] <= hdmi_es_data_s[7:0];
|
||||
end
|
||||
|
|
@ -569,13 +630,13 @@ module axi_hdmi_tx_core (
|
|||
|
||||
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
|
||||
.clk (hdmi_clk),
|
||||
.s444_de (hdmi_24_data_e),
|
||||
.s444_sync ({hdmi_24_hsync,
|
||||
hdmi_24_vsync,
|
||||
hdmi_24_hsync_data_e,
|
||||
hdmi_24_vsync_data_e,
|
||||
hdmi_24_data_e}),
|
||||
.s444_data (hdmi_24_data),
|
||||
.s444_de (hdmi_clip_de_d),
|
||||
.s444_sync ({hdmi_clip_hs_d,
|
||||
hdmi_clip_vs_d,
|
||||
hdmi_clip_hs_de_d,
|
||||
hdmi_clip_vs_de_d,
|
||||
hdmi_clip_de_d}),
|
||||
.s444_data (hdmi_clip_data),
|
||||
.s422_sync ({hdmi_ss_hsync_s,
|
||||
hdmi_ss_vsync_s,
|
||||
hdmi_ss_hsync_data_e_s,
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ adi_ip_files axi_i2s_adi [list \
|
|||
"axi_i2s_adi_constr.xdc" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite axi_i2s_adi
|
||||
adi_ip_properties axi_i2s_adi
|
||||
adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late
|
||||
|
||||
adi_add_bus "DMA_ACK_RX" "slave" \
|
||||
|
|
@ -30,6 +30,7 @@ adi_add_bus "DMA_ACK_RX" "slave" \
|
|||
{"DMA_REQ_RX_DAREADY" "TREADY"} \
|
||||
{"DMA_REQ_RX_DATYPE" "TUSER"} \
|
||||
}
|
||||
|
||||
adi_add_bus "DMA_REQ_RX" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
|
|
@ -95,8 +96,9 @@ adi_set_ports_dependency "DMA_REQ_RX_ACLK" \
|
|||
adi_set_ports_dependency "DMA_REQ_RX_RSTN" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
|
||||
set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \
|
||||
-of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]]
|
||||
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core]
|
||||
ipx::associate_bus_interfaces -busif I2S -clock i2s_signal_clock [ipx::current_core]
|
||||
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
|
|
|||
|
|
@ -668,8 +668,8 @@ module axi_jesd_gt #(
|
|||
|
||||
// axi - clock & reset
|
||||
|
||||
input axi_aclk,
|
||||
input axi_aresetn,
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
|
||||
// axi interface
|
||||
|
||||
|
|
@ -831,8 +831,8 @@ module axi_jesd_gt #(
|
|||
|
||||
// signal name changes
|
||||
|
||||
assign up_rstn = axi_aresetn;
|
||||
assign up_clk = axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
assign up_clk = s_axi_aclk;
|
||||
|
||||
// pll
|
||||
|
||||
|
|
|
|||
|
|
@ -24,16 +24,7 @@ adi_ip_properties axi_jesd_gt
|
|||
adi_ip_constraints axi_jesd_gt [list \
|
||||
"axi_jesd_gt_constr.xdc" ]
|
||||
|
||||
ipx::remove_bus_interface qpll0_rst [ipx::current_core]
|
||||
ipx::remove_bus_interface qpll1_rst [ipx::current_core]
|
||||
|
||||
set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
-of_objects [ipx::get_bus_interfaces axi_aclk \
|
||||
-of_objects [ipx::current_core]]]
|
||||
|
||||
set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \
|
||||
-of_objects [ipx::get_bus_interfaces axi_aclk \
|
||||
-of_objects [ipx::current_core]]]
|
||||
ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core]
|
||||
|
||||
adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \
|
||||
"qpll_rst qpll0_rst "\
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ adi_ip_files axi_spdif_rx [list \
|
|||
"axi_spdif_rx.vhd" \
|
||||
"axi_spdif_rx_constr.xdc"]
|
||||
|
||||
adi_ip_properties_lite axi_spdif_rx
|
||||
adi_ip_properties axi_spdif_rx
|
||||
adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc
|
||||
|
||||
adi_add_bus "DMA_ACK" "slave" \
|
||||
|
|
@ -49,4 +49,5 @@ adi_set_ports_dependency "DMA_REQ_RSTN" \
|
|||
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core]
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ adi_ip_files axi_spdif_tx [list \
|
|||
"axi_spdif_tx.vhd" \
|
||||
"axi_spdif_tx_constr.xdc" ]
|
||||
|
||||
adi_ip_properties_lite axi_spdif_tx
|
||||
adi_ip_properties axi_spdif_tx
|
||||
adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc
|
||||
|
||||
adi_add_bus "DMA_ACK" "slave" \
|
||||
|
|
@ -46,8 +46,7 @@ adi_set_ports_dependency "DMA_REQ_ACLK" \
|
|||
adi_set_ports_dependency "DMA_REQ_RSTN" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)"
|
||||
|
||||
set_property value S_AXI_ARESETN [ipx::get_bus_parameters ASSOCIATED_RESET \
|
||||
-of_objects [ipx::get_bus_interfaces S_AXI_ACLK -of_objects [ipx::current_core]]]
|
||||
|
||||
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXIS_ARESETN -clear [ipx::current_core]
|
||||
ipx::associate_bus_interfaces -clock s_axi_aclk -reset S_AXI_ARESETN [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
|
|
@ -21,21 +21,19 @@
|
|||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
@ -123,26 +121,30 @@ module up_axi (
|
|||
reg up_axi_awready = 'd0;
|
||||
reg up_axi_wready = 'd0;
|
||||
reg up_axi_bvalid = 'd0;
|
||||
reg up_wack_d = 'd0;
|
||||
reg up_wsel = 'd0;
|
||||
reg up_wreq = 'd0;
|
||||
reg [AW:0] up_waddr = 'd0;
|
||||
reg [31:0] up_wdata = 'd0;
|
||||
reg [ 2:0] up_wcount = 'd0;
|
||||
reg up_wack_int = 'd0;
|
||||
reg [ 4:0] up_wcount = 'd0;
|
||||
reg up_axi_arready = 'd0;
|
||||
reg up_axi_rvalid = 'd0;
|
||||
reg [31:0] up_axi_rdata = 'd0;
|
||||
reg up_rack_d = 'd0;
|
||||
reg [31:0] up_rdata_d = 'd0;
|
||||
reg up_rsel = 'd0;
|
||||
reg up_rreq = 'd0;
|
||||
reg [AW:0] up_raddr = 'd0;
|
||||
reg [ 3:0] up_rcount = 'd0;
|
||||
reg up_rack_int = 'd0;
|
||||
reg [31:0] up_rdata_int = 'd0;
|
||||
reg up_rack_int_d = 'd0;
|
||||
reg [31:0] up_rdata_int_d = 'd0;
|
||||
reg [ 4:0] up_rcount = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wack_s;
|
||||
wire up_rack_s;
|
||||
wire [31:0] up_rdata_s;
|
||||
|
||||
// write channel interface
|
||||
|
||||
|
||||
assign up_axi_bresp = 2'd0;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
|
|
@ -153,30 +155,34 @@ module up_axi (
|
|||
end else begin
|
||||
if (up_axi_awready == 1'b1) begin
|
||||
up_axi_awready <= 1'b0;
|
||||
end else if (up_wack_int == 1'b1) begin
|
||||
end else if (up_wack_s == 1'b1) begin
|
||||
up_axi_awready <= 1'b1;
|
||||
end
|
||||
if (up_axi_wready == 1'b1) begin
|
||||
up_axi_wready <= 1'b0;
|
||||
end else if (up_wack_int == 1'b1) begin
|
||||
end else if (up_wack_s == 1'b1) begin
|
||||
up_axi_wready <= 1'b1;
|
||||
end
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
|
||||
up_axi_bvalid <= 1'b0;
|
||||
end else if (up_wack_int == 1'b1) begin
|
||||
end else if (up_wack_d == 1'b1) begin
|
||||
up_axi_bvalid <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_wack_d <= 'd0;
|
||||
up_wsel <= 'd0;
|
||||
up_wreq <= 'd0;
|
||||
up_waddr <= 'd0;
|
||||
up_wdata <= 'd0;
|
||||
up_wcount <= 'd0;
|
||||
end else begin
|
||||
up_wack_d <= up_wack_s;
|
||||
if (up_wsel == 1'b1) begin
|
||||
if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
|
||||
up_wsel <= 1'b0;
|
||||
|
|
@ -184,25 +190,18 @@ module up_axi (
|
|||
up_wreq <= 1'b0;
|
||||
up_waddr <= up_waddr;
|
||||
up_wdata <= up_wdata;
|
||||
up_wcount <= up_wcount + 1'b1;
|
||||
end else begin
|
||||
up_wsel <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_wreq <= up_axi_awvalid & up_axi_wvalid;
|
||||
up_waddr <= up_axi_awaddr[AW+2:2];
|
||||
up_wdata <= up_axi_wdata;
|
||||
up_wcount <= 3'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack_int <= 'd0;
|
||||
end else begin
|
||||
if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin
|
||||
up_wack_int <= 1'b1;
|
||||
end else if (up_wsel == 1'b1) begin
|
||||
up_wack_int <= up_wack;
|
||||
if (up_wack_s == 1'b1) begin
|
||||
up_wcount <= 5'h00;
|
||||
end else if (up_wcount[4] == 1'b1) begin
|
||||
up_wcount <= up_wcount + 1'b1;
|
||||
end else if (up_wreq == 1'b1) begin
|
||||
up_wcount <= 5'h10;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -219,26 +218,33 @@ module up_axi (
|
|||
end else begin
|
||||
if (up_axi_arready == 1'b1) begin
|
||||
up_axi_arready <= 1'b0;
|
||||
end else if (up_rack_int == 1'b1) begin
|
||||
end else if (up_rack_s == 1'b1) begin
|
||||
up_axi_arready <= 1'b1;
|
||||
end
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
|
||||
up_axi_rvalid <= 1'b0;
|
||||
up_axi_rdata <= 32'd0;
|
||||
end else if (up_rack_int_d == 1'b1) begin
|
||||
end else if (up_rack_d == 1'b1) begin
|
||||
up_axi_rvalid <= 1'b1;
|
||||
up_axi_rdata <= up_rdata_int_d;
|
||||
up_axi_rdata <= up_rdata_d;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
|
||||
assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_rack_d <= 'd0;
|
||||
up_rdata_d <= 'd0;
|
||||
up_rsel <= 'd0;
|
||||
up_rreq <= 'd0;
|
||||
up_raddr <= 'd0;
|
||||
up_rcount <= 'd0;
|
||||
end else begin
|
||||
up_rack_d <= up_rack_s;
|
||||
up_rdata_d <= up_rdata_s;
|
||||
if (up_rsel == 1'b1) begin
|
||||
if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
|
||||
up_rsel <= 1'b0;
|
||||
|
|
@ -250,35 +256,16 @@ module up_axi (
|
|||
up_rreq <= up_axi_arvalid;
|
||||
up_raddr <= up_axi_araddr[AW+2:2];
|
||||
end
|
||||
if (up_rack_int == 1'b1) begin
|
||||
up_rcount <= 4'd0;
|
||||
end else if (up_rcount[3] == 1'b1) begin
|
||||
if (up_rack_s == 1'b1) begin
|
||||
up_rcount <= 5'h00;
|
||||
end else if (up_rcount[4] == 1'b1) begin
|
||||
up_rcount <= up_rcount + 1'b1;
|
||||
end else if (up_rreq == 1'b1) begin
|
||||
up_rcount <= 4'd8;
|
||||
up_rcount <= 5'h10;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rack_int <= 'd0;
|
||||
up_rdata_int <= 'd0;
|
||||
up_rack_int_d <= 'd0;
|
||||
up_rdata_int_d <= 'd0;
|
||||
end else begin
|
||||
if ((up_rcount == 4'hf) && (up_rack == 1'b0)) begin
|
||||
up_rack_int <= 1'b1;
|
||||
up_rdata_int <= {2{16'hdead}};
|
||||
end else begin
|
||||
up_rack_int <= up_rack;
|
||||
up_rdata_int <= up_rdata;
|
||||
end
|
||||
up_rack_int_d <= up_rack_int;
|
||||
up_rdata_int_d <= up_rdata_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
|
|
|
|||
|
|
@ -58,6 +58,8 @@ module up_hdmi_tx (
|
|||
hdmi_vs_width,
|
||||
hdmi_ve_max,
|
||||
hdmi_ve_min,
|
||||
hdmi_clip_max,
|
||||
hdmi_clip_min,
|
||||
hdmi_status,
|
||||
hdmi_tpm_oos,
|
||||
hdmi_clk_ratio,
|
||||
|
|
@ -107,6 +109,8 @@ module up_hdmi_tx (
|
|||
output [15:0] hdmi_vs_width;
|
||||
output [15:0] hdmi_ve_max;
|
||||
output [15:0] hdmi_ve_min;
|
||||
output [23:0] hdmi_clip_max;
|
||||
output [23:0] hdmi_clip_min;
|
||||
input hdmi_status;
|
||||
input hdmi_tpm_oos;
|
||||
input [31:0] hdmi_clk_ratio;
|
||||
|
|
@ -157,6 +161,8 @@ module up_hdmi_tx (
|
|||
reg [15:0] up_vs_width = 'd0;
|
||||
reg [15:0] up_ve_max = 'd0;
|
||||
reg [15:0] up_ve_min = 'd0;
|
||||
reg [23:0] up_clip_max = 'd0;
|
||||
reg [23:0] up_clip_min = 'd0;
|
||||
reg up_rack = 'd0;
|
||||
reg [31:0] up_rdata = 'd0;
|
||||
|
||||
|
|
@ -203,6 +209,8 @@ module up_hdmi_tx (
|
|||
up_vs_width <= 'd0;
|
||||
up_ve_max <= 'd0;
|
||||
up_ve_min <= 'd0;
|
||||
up_clip_max <= 24'hf0ebf0;
|
||||
up_clip_min <= 24'h101010;
|
||||
end else begin
|
||||
up_core_preset <= ~up_resetn;
|
||||
up_wack <= up_wreq_s;
|
||||
|
|
@ -243,6 +251,21 @@ module up_hdmi_tx (
|
|||
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
|
||||
up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
|
||||
if ((up_wdata[1]== 1'b1) || (up_wdata[0] == 1'b1)) begin
|
||||
up_clip_max <= 24'hfefefe;
|
||||
up_clip_min <= 24'h010101;
|
||||
end else begin
|
||||
up_clip_max <= 24'hf0ebf0;
|
||||
up_clip_min <= 24'h101010;
|
||||
end
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin
|
||||
up_clip_max <= up_wdata[23:0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin
|
||||
up_clip_min <= up_wdata[23:0];
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
|
||||
up_hl_active <= up_wdata[31:16];
|
||||
up_hl_width <= up_wdata[15:0];
|
||||
|
|
@ -290,6 +313,9 @@ module up_hdmi_tx (
|
|||
12'h017: up_rdata <= {31'd0, up_hdmi_status_s};
|
||||
12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
|
||||
12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos};
|
||||
12'h01a: up_rdata <= {8'd0, up_clip_max};
|
||||
12'h01b: up_rdata <= {8'd0, up_clip_min};
|
||||
|
||||
12'h100: up_rdata <= {up_hl_active, up_hl_width};
|
||||
12'h101: up_rdata <= {16'd0, up_hs_width};
|
||||
12'h102: up_rdata <= {up_he_max, up_he_min};
|
||||
|
|
@ -311,7 +337,7 @@ module up_hdmi_tx (
|
|||
|
||||
// hdmi control & status
|
||||
|
||||
up_xfer_cntrl #(.DATA_WIDTH(189)) i_xfer_cntrl (
|
||||
up_xfer_cntrl #(.DATA_WIDTH(237)) i_xfer_cntrl (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_data_cntrl ({ up_ss_bypass,
|
||||
|
|
@ -328,7 +354,9 @@ module up_hdmi_tx (
|
|||
up_vf_width,
|
||||
up_vs_width,
|
||||
up_ve_max,
|
||||
up_ve_min}),
|
||||
up_ve_min,
|
||||
up_clip_max,
|
||||
up_clip_min}),
|
||||
.up_xfer_done (),
|
||||
.d_rst (hdmi_rst),
|
||||
.d_clk (hdmi_clk),
|
||||
|
|
@ -346,7 +374,9 @@ module up_hdmi_tx (
|
|||
hdmi_vf_width,
|
||||
hdmi_vs_width,
|
||||
hdmi_ve_max,
|
||||
hdmi_ve_min}));
|
||||
hdmi_ve_min,
|
||||
hdmi_clip_max,
|
||||
hdmi_clip_min}));
|
||||
|
||||
up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
|
||||
.up_rstn (up_rstn),
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
# check tool version
|
||||
|
||||
if {![info exists REQUIRED_VIVADO_VERSION]} {
|
||||
set REQUIRED_VIVADO_VERSION "2015.2.1"
|
||||
set REQUIRED_VIVADO_VERSION "2015.4.2"
|
||||
}
|
||||
|
||||
if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
|
||||
|
|
@ -78,13 +78,6 @@ proc adi_ip_bd {ip_name ip_bd_files} {
|
|||
proc adi_ip_properties {ip_name} {
|
||||
|
||||
ipx::package_project -root_dir .
|
||||
ipx::remove_memory_map {s_axi} [ipx::current_core]
|
||||
ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
set_property range {65536} [ipx::get_address_blocks axi_lite \
|
||||
-of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
|
||||
set_property vendor {analog.com} [ipx::current_core]
|
||||
set_property library {user} [ipx::current_core]
|
||||
|
|
@ -109,6 +102,47 @@ proc adi_ip_properties {ip_name} {
|
|||
{qzynq} {Production} \
|
||||
{azynq} {Production}} \
|
||||
[ipx::current_core]
|
||||
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
ipx::infer_bus_interface {\
|
||||
s_axi_awvalid \
|
||||
s_axi_awaddr \
|
||||
s_axi_awprot \
|
||||
s_axi_awready \
|
||||
s_axi_wvalid \
|
||||
s_axi_wdata \
|
||||
s_axi_wstrb \
|
||||
s_axi_wready \
|
||||
s_axi_bvalid \
|
||||
s_axi_bresp \
|
||||
s_axi_bready \
|
||||
s_axi_arvalid \
|
||||
s_axi_araddr \
|
||||
s_axi_arprot \
|
||||
s_axi_arready \
|
||||
s_axi_rvalid \
|
||||
s_axi_rdata \
|
||||
s_axi_rresp \
|
||||
s_axi_rready} \
|
||||
xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
ipx::add_memory_map {s_axi} [ipx::current_core]
|
||||
set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
||||
ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
||||
set_property range {65536} [ipx::get_address_blocks axi_lite \
|
||||
-of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
||||
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
-of_objects [ipx::get_bus_interfaces s_axi_aclk \
|
||||
-of_objects [ipx::current_core]]]
|
||||
|
||||
ipx::infer_bus_interfaces xilinx.com:interface:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interfaces xilinx.com:interface:reset_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
|
||||
}
|
||||
|
||||
proc adi_ip_properties_lite {ip_name} {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
|
||||
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
|
||||
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports dma_clk]]
|
||||
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *adc_xfer_req_m*}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *dma_waddr_rel_t*}]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_t_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_t_m_reg[0]* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *adc_waddr_rel_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
####################################################################################
|
||||
####################################################################################
|
||||
## Copyright 2011(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
|
||||
M_DEPS := util_clkdiv_ip.tcl
|
||||
M_DEPS += ../scripts/adi_env.tcl
|
||||
M_DEPS += ../scripts/adi_ip.tcl
|
||||
M_DEPS += util_clkdiv.v
|
||||
|
||||
M_VIVADO := vivado -mode batch -source
|
||||
|
||||
M_FLIST := *.cache
|
||||
M_FLIST += *.data
|
||||
M_FLIST += *.xpr
|
||||
M_FLIST += *.log
|
||||
M_FLIST += component.xml
|
||||
M_FLIST += *.jou
|
||||
M_FLIST += xgui
|
||||
M_FLIST += *.ip_user_files
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
||||
.PHONY: all clean clean-all
|
||||
all: util_clkdiv.xpr
|
||||
|
||||
|
||||
clean:clean-all
|
||||
|
||||
|
||||
clean-all:
|
||||
rm -rf $(M_FLIST)
|
||||
|
||||
|
||||
util_clkdiv.xpr: $(M_DEPS)
|
||||
-rm -rf $(M_FLIST)
|
||||
$(M_VIVADO) util_clkdiv_ip.tcl >> util_clkdiv_ip.log 2>&1
|
||||
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module util_clkdiv (
|
||||
clk,
|
||||
clk_out
|
||||
);
|
||||
|
||||
input clk;
|
||||
output clk_out;
|
||||
|
||||
BUFR #(
|
||||
.BUFR_DIVIDE("4"),
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) clk_divide (
|
||||
.I(clk),
|
||||
.CE(1),
|
||||
.CLR(0),
|
||||
.O(clk_div_s));
|
||||
|
||||
BUFG i_div_clk_gbuf (
|
||||
.I (clk_div_s),
|
||||
.O (clk_out));
|
||||
|
||||
endmodule // util_clkdiv
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip.tcl
|
||||
|
||||
adi_ip_create util_clkdiv
|
||||
adi_ip_files util_clkdiv [list \
|
||||
"util_clkdiv.v" ]
|
||||
|
||||
adi_ip_properties_lite util_clkdiv
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
|
@ -55,10 +55,14 @@ module util_dacfifo (
|
|||
|
||||
dac_clk,
|
||||
dac_valid,
|
||||
dac_data
|
||||
dac_data,
|
||||
dac_xfer_out,
|
||||
|
||||
dac_fifo_bypass
|
||||
);
|
||||
|
||||
// depth of the FIFO
|
||||
|
||||
parameter ADDRESS_WIDTH = 6;
|
||||
parameter DATA_WIDTH = 128;
|
||||
|
||||
|
|
@ -79,30 +83,36 @@ module util_dacfifo (
|
|||
input dac_clk;
|
||||
input dac_valid;
|
||||
output [(DATA_WIDTH-1):0] dac_data;
|
||||
output dac_xfer_out;
|
||||
|
||||
input dac_fifo_bypass;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_d = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_2d = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_d = 'b0;
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_2d = 'b0;
|
||||
reg dma_xfer_req_ff = 1'b0;
|
||||
reg dma_ready = 1'b0;
|
||||
reg dma_ready_d = 1'b0;
|
||||
|
||||
reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
|
||||
reg [(DATA_WIDTH-1):0] dac_data = 'b0;
|
||||
reg dma_xfer_out = 1'b0;
|
||||
reg [ 2:0] dac_xfer_out_m = 3'b0;
|
||||
|
||||
// internal wires
|
||||
|
||||
wire dma_wren;
|
||||
wire [(DATA_WIDTH-1):0] dac_data_s;
|
||||
|
||||
// write interface
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if(dma_rst == 1'b1) begin
|
||||
dma_ready <= 1'b0;
|
||||
dma_ready_d <= 1'b0;
|
||||
dma_xfer_req_ff <= 1'b0;
|
||||
end else begin
|
||||
dma_ready <= 1'b1; // Fifo is always ready
|
||||
dma_ready_d <= 1'b1; // Fifo is always ready
|
||||
dma_xfer_req_ff <= dma_xfer_req;
|
||||
end
|
||||
end
|
||||
|
|
@ -111,40 +121,44 @@ module util_dacfifo (
|
|||
if(dma_rst == 1'b1) begin
|
||||
dma_waddr <= 'b0;
|
||||
dma_lastaddr <= 'b0;
|
||||
dma_xfer_out <= 1'b0;
|
||||
end else begin
|
||||
if (dma_valid && dma_xfer_req) begin
|
||||
dma_waddr <= dma_waddr + 1;
|
||||
dma_xfer_out <= 1'b0;
|
||||
end
|
||||
if (dma_xfer_last) begin
|
||||
dma_lastaddr <= dma_waddr;
|
||||
dma_waddr <= 'b0;
|
||||
dma_xfer_out <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign dma_wren = dma_valid & dma_xfer_req;
|
||||
|
||||
// read interface
|
||||
|
||||
// sync lastaddr to dac clock domain
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dma_lastaddr_d <= dma_lastaddr;
|
||||
dma_lastaddr_2d <= dma_lastaddr_d;
|
||||
dac_lastaddr_d <= dma_lastaddr;
|
||||
dac_lastaddr_2d <= dac_lastaddr_d;
|
||||
dac_xfer_out_m <= {dac_xfer_out_m[1:0], dma_xfer_out};
|
||||
end
|
||||
|
||||
assign dac_xfer_out = dac_xfer_out_m[2];
|
||||
|
||||
// generate dac read address
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if(dac_valid == 1'b1) begin
|
||||
if (dma_lastaddr_2d == 'h0) begin
|
||||
if (dac_lastaddr_2d == 'h0) begin
|
||||
dac_raddr <= dac_raddr + 1;
|
||||
end else begin
|
||||
dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
|
||||
dac_raddr <= (dac_raddr < dac_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
|
||||
end
|
||||
end
|
||||
dac_data <= dac_data_s;
|
||||
end
|
||||
|
||||
|
||||
// memory instantiation
|
||||
|
||||
ad_mem #(
|
||||
|
|
@ -159,5 +173,10 @@ module util_dacfifo (
|
|||
.addrb (dac_raddr),
|
||||
.doutb (dac_data_s));
|
||||
|
||||
// output logic
|
||||
|
||||
assign dac_data = (dac_fifo_bypass) ? dma_data : dac_data_s;
|
||||
assign dma_ready = (dac_fifo_bypass) ? dac_valid : dma_ready_d;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_lastaddr_d*}]
|
||||
set_property shreg_extract no [get_cells -hier -filter {name =~ *dac_xfer_out_m*}]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *dma_lastaddr_reg* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_lastaddr_d_reg* && IS_SEQUENTIAL}]
|
||||
set_false_path -to [get_cells -hier -filter {name =~ *dac_xfer_out_m_reg[0]* && IS_SEQUENTIAL}]
|
||||
|
||||
|
|
@ -6,9 +6,12 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
|
|||
adi_ip_create util_dacfifo
|
||||
adi_ip_files util_dacfifo [list \
|
||||
"$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
"util_dacfifo.v" ]
|
||||
"util_dacfifo.v" \
|
||||
"util_dacfifo_constr.xdc"]
|
||||
|
||||
adi_ip_properties_lite util_dacfifo
|
||||
adi_ip_constraints util_dacfifo [list \
|
||||
"util_dacfifo_constr.xdc" ]
|
||||
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
|
|
|||
|
|
@ -15,9 +15,8 @@ adi_ip_constraints util_gmii_to_rgmii [list \
|
|||
"util_gmii_to_rgmii_constr.xdc" ]
|
||||
|
||||
ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core]
|
||||
set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]]
|
||||
set_property name {gmii} [ipx::get_bus_interface gmii_1 [ipx::current_core]]
|
||||
ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core]
|
||||
set_property value ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of_objects [ipx::get_bus_interfaces reset -of_objects [ipx::current_core]]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \
|
||||
[ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]]
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ create_bd_port -dir I -from 1 -to 0 rx_data_n
|
|||
|
||||
set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
|
||||
|
||||
set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad6676_jesd]
|
||||
set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad6676_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -34,6 +34,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
|
|||
|
||||
# audio peripherals
|
||||
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -4,3 +4,5 @@ source $ad_hdl_dir/projects/adv7511/common/adv7511_bd.tcl
|
|||
|
||||
set_property -dict [list CONFIG.c_m_axi_mm2s_data_width {512}] $axi_hdmi_dma
|
||||
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
|
||||
set_property -dict [list CONFIG.S04_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -113,6 +113,38 @@
|
|||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
|
|
@ -176,6 +208,21 @@
|
|||
internal="c5soc.sys_hps_hps_io"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="sys_hps_i2c0"
|
||||
internal="c5soc.sys_hps_i2c0"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="sys_hps_i2c0_clk"
|
||||
internal="c5soc.sys_hps_i2c0_clk"
|
||||
type="clock"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="sys_hps_i2c0_scl_in"
|
||||
internal="c5soc.sys_hps_i2c0_scl_in"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="sys_hps_memory"
|
||||
internal="c5soc.sys_hps_memory"
|
||||
|
|
@ -217,9 +264,9 @@
|
|||
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
|
||||
<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="10" />
|
||||
<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="80000000" />
|
||||
<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
|
||||
<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="10" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
|
||||
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
|
||||
|
|
@ -237,6 +284,9 @@
|
|||
<parameter
|
||||
name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 18" />
|
||||
<parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_CLOCK_DOMAIN" value="7" />
|
||||
<parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_CLOCK_RATE" value="0" />
|
||||
<parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_RESET_DOMAIN" value="7" />
|
||||
<parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" />
|
||||
</module>
|
||||
|
|
|
|||
|
|
@ -96,5 +96,18 @@ set_location_assignment PIN_H12 -to spi_clk
|
|||
set_location_assignment PIN_H13 -to spi_mosi
|
||||
set_location_assignment PIN_G11 -to spi_miso
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to scl
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to sda
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ga0
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ga1
|
||||
|
||||
set_location_assignment PIN_F15 -to scl
|
||||
set_location_assignment PIN_G13 -to sda
|
||||
set_location_assignment PIN_C7 -to ga0
|
||||
set_location_assignment PIN_H14 -to ga1
|
||||
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to scl
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sda
|
||||
|
||||
execute_flow -compile
|
||||
|
||||
|
|
|
|||
|
|
@ -140,6 +140,13 @@ module system_top (
|
|||
ad9361_enable,
|
||||
ad9361_txnrx,
|
||||
|
||||
// iic interface
|
||||
|
||||
scl,
|
||||
sda,
|
||||
ga0,
|
||||
ga1,
|
||||
|
||||
// spi
|
||||
|
||||
spi_csn,
|
||||
|
|
@ -248,6 +255,14 @@ module system_top (
|
|||
output ad9361_enable;
|
||||
output ad9361_txnrx;
|
||||
|
||||
// iic interface
|
||||
|
||||
inout scl;
|
||||
inout sda;
|
||||
output ga0;
|
||||
output ga1;
|
||||
|
||||
|
||||
// spi interface
|
||||
|
||||
output spi_csn;
|
||||
|
|
@ -300,14 +315,26 @@ module system_top (
|
|||
wire vid_h_sync;
|
||||
wire [7:0] vid_r,vid_g,vid_b;
|
||||
|
||||
wire i2c0_out_data;
|
||||
wire i2c0_sda;
|
||||
wire i2c0_out_clk;
|
||||
wire i2c0_scl_in_clk;
|
||||
|
||||
// defaults
|
||||
|
||||
|
||||
assign vga_clk = vga_pixel_clock;
|
||||
assign vga_blank_n = 1'b1;
|
||||
assign vga_sync_n = 1'b0;
|
||||
assign vga_hs = vid_h_sync;
|
||||
assign vga_vs = vid_v_sync;
|
||||
assign {vga_b,vga_g,vga_r} = {vid_b,vid_g,vid_r};
|
||||
assign ga0 = 1'b0;
|
||||
assign ga1 = 1'b0;
|
||||
|
||||
|
||||
ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl)); //
|
||||
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda)); //
|
||||
|
||||
|
||||
// instantiations
|
||||
|
||||
|
|
@ -437,6 +464,10 @@ module system_top (
|
|||
.vga_clock_video_output_clocked_video_vid_f (),
|
||||
.vga_clock_video_output_clocked_video_vid_h (),
|
||||
.vga_clock_video_output_clocked_video_vid_v (),
|
||||
.sys_hps_i2c0_out_data(i2c0_out_data),
|
||||
.sys_hps_i2c0_sda(i2c0_sda),
|
||||
.sys_hps_i2c0_clk_clk(i2c0_out_clk),
|
||||
.sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk),
|
||||
.gpio_external_connection_export ({ad9361_resetb, ad9361_en_agc, ad9361_sync, ad9361_enable, ad9361_txnrx})
|
||||
);
|
||||
|
||||
|
|
|
|||
|
|
@ -86,6 +86,14 @@
|
|||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element axi_ad9361
|
||||
{
|
||||
datum _sortIndex
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -2,13 +2,14 @@
|
|||
# device settings
|
||||
|
||||
set_global_assignment -name FAMILY "Arria 10"
|
||||
set_global_assignment -name DEVICE 10AX115S3F45I2SGE2
|
||||
set_global_assignment -name DEVICE 10AX115S3F45E2SGE3
|
||||
|
||||
# clocks and resets
|
||||
|
||||
set_location_assignment PIN_BD32 -to sys_clk
|
||||
set_location_assignment PIN_AR36 -to sys_clk
|
||||
set_location_assignment PIN_AR37 -to "sys_clk(n)"
|
||||
set_location_assignment PIN_BD27 -to sys_resetn
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_clk
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to sys_clk
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to sys_resetn
|
||||
|
||||
# ddr3
|
||||
|
|
@ -170,61 +171,61 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_ref_clk
|
|||
|
||||
# leds
|
||||
|
||||
set_location_assignment PIN_L28 -to gpio_bd[0] ; ## led-g0-d10
|
||||
set_location_assignment PIN_K26 -to gpio_bd[1] ; ## led-g1-d9
|
||||
set_location_assignment PIN_K25 -to gpio_bd[2] ; ## led-g2-d8
|
||||
set_location_assignment PIN_L25 -to gpio_bd[3] ; ## led-g3-d7
|
||||
set_location_assignment PIN_J24 -to gpio_bd[4] ; ## led-g4-d6
|
||||
set_location_assignment PIN_A19 -to gpio_bd[5] ; ## led-g5-d5
|
||||
set_location_assignment PIN_C18 -to gpio_bd[6] ; ## led-g6-d4
|
||||
set_location_assignment PIN_D18 -to gpio_bd[7] ; ## led-g7-d3
|
||||
set_location_assignment PIN_L27 -to gpio_bd[8] ; ## led-r0-d10
|
||||
set_location_assignment PIN_J26 -to gpio_bd[9] ; ## led-r1-d9
|
||||
set_location_assignment PIN_K24 -to gpio_bd[10] ; ## led-r2-d8
|
||||
set_location_assignment PIN_L23 -to gpio_bd[11] ; ## led-r3-d7
|
||||
set_location_assignment PIN_B20 -to gpio_bd[12] ; ## led-r4-d6
|
||||
set_location_assignment PIN_C19 -to gpio_bd[13] ; ## led-r5-d5
|
||||
set_location_assignment PIN_D19 -to gpio_bd[14] ; ## led-r6-d4
|
||||
set_location_assignment PIN_M23 -to gpio_bd[15] ; ## led-r7-d3
|
||||
set_location_assignment PIN_A24 -to gpio_bd[16] ; ## dipsw0
|
||||
set_location_assignment PIN_B23 -to gpio_bd[17] ; ## dipsw1
|
||||
set_location_assignment PIN_A23 -to gpio_bd[18] ; ## dipsw2
|
||||
set_location_assignment PIN_B22 -to gpio_bd[19] ; ## dipsw3
|
||||
set_location_assignment PIN_A22 -to gpio_bd[20] ; ## dipsw4
|
||||
set_location_assignment PIN_B21 -to gpio_bd[21] ; ## dipsw5
|
||||
set_location_assignment PIN_C21 -to gpio_bd[22] ; ## dipsw6
|
||||
set_location_assignment PIN_A20 -to gpio_bd[23] ; ## dipsw7
|
||||
set_location_assignment PIN_T12 -to gpio_bd[24] ; ## pb0-s3
|
||||
set_location_assignment PIN_U12 -to gpio_bd[25] ; ## pb1-s2
|
||||
set_location_assignment PIN_U11 -to gpio_bd[26] ; ## pb2-s1
|
||||
set_location_assignment PIN_L28 -to gpio_bd_o[0] ; ## led-g0-d10
|
||||
set_location_assignment PIN_K26 -to gpio_bd_o[1] ; ## led-g1-d9
|
||||
set_location_assignment PIN_K25 -to gpio_bd_o[2] ; ## led-g2-d8
|
||||
set_location_assignment PIN_L25 -to gpio_bd_o[3] ; ## led-g3-d7
|
||||
set_location_assignment PIN_J24 -to gpio_bd_o[4] ; ## led-g4-d6
|
||||
set_location_assignment PIN_A19 -to gpio_bd_o[5] ; ## led-g5-d5
|
||||
set_location_assignment PIN_C18 -to gpio_bd_o[6] ; ## led-g6-d4
|
||||
set_location_assignment PIN_D18 -to gpio_bd_o[7] ; ## led-g7-d3
|
||||
set_location_assignment PIN_L27 -to gpio_bd_o[8] ; ## led-r0-d10
|
||||
set_location_assignment PIN_J26 -to gpio_bd_o[9] ; ## led-r1-d9
|
||||
set_location_assignment PIN_K24 -to gpio_bd_o[10] ; ## led-r2-d8
|
||||
set_location_assignment PIN_L23 -to gpio_bd_o[11] ; ## led-r3-d7
|
||||
set_location_assignment PIN_B20 -to gpio_bd_o[12] ; ## led-r4-d6
|
||||
set_location_assignment PIN_C19 -to gpio_bd_o[13] ; ## led-r5-d5
|
||||
set_location_assignment PIN_D19 -to gpio_bd_o[14] ; ## led-r6-d4
|
||||
set_location_assignment PIN_M23 -to gpio_bd_o[15] ; ## led-r7-d3
|
||||
set_location_assignment PIN_A24 -to gpio_bd_i[0] ; ## dipsw0
|
||||
set_location_assignment PIN_B23 -to gpio_bd_i[1] ; ## dipsw1
|
||||
set_location_assignment PIN_A23 -to gpio_bd_i[2] ; ## dipsw2
|
||||
set_location_assignment PIN_B22 -to gpio_bd_i[3] ; ## dipsw3
|
||||
set_location_assignment PIN_A22 -to gpio_bd_i[4] ; ## dipsw4
|
||||
set_location_assignment PIN_B21 -to gpio_bd_i[5] ; ## dipsw5
|
||||
set_location_assignment PIN_C21 -to gpio_bd_i[6] ; ## dipsw6
|
||||
set_location_assignment PIN_A20 -to gpio_bd_i[7] ; ## dipsw7
|
||||
set_location_assignment PIN_T12 -to gpio_bd_i[8] ; ## pb0-s3
|
||||
set_location_assignment PIN_U12 -to gpio_bd_i[9] ; ## pb1-s2
|
||||
set_location_assignment PIN_U11 -to gpio_bd_i[10] ; ## pb2-s1
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[0]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[1]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[2]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[3]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[4]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[5]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[6]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[7]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[8]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[9]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[10]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[11]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[12]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[13]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[14]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[15]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[16]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[17]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[18]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[19]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[20]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[21]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[22]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[23]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[24]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[25]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd[26]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[0]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[1]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[2]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[3]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[4]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[5]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[6]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[7]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[8]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[9]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[10]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[11]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[12]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[13]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[14]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_o[15]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[0]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[1]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[2]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[3]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[4]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[5]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[6]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[7]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[8]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[9]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_bd_i[10]
|
||||
|
||||
# globals
|
||||
|
||||
|
|
|
|||
|
|
@ -601,7 +601,7 @@
|
|||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
<parameter name="device" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="device" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="deviceFamily" value="Arria 10" />
|
||||
<parameter name="deviceSpeedGrade" value="2" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
|
|
@ -733,7 +733,7 @@
|
|||
<module name="sys_cpu" kind="altera_nios2_gen2" version="15.1" enabled="1">
|
||||
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="bht_ramBlockType" value="Automatic" />
|
||||
<parameter name="breakOffset" value="32" />
|
||||
|
|
@ -1862,14 +1862,14 @@
|
|||
<parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
|
||||
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR3" />
|
||||
<parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
|
||||
<parameter name="SYS_INFO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="SYS_INFO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_sys_ddr3_cntrl</parameter>
|
||||
<parameter name="TRAIT_SUPPORTS_VID" value="0" />
|
||||
</module>
|
||||
<module name="sys_ethernet" kind="altera_eth_tse" version="15.1" enabled="1">
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="core_variation" value="MAC_PCS" />
|
||||
<parameter name="deviceFamilyName" value="Arria 10" />
|
||||
|
|
@ -1922,7 +1922,7 @@
|
|||
<parameter
|
||||
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
|
||||
value="AddressWidth = -1" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_MM_READ_ADDRESS_MAP" value="" />
|
||||
|
|
@ -1968,7 +1968,7 @@
|
|||
<parameter
|
||||
name="AUTO_DESCRIPTOR_WRITE_MASTER_ADDRESS_WIDTH"
|
||||
value="AddressWidth = -1" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_MM_READ_ADDRESS_MAP"><![CDATA[<address-map><slave name='sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
|
||||
|
|
@ -2046,7 +2046,7 @@
|
|||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="6" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module
|
||||
name="sys_gpio_out"
|
||||
|
|
@ -2064,7 +2064,7 @@
|
|||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="4" />
|
||||
<parameter name="width" value="32" />
|
||||
</module>
|
||||
<module
|
||||
name="sys_id"
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
|
|
@ -62,7 +62,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
|
|||
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
|
||||
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
|
||||
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
|
||||
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
|
||||
|
||||
# instance: microblaze- mdm
|
||||
|
|
@ -76,14 +76,14 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
|
|||
|
||||
# instance: ddr (mig)
|
||||
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
|
||||
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
|
||||
file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/"
|
||||
set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl
|
||||
|
||||
# instance: default peripherals
|
||||
|
||||
set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_ethernet_clkgen]
|
||||
set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_ethernet_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen
|
||||
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "0";
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
|
|
@ -107,7 +107,7 @@
|
|||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "0";
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
|
|
@ -419,6 +419,17 @@
|
|||
internal="sys_hps.hps_io"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="sys_hps_i2c0" internal="sys_hps.i2c0" type="conduit" dir="end" />
|
||||
<interface
|
||||
name="sys_hps_i2c0_clk"
|
||||
internal="sys_hps.i2c0_clk"
|
||||
type="clock"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="sys_hps_i2c0_scl_in"
|
||||
internal="sys_hps.i2c0_scl_in"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="sys_hps_memory"
|
||||
internal="sys_hps.memory"
|
||||
|
|
@ -686,7 +697,7 @@
|
|||
<parameter
|
||||
name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
|
||||
value="100" />
|
||||
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
|
||||
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="0" />
|
||||
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
|
||||
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
|
||||
<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
|
||||
|
|
@ -721,8 +732,8 @@
|
|||
<parameter name="HHP_HPS_VERIFICATION" value="false" />
|
||||
<parameter name="HLGPI_Enable" value="false" />
|
||||
<parameter name="HPS_PROTOCOL" value="DDR3" />
|
||||
<parameter name="I2C0_Mode" value="N/A" />
|
||||
<parameter name="I2C0_PinMuxing" value="Unused" />
|
||||
<parameter name="I2C0_Mode" value="Full" />
|
||||
<parameter name="I2C0_PinMuxing" value="FPGA" />
|
||||
<parameter name="I2C1_Mode" value="N/A" />
|
||||
<parameter name="I2C1_PinMuxing" value="Unused" />
|
||||
<parameter name="I2C2_Mode" value="N/A" />
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
|
|||
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
|
||||
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
|
||||
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
|
||||
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
|
||||
|
||||
# instance: microblaze- mdm
|
||||
|
|
@ -82,7 +82,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
|
|||
|
||||
# instance: ddr (mig)
|
||||
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
|
||||
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
|
||||
file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/"
|
||||
set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
|
|||
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
|
||||
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
|
||||
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
|
||||
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
|
||||
|
||||
# instance: microblaze- mdm
|
||||
|
|
@ -80,32 +80,23 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
|
|||
|
||||
# instance: ddr (mig)
|
||||
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig:7.1 axi_ddr_cntrl]
|
||||
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
|
||||
set axi_ddr_cntrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:1.1 axi_ddr_cntrl ]
|
||||
set_property -dict [list CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_300}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl
|
||||
|
||||
set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen]
|
||||
|
||||
# instance: default peripherals
|
||||
|
||||
set axi_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 axi_ethernet_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {625}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.PRIM_SOURCE {Differential_clock_capable_pin}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT2_USED {true}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {312}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT3_USED {true}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {625}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT4_USED {false}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.USE_LOCKED {true}] $axi_ethernet_clkgen
|
||||
set_property -dict [list CONFIG.USE_RESET {false}] $axi_ethernet_clkgen
|
||||
|
||||
set axi_ethernet_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ethernet_rstgen]
|
||||
set axi_ethernet_idelayctrl [create_bd_cell -type ip -vlnv xilinx.com:ip:util_idelay_ctrl:1.0 axi_ethernet_idelayctrl]
|
||||
|
||||
set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet]
|
||||
set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.ENABLE_LVDS {true}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.SupportLevel {0}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.SupportLevel {1}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.lvdsclkrate {625}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet
|
||||
|
|
@ -210,13 +201,12 @@ ad_connect c0_ddr4 axi_ddr_cntrl/C0_DDR4
|
|||
ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK
|
||||
|
||||
ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in
|
||||
ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ethernet_rstgen/ext_reset_in
|
||||
ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in
|
||||
ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk
|
||||
|
||||
# defaults (ethernet)
|
||||
|
||||
ad_connect phy_clk axi_ethernet_clkgen/CLK_IN1_D
|
||||
ad_connect phy_clk axi_ethernet/lvds_clk
|
||||
ad_connect mdio axi_ethernet/mdio
|
||||
ad_connect sgmii axi_ethernet/sgmii
|
||||
ad_connect axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S
|
||||
|
|
@ -225,19 +215,10 @@ ad_connect axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM
|
|||
ad_connect axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS
|
||||
ad_connect phy_sd axi_ethernet/signal_detect
|
||||
ad_connect sys_cpu_resetn phy_rst_n
|
||||
ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet/clk125m
|
||||
ad_connect axi_ethernet_clkgen/clk_out1 axi_ethernet_rstgen/slowest_sync_clk
|
||||
ad_connect axi_ethernet_clkgen/clk_out2 axi_ethernet/clk312
|
||||
ad_connect axi_ethernet_clkgen/clk_out3 axi_ethernet/clk625
|
||||
ad_connect axi_ethernet_clkgen/locked axi_ethernet/mmcm_locked
|
||||
ad_connect axi_ethernet_rstgen/peripheral_reset axi_ethernet/rst_125
|
||||
ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n
|
||||
ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n
|
||||
ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n
|
||||
ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n
|
||||
ad_connect axi_ethernet_idelayctrl/rdy axi_ethernet/idelay_rdy_in
|
||||
ad_connect axi_ethernet_idelayctrl/rst axi_ethernet_rstgen/peripheral_reset
|
||||
ad_connect axi_ethernet_idelayctrl/ref_clk axi_ethernet_clkgen/clk_out3
|
||||
|
||||
# defaults (misc)
|
||||
|
||||
|
|
@ -274,6 +255,8 @@ ad_cpu_interconnect 0x44A70000 axi_spi
|
|||
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect
|
||||
set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect]
|
||||
set_property CONFIG.NUM_SI {1} [get_bd_cells axi_ddr_interconnect]
|
||||
set_property CONFIG.S00_HAS_REGSLICE {4} [get_bd_cells axi_ddr_interconnect]
|
||||
set_property CONFIG.S00_HAS_DATA_FIFO {1} [get_bd_cells axi_ddr_interconnect]
|
||||
|
||||
ad_connect axi_ddr_interconnect/M00_AXI axi_ddr_cntrl/C0_DDR4_S_AXI
|
||||
ad_connect sys_mem_clk axi_ddr_interconnect/ACLK
|
||||
|
|
|
|||
|
|
@ -3,26 +3,15 @@
|
|||
|
||||
set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst]
|
||||
|
||||
# clocks
|
||||
|
||||
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports phy_clk_p]
|
||||
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25} [get_ports phy_clk_n]
|
||||
|
||||
# ethernet
|
||||
|
||||
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports mdio_mdc]
|
||||
set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports mdio_mdio]
|
||||
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n]
|
||||
set_property -dict {PACKAGE_PIN N24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_tx_p]
|
||||
set_property -dict {PACKAGE_PIN M24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_tx_n]
|
||||
set_property -dict {PACKAGE_PIN P24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_rx_p]
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_rx_n]
|
||||
|
||||
# uart
|
||||
|
||||
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sout]
|
||||
set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports uart_sin]
|
||||
|
||||
# ethernet (phy_rst_n automation cannot be used with axi_ethernet 7.0)
|
||||
|
||||
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n]
|
||||
|
||||
# fan
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
|
||||
|
|
@ -56,125 +45,11 @@ set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda
|
|||
|
||||
set_property -dict {PACKAGE_PIN AK17} [get_ports sys_clk_p]
|
||||
set_property -dict {PACKAGE_PIN AK16} [get_ports sys_clk_n]
|
||||
set_property -dict {PACKAGE_PIN AH14} [get_ports ddr4_act_n]
|
||||
set_property -dict {PACKAGE_PIN AE17} [get_ports ddr4_addr[0]]
|
||||
set_property -dict {PACKAGE_PIN AH17} [get_ports ddr4_addr[1]]
|
||||
set_property -dict {PACKAGE_PIN AE18} [get_ports ddr4_addr[2]]
|
||||
set_property -dict {PACKAGE_PIN AJ15} [get_ports ddr4_addr[3]]
|
||||
set_property -dict {PACKAGE_PIN AG16} [get_ports ddr4_addr[4]]
|
||||
set_property -dict {PACKAGE_PIN AL17} [get_ports ddr4_addr[5]]
|
||||
set_property -dict {PACKAGE_PIN AK18} [get_ports ddr4_addr[6]]
|
||||
set_property -dict {PACKAGE_PIN AG17} [get_ports ddr4_addr[7]]
|
||||
set_property -dict {PACKAGE_PIN AF18} [get_ports ddr4_addr[8]]
|
||||
set_property -dict {PACKAGE_PIN AH19} [get_ports ddr4_addr[9]]
|
||||
set_property -dict {PACKAGE_PIN AF15} [get_ports ddr4_addr[10]]
|
||||
set_property -dict {PACKAGE_PIN AD19} [get_ports ddr4_addr[11]]
|
||||
set_property -dict {PACKAGE_PIN AJ14} [get_ports ddr4_addr[12]]
|
||||
set_property -dict {PACKAGE_PIN AG19} [get_ports ddr4_addr[13]]
|
||||
set_property -dict {PACKAGE_PIN AD16} [get_ports ddr4_addr[14]]
|
||||
set_property -dict {PACKAGE_PIN AG14} [get_ports ddr4_addr[15]]
|
||||
set_property -dict {PACKAGE_PIN AF14} [get_ports ddr4_addr[16]]
|
||||
set_property -dict {PACKAGE_PIN AF17} [get_ports ddr4_ba[0]]
|
||||
set_property -dict {PACKAGE_PIN AL15} [get_ports ddr4_ba[1]]
|
||||
set_property -dict {PACKAGE_PIN AG15} [get_ports ddr4_bg[0]]
|
||||
set_property -dict {PACKAGE_PIN AE16} [get_ports ddr4_ck_p]
|
||||
set_property -dict {PACKAGE_PIN AE15} [get_ports ddr4_ck_n]
|
||||
set_property -dict {PACKAGE_PIN AD15} [get_ports ddr4_cke[0]]
|
||||
set_property -dict {PACKAGE_PIN AL19} [get_ports ddr4_cs_n[0]]
|
||||
set_property -dict {PACKAGE_PIN AD21} [get_ports ddr4_dm_n[0]]
|
||||
set_property -dict {PACKAGE_PIN AE25} [get_ports ddr4_dm_n[1]]
|
||||
set_property -dict {PACKAGE_PIN AJ21} [get_ports ddr4_dm_n[2]]
|
||||
set_property -dict {PACKAGE_PIN AM21} [get_ports ddr4_dm_n[3]]
|
||||
set_property -dict {PACKAGE_PIN AH26} [get_ports ddr4_dm_n[4]]
|
||||
set_property -dict {PACKAGE_PIN AN26} [get_ports ddr4_dm_n[5]]
|
||||
set_property -dict {PACKAGE_PIN AJ29} [get_ports ddr4_dm_n[6]]
|
||||
set_property -dict {PACKAGE_PIN AL32} [get_ports ddr4_dm_n[7]]
|
||||
set_property -dict {PACKAGE_PIN AE23} [get_ports ddr4_dq[0]]
|
||||
set_property -dict {PACKAGE_PIN AG20} [get_ports ddr4_dq[1]]
|
||||
set_property -dict {PACKAGE_PIN AF22} [get_ports ddr4_dq[2]]
|
||||
set_property -dict {PACKAGE_PIN AF20} [get_ports ddr4_dq[3]]
|
||||
set_property -dict {PACKAGE_PIN AE22} [get_ports ddr4_dq[4]]
|
||||
set_property -dict {PACKAGE_PIN AD20} [get_ports ddr4_dq[5]]
|
||||
set_property -dict {PACKAGE_PIN AG22} [get_ports ddr4_dq[6]]
|
||||
set_property -dict {PACKAGE_PIN AE20} [get_ports ddr4_dq[7]]
|
||||
set_property -dict {PACKAGE_PIN AJ24} [get_ports ddr4_dq[8]]
|
||||
set_property -dict {PACKAGE_PIN AG24} [get_ports ddr4_dq[9]]
|
||||
set_property -dict {PACKAGE_PIN AJ23} [get_ports ddr4_dq[10]]
|
||||
set_property -dict {PACKAGE_PIN AF23} [get_ports ddr4_dq[11]]
|
||||
set_property -dict {PACKAGE_PIN AH23} [get_ports ddr4_dq[12]]
|
||||
set_property -dict {PACKAGE_PIN AF24} [get_ports ddr4_dq[13]]
|
||||
set_property -dict {PACKAGE_PIN AH22} [get_ports ddr4_dq[14]]
|
||||
set_property -dict {PACKAGE_PIN AG25} [get_ports ddr4_dq[15]]
|
||||
set_property -dict {PACKAGE_PIN AL22} [get_ports ddr4_dq[16]]
|
||||
set_property -dict {PACKAGE_PIN AL25} [get_ports ddr4_dq[17]]
|
||||
set_property -dict {PACKAGE_PIN AM20} [get_ports ddr4_dq[18]]
|
||||
set_property -dict {PACKAGE_PIN AK23} [get_ports ddr4_dq[19]]
|
||||
set_property -dict {PACKAGE_PIN AK22} [get_ports ddr4_dq[20]]
|
||||
set_property -dict {PACKAGE_PIN AL24} [get_ports ddr4_dq[21]]
|
||||
set_property -dict {PACKAGE_PIN AL20} [get_ports ddr4_dq[22]]
|
||||
set_property -dict {PACKAGE_PIN AL23} [get_ports ddr4_dq[23]]
|
||||
set_property -dict {PACKAGE_PIN AM24} [get_ports ddr4_dq[24]]
|
||||
set_property -dict {PACKAGE_PIN AN23} [get_ports ddr4_dq[25]]
|
||||
set_property -dict {PACKAGE_PIN AN24} [get_ports ddr4_dq[26]]
|
||||
set_property -dict {PACKAGE_PIN AP23} [get_ports ddr4_dq[27]]
|
||||
set_property -dict {PACKAGE_PIN AP25} [get_ports ddr4_dq[28]]
|
||||
set_property -dict {PACKAGE_PIN AN22} [get_ports ddr4_dq[29]]
|
||||
set_property -dict {PACKAGE_PIN AP24} [get_ports ddr4_dq[30]]
|
||||
set_property -dict {PACKAGE_PIN AM22} [get_ports ddr4_dq[31]]
|
||||
set_property -dict {PACKAGE_PIN AH28} [get_ports ddr4_dq[32]]
|
||||
set_property -dict {PACKAGE_PIN AK26} [get_ports ddr4_dq[33]]
|
||||
set_property -dict {PACKAGE_PIN AK28} [get_ports ddr4_dq[34]]
|
||||
set_property -dict {PACKAGE_PIN AM27} [get_ports ddr4_dq[35]]
|
||||
set_property -dict {PACKAGE_PIN AJ28} [get_ports ddr4_dq[36]]
|
||||
set_property -dict {PACKAGE_PIN AH27} [get_ports ddr4_dq[37]]
|
||||
set_property -dict {PACKAGE_PIN AK27} [get_ports ddr4_dq[38]]
|
||||
set_property -dict {PACKAGE_PIN AM26} [get_ports ddr4_dq[39]]
|
||||
set_property -dict {PACKAGE_PIN AL30} [get_ports ddr4_dq[40]]
|
||||
set_property -dict {PACKAGE_PIN AP29} [get_ports ddr4_dq[41]]
|
||||
set_property -dict {PACKAGE_PIN AM30} [get_ports ddr4_dq[42]]
|
||||
set_property -dict {PACKAGE_PIN AN28} [get_ports ddr4_dq[43]]
|
||||
set_property -dict {PACKAGE_PIN AL29} [get_ports ddr4_dq[44]]
|
||||
set_property -dict {PACKAGE_PIN AP28} [get_ports ddr4_dq[45]]
|
||||
set_property -dict {PACKAGE_PIN AM29} [get_ports ddr4_dq[46]]
|
||||
set_property -dict {PACKAGE_PIN AN27} [get_ports ddr4_dq[47]]
|
||||
set_property -dict {PACKAGE_PIN AH31} [get_ports ddr4_dq[48]]
|
||||
set_property -dict {PACKAGE_PIN AH32} [get_ports ddr4_dq[49]]
|
||||
set_property -dict {PACKAGE_PIN AJ34} [get_ports ddr4_dq[50]]
|
||||
set_property -dict {PACKAGE_PIN AK31} [get_ports ddr4_dq[51]]
|
||||
set_property -dict {PACKAGE_PIN AJ31} [get_ports ddr4_dq[52]]
|
||||
set_property -dict {PACKAGE_PIN AJ30} [get_ports ddr4_dq[53]]
|
||||
set_property -dict {PACKAGE_PIN AH34} [get_ports ddr4_dq[54]]
|
||||
set_property -dict {PACKAGE_PIN AK32} [get_ports ddr4_dq[55]]
|
||||
set_property -dict {PACKAGE_PIN AN33} [get_ports ddr4_dq[56]]
|
||||
set_property -dict {PACKAGE_PIN AP33} [get_ports ddr4_dq[57]]
|
||||
set_property -dict {PACKAGE_PIN AM34} [get_ports ddr4_dq[58]]
|
||||
set_property -dict {PACKAGE_PIN AP31} [get_ports ddr4_dq[59]]
|
||||
set_property -dict {PACKAGE_PIN AM32} [get_ports ddr4_dq[60]]
|
||||
set_property -dict {PACKAGE_PIN AN31} [get_ports ddr4_dq[61]]
|
||||
set_property -dict {PACKAGE_PIN AL34} [get_ports ddr4_dq[62]]
|
||||
set_property -dict {PACKAGE_PIN AN32} [get_ports ddr4_dq[63]]
|
||||
set_property -dict {PACKAGE_PIN AG21} [get_ports ddr4_dqs_p[0]]
|
||||
set_property -dict {PACKAGE_PIN AH24} [get_ports ddr4_dqs_p[1]]
|
||||
set_property -dict {PACKAGE_PIN AJ20} [get_ports ddr4_dqs_p[2]]
|
||||
set_property -dict {PACKAGE_PIN AP20} [get_ports ddr4_dqs_p[3]]
|
||||
set_property -dict {PACKAGE_PIN AL27} [get_ports ddr4_dqs_p[4]]
|
||||
set_property -dict {PACKAGE_PIN AN29} [get_ports ddr4_dqs_p[5]]
|
||||
set_property -dict {PACKAGE_PIN AH33} [get_ports ddr4_dqs_p[6]]
|
||||
set_property -dict {PACKAGE_PIN AN34} [get_ports ddr4_dqs_p[7]]
|
||||
set_property -dict {PACKAGE_PIN AH21} [get_ports ddr4_dqs_n[0]]
|
||||
set_property -dict {PACKAGE_PIN AJ25} [get_ports ddr4_dqs_n[1]]
|
||||
set_property -dict {PACKAGE_PIN AK20} [get_ports ddr4_dqs_n[2]]
|
||||
set_property -dict {PACKAGE_PIN AP21} [get_ports ddr4_dqs_n[3]]
|
||||
set_property -dict {PACKAGE_PIN AL28} [get_ports ddr4_dqs_n[4]]
|
||||
set_property -dict {PACKAGE_PIN AP30} [get_ports ddr4_dqs_n[5]]
|
||||
set_property -dict {PACKAGE_PIN AJ33} [get_ports ddr4_dqs_n[6]]
|
||||
set_property -dict {PACKAGE_PIN AP34} [get_ports ddr4_dqs_n[7]]
|
||||
set_property -dict {PACKAGE_PIN AJ18} [get_ports ddr4_odt[0]]
|
||||
set_property -dict {PACKAGE_PIN AL18} [get_ports ddr4_reset_n]
|
||||
|
||||
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 44]
|
||||
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 45]
|
||||
set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46]
|
||||
|
||||
set_false_path -to [get_pins -hier -filter {name =~ *axi_ethernet_idelayctrl*/RST}]
|
||||
create_clock -name phy_clk -period 1.60 [get_ports phy_clk_p]
|
||||
|
||||
set_false_path -to [get_pins -hier -filter {name =~ *ethernet*idelayctrl*/RST}]
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
|
|||
|
||||
# audio peripherals
|
||||
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
|
|||
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
|
||||
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
|
||||
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
|
||||
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
|
||||
|
||||
# instance: microblaze- mdm
|
||||
|
|
@ -78,7 +78,7 @@ set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 s
|
|||
|
||||
# instance: ddr (mig)
|
||||
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
|
||||
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
|
||||
file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/"
|
||||
set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
|
|
@ -67,10 +67,12 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
|
|||
create_bd_pin -dir I -from [expr ($data_width-1)] -to 0 dma_data
|
||||
create_bd_pin -dir I dma_xfer_req
|
||||
create_bd_pin -dir I dma_xfer_last
|
||||
create_bd_pin -dir I dac_fifo_bypass
|
||||
|
||||
create_bd_pin -dir I dac_clk
|
||||
create_bd_pin -dir I dac_valid
|
||||
create_bd_pin -dir O -from [expr ($data_width - 1)] -to 0 dac_data
|
||||
create_bd_pin -dir O dac_xfer_out
|
||||
|
||||
set util_dacfifo [create_bd_cell -type ip -vlnv analog.com:user:util_dacfifo:1.0 util_dacfifo]
|
||||
set_property -dict [list CONFIG.DATA_WIDTH $data_width] $util_dacfifo
|
||||
|
|
@ -86,6 +88,8 @@ proc p_sys_dacfifo {p_name m_name data_width addr_width} {
|
|||
ad_connect dma_xfer_last util_dacfifo/dma_xfer_last
|
||||
ad_connect dac_valid util_dacfifo/dac_valid
|
||||
ad_connect dac_data util_dacfifo/dac_data
|
||||
ad_connect dac_xfer_out util_dacfifo/dac_xfer_out
|
||||
ad_connect dac_fifo_bypass util_dacfifo/dac_fifo_bypass
|
||||
|
||||
current_bd_instance $c_instance
|
||||
}
|
||||
|
|
|
|||
|
|
@ -100,7 +100,7 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
|
|||
|
||||
# audio peripherals
|
||||
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
|
|||
|
||||
# audio peripherals
|
||||
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} {
|
|||
create_bd_pin -dir I dma_xfer_req
|
||||
create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
|
||||
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
|
||||
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
|
||||
file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
|
||||
set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
|
|||
|
||||
# audio peripherals
|
||||
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_a
|
|||
|
||||
set axi_ad9250_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_core]
|
||||
|
||||
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9250_jesd]
|
||||
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd
|
||||
|
||||
|
|
|
|||
|
|
@ -37,6 +37,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "212992";
|
||||
value = "229376";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -66,7 +66,7 @@
|
|||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "196608";
|
||||
value = "212992";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
|
|
@ -78,6 +78,54 @@
|
|||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq2.xcvr_core_jesd204_rx_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "254976";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq2.xcvr_core_jesd204_tx_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "253952";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq2.xcvr_core_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "196608";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq2.xcvr_rx_pll_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "251904";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq2.xcvr_tx_lane_pll_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "245760";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq2.xcvr_tx_pll_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "249856";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element sys_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
|
|
@ -313,7 +361,7 @@
|
|||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
<parameter name="device" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="device" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="deviceFamily" value="Arria 10" />
|
||||
<parameter name="deviceSpeedGrade" value="2" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
|
|
@ -418,14 +466,14 @@
|
|||
type="reset"
|
||||
dir="end" />
|
||||
<module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
|
||||
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x34000' end='0x38000' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq2_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq2_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq2_axi_ad9144_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq2_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq2_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq2_axi_ad9144_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq2_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq2_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq2_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq2_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq2_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
|
||||
<parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
|
||||
<parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
|
||||
|
|
@ -445,7 +493,7 @@
|
|||
<parameter
|
||||
name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 29" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
|
|
@ -502,7 +550,7 @@
|
|||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq2.axi_ad9144_dma_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00034000" />
|
||||
<parameter name="baseAddress" value="0x00038000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -520,7 +568,7 @@
|
|||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq2.axi_ad9680_dma_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00030000" />
|
||||
<parameter name="baseAddress" value="0x00034000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
|
|
@ -532,6 +580,60 @@
|
|||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq2.xcvr_core_jesd204_rx_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003e400" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq2.xcvr_core_jesd204_tx_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003e000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq2.xcvr_core_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00030000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq2.xcvr_rx_pll_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003d800" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq2.xcvr_tx_lane_pll_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003c000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq2.xcvr_tx_pll_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003d000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
|
|
|
|||
|
|
@ -15,4 +15,29 @@ set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
|
|||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_tx_csr_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_rx_csr_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_tx_csr_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_rx_csr_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
|
|
|
|||
|
|
@ -76,7 +76,8 @@ module system_top (
|
|||
|
||||
// board gpio
|
||||
|
||||
gpio_bd,
|
||||
gpio_bd_i,
|
||||
gpio_bd_o,
|
||||
|
||||
// lane interface
|
||||
|
||||
|
|
@ -147,7 +148,8 @@ module system_top (
|
|||
|
||||
// board gpio
|
||||
|
||||
inout [ 26:0] gpio_bd;
|
||||
input [ 10:0] gpio_bd_i;
|
||||
output [ 15:0] gpio_bd_o;
|
||||
|
||||
// lane interface
|
||||
|
||||
|
|
@ -187,8 +189,8 @@ module system_top (
|
|||
wire eth_mdio_i;
|
||||
wire eth_mdio_o;
|
||||
wire eth_mdio_t;
|
||||
wire [ 31:0] gpio_i;
|
||||
wire [ 31:0] gpio_o;
|
||||
wire [ 63:0] gpio_i;
|
||||
wire [ 63:0] gpio_o;
|
||||
wire spi_miso_s;
|
||||
wire spi_mosi_s;
|
||||
wire [ 7:0] spi_csn_s;
|
||||
|
|
@ -207,6 +209,20 @@ module system_top (
|
|||
.spi_sdio (spi_sdio),
|
||||
.spi_dir (spi_dir));
|
||||
|
||||
// gpio in & out are separate cores
|
||||
|
||||
assign adc_pd = gpio_o[42];
|
||||
assign dac_txen = gpio_o[41];
|
||||
assign dac_reset = gpio_o[40];
|
||||
assign clkd_sync = gpio_o[38];
|
||||
|
||||
assign gpio_i[63:38] = gpio_o[63:38];
|
||||
assign gpio_i[37:37] = trig;
|
||||
assign gpio_i[36:36] = adc_fdb;
|
||||
assign gpio_i[35:35] = adc_fda;
|
||||
assign gpio_i[34:34] = dac_irq;
|
||||
assign gpio_i[33:32] = clkd_status;
|
||||
|
||||
// board stuff
|
||||
|
||||
assign eth_resetn = ~eth_reset;
|
||||
|
|
@ -216,12 +232,10 @@ module system_top (
|
|||
assign ddr3_a[14:12] = 3'd0;
|
||||
|
||||
assign gpio_i[31:27] = gpio_o[31:27];
|
||||
assign gpio_i[26:16] = gpio_bd_i;
|
||||
assign gpio_i[15: 0] = gpio_o[15:0];
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
|
||||
.dio_t ({11'h7ff, 16'h0}),
|
||||
.dio_i (gpio_o[26:0]),
|
||||
.dio_o (gpio_i[26:0]),
|
||||
.dio_p (gpio_bd));
|
||||
assign gpio_bd_o = gpio_o[15:0];
|
||||
|
||||
system_bd i_system_bd (
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
|
||||
|
|
@ -249,8 +263,8 @@ module system_top (
|
|||
.a10gx_base_sys_ethernet_reset_reset (eth_reset),
|
||||
.a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
|
||||
.a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
|
||||
.a10gx_base_sys_gpio_in_export ({trig, adc_fdb, adc_fda, dac_irq, clkd_status[1], clkd_status[0]}),
|
||||
.a10gx_base_sys_gpio_out_export ({adc_pd, dac_txen, dac_reset, clkd_sync}),
|
||||
.a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
|
||||
.a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
|
||||
.a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||
.a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||
.a10gx_base_sys_spi_MISO (spi_miso_s),
|
||||
|
|
@ -272,3 +286,4 @@ endmodule
|
|||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "9";
|
||||
value = "11";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -21,7 +21,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "14";
|
||||
value = "16";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "12";
|
||||
value = "14";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -53,7 +53,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "11";
|
||||
value = "13";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -69,7 +69,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "8";
|
||||
value = "10";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
|
|
@ -90,7 +90,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "15";
|
||||
value = "17";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -642,7 +642,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "10";
|
||||
value = "12";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -650,7 +650,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "13";
|
||||
value = "15";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -658,7 +658,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "18";
|
||||
value = "20";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -666,7 +666,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "16";
|
||||
value = "18";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -674,7 +674,15 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "7";
|
||||
value = "8";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element xcvr_rx_pll_reconfig
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "9";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -682,7 +690,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "6";
|
||||
value = "7";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -690,7 +698,7 @@
|
|||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "17";
|
||||
value = "19";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
|
|
@ -702,6 +710,14 @@
|
|||
type = "int";
|
||||
}
|
||||
}
|
||||
element xcvr_tx_pll_reconfig
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "6";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element xcvr_tx_ref_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
|
|
@ -713,7 +729,7 @@
|
|||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
<parameter name="device" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="device" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="deviceFamily" value="Arria 10" />
|
||||
<parameter name="deviceSpeedGrade" value="2" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
|
|
@ -821,6 +837,36 @@
|
|||
internal="axi_jesd_xcvr.if_tx_ext_sysref_in"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_core_jesd204_rx_s_avl"
|
||||
internal="xcvr_core.jesd204_rx_avs"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_core_jesd204_tx_s_avl"
|
||||
internal="xcvr_core.jesd204_tx_avs"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_core_reconfig_s_avl"
|
||||
internal="xcvr_core.reconfig_avmm"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_rx_pll_reconfig_s_avl"
|
||||
internal="xcvr_rx_pll_reconfig.mgmt_avalon_slave"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_tx_lane_pll_s_avl"
|
||||
internal="xcvr_tx_lane_pll.reconfig_avmm0"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="xcvr_tx_pll_reconfig_s_avl"
|
||||
internal="xcvr_tx_pll_reconfig.mgmt_avalon_slave"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<module name="ad9680_adcfifo" kind="util_adcfifo" version="1.0" enabled="1">
|
||||
<parameter name="ADC_DATA_WIDTH" value="128" />
|
||||
<parameter name="DMA_ADDRESS_WIDTH" value="16" />
|
||||
|
|
@ -909,7 +955,7 @@
|
|||
<module name="xcvr_core" kind="altera_jesd204" version="15.1" enabled="1">
|
||||
<parameter name="ADJCNT" value="0" />
|
||||
<parameter name="ADJDIR" value="0" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="BID" value="0" />
|
||||
<parameter name="CF" value="0" />
|
||||
|
|
@ -957,14 +1003,14 @@
|
|||
<parameter name="bitrev_en" value="false" />
|
||||
<parameter name="bonded_mode" value="non_bonded" />
|
||||
<parameter name="lane_rate" value="10000.0" />
|
||||
<parameter name="part_trait_bd" value="NIGHTFURY5ES2" />
|
||||
<parameter name="part_trait_dp" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="pll_reconfig_enable" value="false" />
|
||||
<parameter name="part_trait_bd" value="NIGHTFURY5" />
|
||||
<parameter name="part_trait_dp" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="pll_reconfig_enable" value="true" />
|
||||
<parameter name="pll_type" value="CMU" />
|
||||
<parameter name="rcfg_jtag_enable" value="false" />
|
||||
<parameter name="sdc_constraint" value="1.0" />
|
||||
<parameter name="set_capability_reg_enable" value="false" />
|
||||
<parameter name="set_csr_soft_logic_enable" value="false" />
|
||||
<parameter name="set_capability_reg_enable" value="true" />
|
||||
<parameter name="set_csr_soft_logic_enable" value="true" />
|
||||
<parameter name="set_prbs_soft_logic_enable" value="false" />
|
||||
<parameter name="set_user_identifier" value="0" />
|
||||
<parameter name="wrapper_opt" value="base_phy" />
|
||||
|
|
@ -978,19 +1024,19 @@
|
|||
<parameter name="PLLS" value="1" />
|
||||
<parameter name="REDUCED_SIM_TIME" value="1" />
|
||||
<parameter name="RX_ENABLE" value="1" />
|
||||
<parameter name="RX_PER_CHANNEL" value="1" />
|
||||
<parameter name="RX_PER_CHANNEL" value="0" />
|
||||
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
|
||||
<parameter name="SYNCHRONIZE_RESET" value="1" />
|
||||
<parameter name="SYS_CLK_IN_MHZ" value="100" />
|
||||
<parameter name="TX_ENABLE" value="1" />
|
||||
<parameter name="TX_PER_CHANNEL" value="1" />
|
||||
<parameter name="TX_PER_CHANNEL" value="0" />
|
||||
<parameter name="TX_PLL_ENABLE" value="1" />
|
||||
<parameter name="T_PLL_LOCK_HYST" value="0" />
|
||||
<parameter name="T_PLL_POWERDOWN" value="1000" />
|
||||
<parameter name="T_RX_ANALOGRESET" value="40" />
|
||||
<parameter name="T_RX_ANALOGRESET" value="70000" />
|
||||
<parameter name="T_RX_DIGITALRESET" value="4000" />
|
||||
<parameter name="T_TX_ANALOGRESET" value="40" />
|
||||
<parameter name="T_TX_DIGITALRESET" value="4000" />
|
||||
<parameter name="T_TX_ANALOGRESET" value="70000" />
|
||||
<parameter name="T_TX_DIGITALRESET" value="70000" />
|
||||
<parameter name="device_family" value="Arria 10" />
|
||||
<parameter name="gui_pll_cal_busy" value="1" />
|
||||
<parameter name="gui_rx_auto_reset" value="0" />
|
||||
|
|
@ -1174,7 +1220,7 @@
|
|||
<parameter name="gui_en_extclkout_ports" value="false" />
|
||||
<parameter name="gui_en_lvds_ports" value="Disabled" />
|
||||
<parameter name="gui_en_phout_ports" value="false" />
|
||||
<parameter name="gui_en_reconf" value="false" />
|
||||
<parameter name="gui_en_reconf" value="true" />
|
||||
<parameter name="gui_enable_cascade_in" value="false" />
|
||||
<parameter name="gui_enable_cascade_out" value="false" />
|
||||
<parameter name="gui_enable_mif_dps" value="false" />
|
||||
|
|
@ -1275,11 +1321,21 @@
|
|||
<parameter name="gui_use_NDFB_modes" value="false" />
|
||||
<parameter name="gui_use_locked" value="false" />
|
||||
<parameter name="gui_vco_frequency" value="600.0" />
|
||||
<parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="system_info_device_family" value="Arria 10" />
|
||||
<parameter name="system_info_device_speed_grade" value="2" />
|
||||
<parameter name="system_part_trait_speed_grade" value="2" />
|
||||
</module>
|
||||
<module
|
||||
name="xcvr_rx_pll_reconfig"
|
||||
kind="altera_pll_reconfig"
|
||||
version="15.1"
|
||||
enabled="1">
|
||||
<parameter name="ENABLE_BYTEENABLE" value="false" />
|
||||
<parameter name="ENABLE_MIF" value="false" />
|
||||
<parameter name="MIF_FILE_NAME" value="" />
|
||||
<parameter name="device_family" value="Arria 10" />
|
||||
</module>
|
||||
<module
|
||||
name="xcvr_rx_ref_clk"
|
||||
kind="altera_clock_bridge"
|
||||
|
|
@ -1294,15 +1350,15 @@
|
|||
kind="altera_xcvr_atx_pll_a10"
|
||||
version="15.1"
|
||||
enabled="1">
|
||||
<parameter name="base_device" value="NIGHTFURY5ES2" />
|
||||
<parameter name="base_device" value="NIGHTFURY5" />
|
||||
<parameter name="bw_sel" value="medium" />
|
||||
<parameter name="device" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="device" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="device_family" value="Arria 10" />
|
||||
<parameter name="enable_16G_path" value="0" />
|
||||
<parameter name="enable_8G_path" value="1" />
|
||||
<parameter name="enable_analog_resets" value="0" />
|
||||
<parameter name="enable_atx_to_fpll_cascade_out" value="0" />
|
||||
<parameter name="enable_bonding_clks" value="1" />
|
||||
<parameter name="enable_bonding_clks" value="0" />
|
||||
<parameter name="enable_cascade_out" value="0" />
|
||||
<parameter name="enable_debug_ports_parameters" value="0" />
|
||||
<parameter name="enable_fb_comp_bonding" value="0" />
|
||||
|
|
@ -1315,7 +1371,7 @@
|
|||
<parameter name="enable_pcie_clk" value="0" />
|
||||
<parameter name="enable_pld_atx_cal_busy_port" value="1" />
|
||||
<parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
|
||||
<parameter name="enable_pll_reconfig" value="0" />
|
||||
<parameter name="enable_pll_reconfig" value="1" />
|
||||
<parameter name="generate_add_hdl_instance_example" value="0" />
|
||||
<parameter name="generate_docs" value="1" />
|
||||
<parameter name="mcgb_aux_clkin_cnt" value="0" />
|
||||
|
|
@ -1335,7 +1391,7 @@
|
|||
<parameter name="rcfg_param_vals2" value="" />
|
||||
<parameter name="rcfg_profile_cnt" value="2" />
|
||||
<parameter name="rcfg_profile_select" value="1" />
|
||||
<parameter name="rcfg_separate_avmm_busy" value="0" />
|
||||
<parameter name="rcfg_separate_avmm_busy" value="1" />
|
||||
<parameter name="rcfg_sv_file_enable" value="0" />
|
||||
<parameter name="rcfg_txt_file_enable" value="0" />
|
||||
<parameter name="refclk_cnt" value="1" />
|
||||
|
|
@ -1343,16 +1399,16 @@
|
|||
<parameter name="select_manual_config" value="false" />
|
||||
<parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
|
||||
<parameter name="set_auto_reference_clock_frequency" value="500.0" />
|
||||
<parameter name="set_capability_reg_enable" value="0" />
|
||||
<parameter name="set_csr_soft_logic_enable" value="0" />
|
||||
<parameter name="set_fref_clock_frequency" value="100.0" />
|
||||
<parameter name="set_capability_reg_enable" value="1" />
|
||||
<parameter name="set_csr_soft_logic_enable" value="1" />
|
||||
<parameter name="set_fref_clock_frequency" value="156.25" />
|
||||
<parameter name="set_hip_cal_en" value="0" />
|
||||
<parameter name="set_k_counter" value="1" />
|
||||
<parameter name="set_l_cascade_counter" value="4" />
|
||||
<parameter name="set_k_counter" value="2000000000" />
|
||||
<parameter name="set_l_cascade_counter" value="15" />
|
||||
<parameter name="set_l_cascade_predivider" value="1" />
|
||||
<parameter name="set_l_counter" value="4" />
|
||||
<parameter name="set_m_counter" value="50" />
|
||||
<parameter name="set_manual_reference_clock_frequency" value="100.0" />
|
||||
<parameter name="set_l_counter" value="16" />
|
||||
<parameter name="set_m_counter" value="24" />
|
||||
<parameter name="set_manual_reference_clock_frequency" value="200.0" />
|
||||
<parameter name="set_output_clock_frequency" value="5000.0" />
|
||||
<parameter name="set_ref_clk_div" value="1" />
|
||||
<parameter name="set_user_identifier" value="0" />
|
||||
|
|
@ -1537,7 +1593,7 @@
|
|||
<parameter name="gui_en_extclkout_ports" value="false" />
|
||||
<parameter name="gui_en_lvds_ports" value="Disabled" />
|
||||
<parameter name="gui_en_phout_ports" value="false" />
|
||||
<parameter name="gui_en_reconf" value="false" />
|
||||
<parameter name="gui_en_reconf" value="true" />
|
||||
<parameter name="gui_enable_cascade_in" value="false" />
|
||||
<parameter name="gui_enable_cascade_out" value="false" />
|
||||
<parameter name="gui_enable_mif_dps" value="false" />
|
||||
|
|
@ -1638,11 +1694,21 @@
|
|||
<parameter name="gui_use_NDFB_modes" value="false" />
|
||||
<parameter name="gui_use_locked" value="false" />
|
||||
<parameter name="gui_vco_frequency" value="600.0" />
|
||||
<parameter name="system_info_device_component" value="10AX115S3F45I2SGE2" />
|
||||
<parameter name="system_info_device_component" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="system_info_device_family" value="Arria 10" />
|
||||
<parameter name="system_info_device_speed_grade" value="2" />
|
||||
<parameter name="system_part_trait_speed_grade" value="2" />
|
||||
</module>
|
||||
<module
|
||||
name="xcvr_tx_pll_reconfig"
|
||||
kind="altera_pll_reconfig"
|
||||
version="15.1"
|
||||
enabled="1">
|
||||
<parameter name="ENABLE_BYTEENABLE" value="false" />
|
||||
<parameter name="ENABLE_MIF" value="false" />
|
||||
<parameter name="MIF_FILE_NAME" value="" />
|
||||
<parameter name="device_family" value="Arria 10" />
|
||||
</module>
|
||||
<module
|
||||
name="xcvr_tx_ref_clk"
|
||||
kind="altera_clock_bridge"
|
||||
|
|
@ -1699,11 +1765,31 @@
|
|||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_ad9144_dma.m_src_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="xcvr_tx_pll_reconfig.mgmt_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="xcvr_rx_pll_reconfig.mgmt_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="xcvr_tx_ref_clk.out_clk"
|
||||
end="xcvr_tx_lane_pll.pll_refclk0" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="xcvr_core.reconfig_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="xcvr_tx_lane_pll.reconfig_clk0" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
|
|
@ -1995,19 +2081,8 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_jesd_xcvr.if_tx_ready"
|
||||
end="xcvr_rst_cntrl.tx_ready">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rst_cntrl.pll_cal_busy"
|
||||
end="xcvr_tx_lane_pll.pll_cal_busy">
|
||||
start="xcvr_tx_lane_pll.pll_cal_busy"
|
||||
end="xcvr_rst_cntrl.pll_cal_busy">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
|
@ -2028,8 +2103,52 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_tx_lane_pll.pll_powerdown"
|
||||
end="xcvr_rst_cntrl.pll_powerdown">
|
||||
start="xcvr_rst_cntrl.pll_powerdown"
|
||||
end="xcvr_tx_lane_pll.pll_powerdown">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_tx_pll_reconfig.reconfig_from_pll"
|
||||
end="xcvr_tx_pll.reconfig_from_pll">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rx_pll.reconfig_from_pll"
|
||||
end="xcvr_rx_pll_reconfig.reconfig_from_pll">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_tx_pll.reconfig_to_pll"
|
||||
end="xcvr_tx_pll_reconfig.reconfig_to_pll">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rx_pll_reconfig.reconfig_to_pll"
|
||||
end="xcvr_rx_pll.reconfig_to_pll">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
|
@ -2127,8 +2246,19 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rst_cntrl.tx_digitalreset"
|
||||
end="xcvr_core.tx_digitalreset">
|
||||
start="xcvr_core.tx_digitalreset"
|
||||
end="xcvr_rst_cntrl.tx_digitalreset">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="xcvr_rst_cntrl.tx_ready"
|
||||
end="axi_jesd_xcvr.if_tx_ready">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
|
@ -2220,6 +2350,26 @@
|
|||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="axi_ad9144_dma.m_src_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_tx_pll_reconfig.mgmt_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_rx_pll_reconfig.mgmt_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_core.reconfig_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_tx_lane_pll.reconfig_reset0" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
|
|
@ -2230,6 +2380,11 @@
|
|||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_rx_pll.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="xcvr_rst_cntrl.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n
|
|||
set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
|
||||
set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9144_core
|
||||
|
||||
set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9144_jesd]
|
||||
set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9144_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd
|
||||
|
||||
|
|
@ -42,7 +42,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9144_upack
|
|||
|
||||
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
|
||||
|
||||
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd]
|
||||
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
|
||||
|
||||
|
|
@ -142,6 +142,7 @@ ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1
|
|||
ad_connect util_daq2_gt/tx_out_clk axi_ad9144_fifo/dac_clk
|
||||
ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid
|
||||
ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data
|
||||
ad_connect axi_ad9144_upack/dma_xfer_in axi_ad9144_fifo/dac_xfer_out
|
||||
ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk
|
||||
ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst
|
||||
ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk
|
||||
|
|
|
|||
|
|
@ -40,6 +40,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -11,4 +11,16 @@ set_property -dict [list CONFIG.GTH_OR_GTX_N {1}] $axi_daq2_gt
|
|||
set_property -dict [list CONFIG.QPLL0_FBDIV {20}] $axi_daq2_gt
|
||||
set_property -dict [list CONFIG.QPLL0_REFCLK_DIV {1}] $axi_daq2_gt
|
||||
|
||||
set_property -dict [list CONFIG.S00_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
set_property -dict [list CONFIG.S01_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
set_property -dict [list CONFIG.S02_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
set_property -dict [list CONFIG.S03_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
set_property -dict [list CONFIG.S04_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
set_property -dict [list CONFIG.S05_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
set_property -dict [list CONFIG.S06_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
set_property -dict [list CONFIG.S07_HAS_REGSLICE {4}] [get_bd_cells axi_mem_interconnect]
|
||||
|
||||
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] [get_bd_cells axi_ddr_interconnect]
|
||||
set_property -dict [list CONFIG.XBAR_DATA_WIDTH.VALUE_SRC USER] [get_bd_cells axi_ddr_interconnect]
|
||||
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] [get_bd_cells axi_ddr_interconnect]
|
||||
|
||||
|
|
|
|||
|
|
@ -13,9 +13,6 @@ adi_project_files daq2_kcu105 [list \
|
|||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
|
||||
|
||||
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
|
||||
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
|
||||
|
||||
adi_project_run daq2_kcu105
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -46,6 +46,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,139 @@
|
|||
####################################################################################
|
||||
####################################################################################
|
||||
## Copyright 2011(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
|
||||
M_DEPS += system_top.v
|
||||
M_DEPS += system_project.tcl
|
||||
M_DEPS += system_constr.sdc
|
||||
M_DEPS += system_bd.qsys
|
||||
M_DEPS += ../common/daq3_spi.v
|
||||
M_DEPS += ../common/daq3_bd.qsys
|
||||
M_DEPS += ../../scripts/adi_env.tcl
|
||||
M_DEPS += ../../common/a10gx/a10gx_system_bd.qsys
|
||||
M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
|
||||
M_DEPS += ../../../library/common/ad_iobuf.v
|
||||
M_DEPS += ../../../library/axi_ad9152/axi_ad9152.v
|
||||
M_DEPS += ../../../library/axi_ad9152/axi_ad9152_channel.v
|
||||
M_DEPS += ../../../library/axi_ad9152/axi_ad9152_core.v
|
||||
M_DEPS += ../../../library/axi_ad9152/axi_ad9152_hw.tcl
|
||||
M_DEPS += ../../../library/axi_ad9152/axi_ad9152_if.v
|
||||
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
|
||||
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
|
||||
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
|
||||
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
|
||||
M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
|
||||
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
|
||||
M_DEPS += ../../../library/axi_dmac/address_generator.v
|
||||
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
|
||||
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
|
||||
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
|
||||
M_DEPS += ../../../library/axi_dmac/data_mover.v
|
||||
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
|
||||
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
|
||||
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
|
||||
M_DEPS += ../../../library/axi_dmac/inc_id.h
|
||||
M_DEPS += ../../../library/axi_dmac/request_arb.v
|
||||
M_DEPS += ../../../library/axi_dmac/request_generator.v
|
||||
M_DEPS += ../../../library/axi_dmac/resp.h
|
||||
M_DEPS += ../../../library/axi_dmac/response_generator.v
|
||||
M_DEPS += ../../../library/axi_dmac/response_handler.v
|
||||
M_DEPS += ../../../library/axi_dmac/splitter.v
|
||||
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
|
||||
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
|
||||
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
|
||||
M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr.v
|
||||
M_DEPS += ../../../library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
|
||||
M_DEPS += ../../../library/common/ad_datafmt.v
|
||||
M_DEPS += ../../../library/common/ad_dds.v
|
||||
M_DEPS += ../../../library/common/ad_dds_1.v
|
||||
M_DEPS += ../../../library/common/ad_dds_sine.v
|
||||
M_DEPS += ../../../library/common/ad_jesd_align.v
|
||||
M_DEPS += ../../../library/common/ad_mul.v
|
||||
M_DEPS += ../../../library/common/ad_pnmon.v
|
||||
M_DEPS += ../../../library/common/ad_rst.v
|
||||
M_DEPS += ../../../library/common/altera/MULT_MACRO.v
|
||||
M_DEPS += ../../../library/common/sync_bits.v
|
||||
M_DEPS += ../../../library/common/sync_gray.v
|
||||
M_DEPS += ../../../library/common/up_adc_channel.v
|
||||
M_DEPS += ../../../library/common/up_adc_common.v
|
||||
M_DEPS += ../../../library/common/up_axi.v
|
||||
M_DEPS += ../../../library/common/up_clock_mon.v
|
||||
M_DEPS += ../../../library/common/up_dac_channel.v
|
||||
M_DEPS += ../../../library/common/up_dac_common.v
|
||||
M_DEPS += ../../../library/common/up_delay_cntrl.v
|
||||
M_DEPS += ../../../library/common/up_xcvr.v
|
||||
M_DEPS += ../../../library/common/up_xfer_cntrl.v
|
||||
M_DEPS += ../../../library/common/up_xfer_status.v
|
||||
M_DEPS += ../../../library/util_adcfifo/../common/ad_axis_inf_rx.v
|
||||
M_DEPS += ../../../library/util_adcfifo/../common/ad_mem_asym.v
|
||||
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
|
||||
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
|
||||
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
|
||||
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
|
||||
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
|
||||
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
|
||||
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
|
||||
M_DEPS += ../../../library/util_cpack/util_cpack.v
|
||||
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
|
||||
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
|
||||
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
|
||||
M_DEPS += ../../../library/util_upack/util_upack.v
|
||||
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
|
||||
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
|
||||
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
|
||||
|
||||
|
||||
M_ALTERA := quartus_sh --64bit -t
|
||||
|
||||
|
||||
M_FLIST += *.log
|
||||
M_FLIST += *_INFO.txt
|
||||
M_FLIST += *_dump.txt
|
||||
M_FLIST += db
|
||||
M_FLIST += *.asm.rpt
|
||||
M_FLIST += *.done
|
||||
M_FLIST += *.eda.rpt
|
||||
M_FLIST += *.fit.*
|
||||
M_FLIST += *.map.*
|
||||
M_FLIST += *.sta.*
|
||||
M_FLIST += *.qsf
|
||||
M_FLIST += *.qpf
|
||||
M_FLIST += *.qws
|
||||
M_FLIST += *.sof
|
||||
M_FLIST += *.cdf
|
||||
M_FLIST += *.sld
|
||||
M_FLIST += *.qdf
|
||||
M_FLIST += hc_output
|
||||
M_FLIST += system_bd
|
||||
M_FLIST += hps_isw_handoff
|
||||
M_FLIST += hps_sdram_*.csv
|
||||
M_FLIST += *ddr3_*.csv
|
||||
M_FLIST += incremental_db
|
||||
M_FLIST += reconfig_mif
|
||||
M_FLIST += *.sopcinfo
|
||||
M_FLIST += *.jdi
|
||||
M_FLIST += *.pin
|
||||
|
||||
|
||||
|
||||
.PHONY: all clean clean-all
|
||||
all: daq3_a10gx.sof
|
||||
|
||||
|
||||
|
||||
clean:clean-all
|
||||
|
||||
|
||||
clean-all:
|
||||
rm -rf $(M_FLIST)
|
||||
|
||||
|
||||
daq3_a10gx.sof: $(M_DEPS)
|
||||
rm -rf $(M_FLIST)
|
||||
$(M_ALTERA) system_project.tcl >> daq3_a10gx_quartus.log 2>&1
|
||||
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
|
|
@ -0,0 +1,680 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags=""
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element a10gx_base
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "1";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element a10gx_base.sys_mem_s_avl
|
||||
{
|
||||
datum _lockedAddress
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
datum baseAddress
|
||||
{
|
||||
value = "0";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "2";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element daq3.axi_ad9152_core_s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "131072";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.axi_ad9152_dma_s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "229376";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.axi_ad9680_core_s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "65536";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.axi_ad9680_dma_s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "212992";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.axi_jesd_xcvr_s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "0";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_core_jesd204_rx_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "254976";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_core_jesd204_tx_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "253952";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_core_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "196608";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_rx_pll_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "251904";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_tx_lane_pll_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "245760";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element daq3.xcvr_tx_pll_reconfig_s_avl
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "249856";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element sys_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria 10";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
<parameter name="device" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="deviceFamily" value="Arria 10" />
|
||||
<parameter name="deviceSpeedGrade" value="2" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="false" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="2" />
|
||||
<parameter name="projectName" value="daq3_a10gx.qpf" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface
|
||||
name="a10gx_base_sys_ddr3_cntrl_mem"
|
||||
internal="a10gx_base.sys_ddr3_cntrl_mem"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="a10gx_base_sys_ddr3_cntrl_oct"
|
||||
internal="a10gx_base.sys_ddr3_cntrl_oct"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="a10gx_base_sys_ddr3_cntrl_pll_ref_clk"
|
||||
internal="a10gx_base.sys_ddr3_cntrl_pll_ref_clk"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="a10gx_base_sys_ethernet_mdio"
|
||||
internal="a10gx_base.sys_ethernet_mdio"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="a10gx_base_sys_ethernet_ref_clk"
|
||||
internal="a10gx_base.sys_ethernet_ref_clk"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="a10gx_base_sys_ethernet_reset"
|
||||
internal="a10gx_base.sys_ethernet_reset"
|
||||
type="reset"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="a10gx_base_sys_ethernet_sgmii"
|
||||
internal="a10gx_base.sys_ethernet_sgmii"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="a10gx_base_sys_gpio" internal="a10gx_base.sys_gpio" />
|
||||
<interface
|
||||
name="a10gx_base_sys_gpio_bd"
|
||||
internal="a10gx_base.sys_gpio_bd"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="a10gx_base_sys_gpio_in"
|
||||
internal="a10gx_base.sys_gpio_in"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="a10gx_base_sys_gpio_out"
|
||||
internal="a10gx_base.sys_gpio_out"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="a10gx_base_sys_spi"
|
||||
internal="a10gx_base.sys_spi"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="daq3_rx_data" internal="daq3.rx_data" type="conduit" dir="end" />
|
||||
<interface
|
||||
name="daq3_rx_ref_clk"
|
||||
internal="daq3.rx_ref_clk"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface name="daq3_rx_sync" internal="daq3.rx_sync" type="conduit" dir="end" />
|
||||
<interface
|
||||
name="daq3_rx_sysref"
|
||||
internal="daq3.rx_sysref"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="daq3_tx_data" internal="daq3.tx_data" type="conduit" dir="end" />
|
||||
<interface
|
||||
name="daq3_tx_ref_clk"
|
||||
internal="daq3.tx_ref_clk"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface name="daq3_tx_sync" internal="daq3.tx_sync" type="conduit" dir="end" />
|
||||
<interface
|
||||
name="daq3_tx_sysref"
|
||||
internal="daq3.tx_sysref"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
|
||||
<interface
|
||||
name="sys_reset"
|
||||
internal="sys_clk.clk_in_reset"
|
||||
type="reset"
|
||||
dir="end" />
|
||||
<module name="a10gx_base" kind="a10gx_system_bd" version="1.0" enabled="1">
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
|
||||
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='daq3_axi_jesd_xcvr.s_axi' start='0x0' end='0x10000' /><slave name='daq3_axi_ad9680_core.s_axi' start='0x10000' end='0x20000' /><slave name='daq3_axi_ad9152_core.s_axi' start='0x20000' end='0x30000' /><slave name='daq3_xcvr_core.reconfig_avmm' start='0x30000' end='0x34000' /><slave name='daq3_axi_ad9680_dma.s_axi' start='0x34000' end='0x38000' /><slave name='daq3_axi_ad9152_dma.s_axi' start='0x38000' end='0x3C000' /><slave name='daq3_xcvr_tx_lane_pll.reconfig_avmm0' start='0x3C000' end='0x3D000' /><slave name='daq3_xcvr_tx_pll_reconfig.mgmt_avalon_slave' start='0x3D000' end='0x3D800' /><slave name='daq3_xcvr_rx_pll_reconfig.mgmt_avalon_slave' start='0x3D800' end='0x3E000' /><slave name='daq3_xcvr_core.jesd204_tx_avs' start='0x3E000' end='0x3E400' /><slave name='daq3_xcvr_core.jesd204_rx_avs' start='0x3E400' end='0x3E800' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 18" />
|
||||
<parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_DOMAIN" value="1" />
|
||||
<parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_CLOCK_RATE" value="0" />
|
||||
<parameter name="AUTO_SYS_DDR3_CNTRL_PLL_REF_CLK_RESET_DOMAIN" value="1" />
|
||||
<parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_DOMAIN" value="2" />
|
||||
<parameter name="AUTO_SYS_ETHERNET_REF_CLK_CLOCK_RATE" value="0" />
|
||||
<parameter name="AUTO_SYS_ETHERNET_REF_CLK_RESET_DOMAIN" value="2" />
|
||||
<parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="3" />
|
||||
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_a10gx_base</parameter>
|
||||
</module>
|
||||
<module name="daq3" kind="daq3_bd" version="1.0" enabled="1">
|
||||
<parameter name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
|
||||
<parameter
|
||||
name="AUTO_AXI_AD9152_DMA_M_AXI_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 29" />
|
||||
<parameter name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10gx_base_sys_ddr3_cntrl_arch.ctrl_amm_0' start='0x0' end='0x10000000' /></address-map>]]></parameter>
|
||||
<parameter
|
||||
name="AUTO_AXI_AD9680_DMA_M_AXI_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 29" />
|
||||
<parameter name="AUTO_DEVICE" value="10AX115S3F45E2SGE3" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="8" />
|
||||
<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="133333250" />
|
||||
<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="8" />
|
||||
<parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
|
||||
<parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
|
||||
<parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
|
||||
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_TX_REF_CLK_CLOCK_DOMAIN" value="5" />
|
||||
<parameter name="AUTO_TX_REF_CLK_CLOCK_RATE" value="0" />
|
||||
<parameter name="AUTO_TX_REF_CLK_RESET_DOMAIN" value="5" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_daq3" />
|
||||
</module>
|
||||
<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
|
||||
<parameter name="clockFrequency" value="100000000" />
|
||||
<parameter name="clockFrequencyKnown" value="true" />
|
||||
<parameter name="inputClockFrequency" value="0" />
|
||||
<parameter name="resetSynchronousEdges" value="NONE" />
|
||||
</module>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="daq3.axi_ad9152_dma_m_axi"
|
||||
end="a10gx_base.sys_mem_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="daq3.axi_ad9680_dma_m_axi"
|
||||
end="a10gx_base.sys_mem_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_ad9152_core_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00020000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_ad9152_dma_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00038000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_ad9680_core_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00010000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_ad9680_dma_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00034000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.axi_jesd_xcvr_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_core_jesd204_rx_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003e400" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_core_jesd204_tx_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003e000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_core_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00030000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_rx_pll_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003d800" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_tx_lane_pll_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003c000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_cpu_m_avl"
|
||||
end="daq3.xcvr_tx_pll_reconfig_s_avl">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0003d000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.clk"
|
||||
end="a10gx_base.sys_clk" />
|
||||
<connection kind="clock" version="15.1" start="sys_clk.clk" end="daq3.sys_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="a10gx_base.mem_clk"
|
||||
end="daq3.mem_clk" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_intr"
|
||||
end="daq3.axi_ad9152_dma_intr">
|
||||
<parameter name="irqNumber" value="1" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.1"
|
||||
start="a10gx_base.sys_intr"
|
||||
end="daq3.axi_ad9680_dma_intr">
|
||||
<parameter name="irqNumber" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_clk.clk_reset"
|
||||
end="a10gx_base.sys_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_clk.clk_reset"
|
||||
end="daq3.sys_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="a10gx_base.mem_rst"
|
||||
end="daq3.mem_rst" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
</system>
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
|
||||
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
|
||||
create_clock -period "2.000 ns" -name rx_ref_clk_500mhz [get_ports {rx_ref_clk}]
|
||||
create_clock -period "2.000 ns" -name tx_ref_clk_500mhz [get_ports {tx_ref_clk}]
|
||||
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
|
||||
i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_tx_csr_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {sys_clk_100mhz}]\
|
||||
-through [get_nets *altera_jesd204_rx_csr_inst*]\
|
||||
-to [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_tx_csr_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_tx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_tx_ctl_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
set_false_path -from [get_clocks {i_system_bd|daq3|xcvr_rx_pll|outclk0}]\
|
||||
-through [get_nets *altera_jesd204_rx_csr_inst*]\
|
||||
-to [get_clocks {sys_clk_100mhz}]
|
||||
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
|
||||
load_package flow
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
project_new daq3_a10gx -overwrite
|
||||
|
||||
source "../../common/a10gx/a10gx_system_assign.tcl"
|
||||
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*"
|
||||
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*"
|
||||
set_global_assignment -name QSYS_FILE system_bd.qsys
|
||||
|
||||
set_global_assignment -name VERILOG_FILE ../common/daq3_spi.v
|
||||
set_global_assignment -name VERILOG_FILE system_top.v
|
||||
|
||||
set_global_assignment -name SDC_FILE system_constr.sdc
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY system_top
|
||||
|
||||
# lane interface
|
||||
|
||||
set_location_assignment PIN_AJ8 -to rx_ref_clk ; ## B20 FMCA_GBTCLK1_M2C_P
|
||||
set_location_assignment PIN_AJ7 -to "rx_ref_clk(n)" ; ## B21 FMCA_GBTCLK1_M2C_N
|
||||
set_location_assignment PIN_AV5 -to rx_data[0] ; ## A10 FMCA_DP3_M2C_P
|
||||
set_location_assignment PIN_AV6 -to "rx_data[0](n)" ; ## A11 FMCA_DP3_M2C_N
|
||||
set_location_assignment PIN_AW7 -to rx_data[1] ; ## C06 FMCA_DP0_M2C_P
|
||||
set_location_assignment PIN_AW8 -to "rx_data[1](n)" ; ## C07 FMCA_DP0_M2C_N
|
||||
set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_DP2_M2C_P
|
||||
set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_DP2_M2C_N
|
||||
set_location_assignment PIN_BA7 -to rx_data[3] ; ## A02 FMCA_DP1_M2C_P
|
||||
set_location_assignment PIN_BA8 -to "rx_data[3](n)" ; ## A03 FMCA_DP1_M2C_N
|
||||
set_location_assignment PIN_AT10 -to rx_sync ; ## D08 FMCA_LA01_CC_P
|
||||
set_location_assignment PIN_AR11 -to "rx_sync(n)" ; ## D09 FMCA_LA01_CC_N
|
||||
set_location_assignment PIN_AR20 -to rx_sysref ; ## G09 FMCA_LA03_P
|
||||
set_location_assignment PIN_AR19 -to "rx_sysref(n)" ; ## G10 FMCA_LA03_N
|
||||
set_location_assignment PIN_AL8 -to tx_ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P
|
||||
set_location_assignment PIN_AL7 -to "tx_ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N
|
||||
set_location_assignment PIN_BC3 -to tx_data[0] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[0])
|
||||
set_location_assignment PIN_BC4 -to "tx_data[0](n)" ; ## A31 FMCA_DP3_C2M_N (tx_data_n[0])
|
||||
set_location_assignment PIN_BC7 -to tx_data[1] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[3])
|
||||
set_location_assignment PIN_BC8 -to "tx_data[1](n)" ; ## C03 FMCA_DP0_C2M_N (tx_data_n[3])
|
||||
set_location_assignment PIN_BB5 -to tx_data[2] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1])
|
||||
set_location_assignment PIN_BB6 -to "tx_data[2](n)" ; ## A27 FMCA_DP2_C2M_N (tx_data_n[1])
|
||||
set_location_assignment PIN_BD5 -to tx_data[3] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[2])
|
||||
set_location_assignment PIN_BD6 -to "tx_data[3](n)" ; ## A23 FMCA_DP1_C2M_N (tx_data_n[2])
|
||||
set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_LA02_P
|
||||
set_location_assignment PIN_AT22 -to "tx_sync(n)" ; ## H08 FMCA_LA02_N
|
||||
set_location_assignment PIN_AN20 -to tx_sysref ; ## H10 FMCA_LA04_P
|
||||
set_location_assignment PIN_AP19 -to "tx_sysref(n)" ; ## H11 FMCA_LA04_N
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
|
||||
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
|
||||
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
|
||||
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
|
||||
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref
|
||||
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
|
||||
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
|
||||
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
|
||||
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
|
||||
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
|
||||
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
|
||||
|
||||
# gpio
|
||||
|
||||
set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P
|
||||
set_location_assignment PIN_AU17 -to "trig(n)" ; ## H14 FMCA_LA07_N
|
||||
set_location_assignment PIN_AR14 -to adc_fdb ; ## H17 FMCA_LA11_N
|
||||
set_location_assignment PIN_AT14 -to adc_fda ; ## H16 FMCA_LA11_P
|
||||
set_location_assignment PIN_AR16 -to dac_irq ; ## G15 FMCA_LA12_P
|
||||
set_location_assignment PIN_AN19 -to clkd_status[1] ; ## G13 FMCA_LA08_N
|
||||
set_location_assignment PIN_AP18 -to clkd_status[0] ; ## G12 FMCA_LA08_P
|
||||
set_location_assignment PIN_AV14 -to adc_pd ; ## C10 FMCA_LA06_P
|
||||
set_location_assignment PIN_AP16 -to dac_txen ; ## G16 FMCA_LA12_N
|
||||
set_location_assignment PIN_AR17 -to sysref ; ## D17 FMCA_LA13_P
|
||||
set_location_assignment PIN_AP17 -to "sysref(n)" ; ## D18 FMCA_LA13_N
|
||||
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to trig
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to sysref
|
||||
|
||||
# spi
|
||||
|
||||
set_location_assignment PIN_AV11 -to spi_csn_clk ; ## D11 FMCA_LA05_P
|
||||
set_location_assignment PIN_AR15 -to spi_csn_dac ; ## C14 FMCA_LA10_P
|
||||
set_location_assignment PIN_AV13 -to spi_csn_adc ; ## D15 FMCA_LA09_N
|
||||
set_location_assignment PIN_AW11 -to spi_clk ; ## D12 FMCA_LA05_N
|
||||
set_location_assignment PIN_AW13 -to spi_sdio ; ## D14 FMCA_LA09_P
|
||||
set_location_assignment PIN_AW14 -to spi_dir ; ## C11 FMCA_LA06_N
|
||||
|
||||
execute_flow -compile
|
||||
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
// clock and resets
|
||||
|
||||
sys_clk,
|
||||
sys_resetn,
|
||||
|
||||
// ddr3
|
||||
|
||||
ddr3_clk_p,
|
||||
ddr3_clk_n,
|
||||
ddr3_a,
|
||||
ddr3_ba,
|
||||
ddr3_cke,
|
||||
ddr3_cs_n,
|
||||
ddr3_odt,
|
||||
ddr3_reset_n,
|
||||
ddr3_we_n,
|
||||
ddr3_ras_n,
|
||||
ddr3_cas_n,
|
||||
ddr3_dqs_p,
|
||||
ddr3_dqs_n,
|
||||
ddr3_dq,
|
||||
ddr3_dm,
|
||||
ddr3_rzq,
|
||||
ddr3_ref_clk,
|
||||
|
||||
// ethernet
|
||||
|
||||
eth_ref_clk,
|
||||
eth_rxd,
|
||||
eth_txd,
|
||||
eth_mdc,
|
||||
eth_mdio,
|
||||
eth_resetn,
|
||||
eth_intn,
|
||||
|
||||
// board gpio
|
||||
|
||||
gpio_bd_i,
|
||||
gpio_bd_o,
|
||||
|
||||
// lane interface
|
||||
|
||||
rx_ref_clk,
|
||||
rx_sysref,
|
||||
rx_sync,
|
||||
rx_data,
|
||||
tx_ref_clk,
|
||||
tx_sysref,
|
||||
tx_sync,
|
||||
tx_data,
|
||||
|
||||
// gpio
|
||||
|
||||
trig,
|
||||
adc_fdb,
|
||||
adc_fda,
|
||||
dac_irq,
|
||||
clkd_status,
|
||||
adc_pd,
|
||||
dac_txen,
|
||||
sysref,
|
||||
|
||||
// spi
|
||||
|
||||
spi_csn_clk,
|
||||
spi_csn_dac,
|
||||
spi_csn_adc,
|
||||
spi_clk,
|
||||
spi_sdio,
|
||||
spi_dir);
|
||||
|
||||
// clock and resets
|
||||
|
||||
input sys_clk;
|
||||
input sys_resetn;
|
||||
|
||||
// ddr3
|
||||
|
||||
output ddr3_clk_p;
|
||||
output ddr3_clk_n;
|
||||
output [ 14:0] ddr3_a;
|
||||
output [ 2:0] ddr3_ba;
|
||||
output ddr3_cke;
|
||||
output ddr3_cs_n;
|
||||
output ddr3_odt;
|
||||
output ddr3_reset_n;
|
||||
output ddr3_we_n;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_cas_n;
|
||||
inout [ 7:0] ddr3_dqs_p;
|
||||
inout [ 7:0] ddr3_dqs_n;
|
||||
inout [ 63:0] ddr3_dq;
|
||||
output [ 7:0] ddr3_dm;
|
||||
input ddr3_rzq;
|
||||
input ddr3_ref_clk;
|
||||
|
||||
// ethernet
|
||||
|
||||
input eth_ref_clk;
|
||||
input eth_rxd;
|
||||
output eth_txd;
|
||||
output eth_mdc;
|
||||
inout eth_mdio;
|
||||
output eth_resetn;
|
||||
input eth_intn;
|
||||
|
||||
// board gpio
|
||||
|
||||
inout [ 10:0] gpio_bd_i;
|
||||
inout [ 15:0] gpio_bd_o;
|
||||
|
||||
// lane interface
|
||||
|
||||
input rx_ref_clk;
|
||||
input rx_sysref;
|
||||
output rx_sync;
|
||||
input [ 3:0] rx_data;
|
||||
input tx_ref_clk;
|
||||
input tx_sysref;
|
||||
input tx_sync;
|
||||
output [ 3:0] tx_data;
|
||||
|
||||
// gpio
|
||||
|
||||
input trig;
|
||||
input adc_fdb;
|
||||
input adc_fda;
|
||||
input dac_irq;
|
||||
input [ 1:0] clkd_status;
|
||||
output adc_pd;
|
||||
output dac_txen;
|
||||
output sysref;
|
||||
|
||||
// spi
|
||||
|
||||
output spi_csn_clk;
|
||||
output spi_csn_dac;
|
||||
output spi_csn_adc;
|
||||
output spi_clk;
|
||||
inout spi_sdio;
|
||||
output spi_dir;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire eth_reset;
|
||||
wire eth_mdio_i;
|
||||
wire eth_mdio_o;
|
||||
wire eth_mdio_t;
|
||||
wire [ 63:0] gpio_i;
|
||||
wire [ 63:0] gpio_o;
|
||||
wire spi_miso_s;
|
||||
wire spi_mosi_s;
|
||||
wire [ 7:0] spi_csn_s;
|
||||
|
||||
// daq3
|
||||
|
||||
assign spi_csn_adc = spi_csn_s[2];
|
||||
assign spi_csn_dac = spi_csn_s[1];
|
||||
assign spi_csn_clk = spi_csn_s[0];
|
||||
|
||||
daq3_spi i_daq3_spi (
|
||||
.spi_csn (spi_csn_s[2:0]),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi_s),
|
||||
.spi_miso (spi_miso_s),
|
||||
.spi_sdio (spi_sdio),
|
||||
.spi_dir (spi_dir));
|
||||
|
||||
// gpio in & out are separate cores
|
||||
|
||||
assign sysref = gpio_o[36];
|
||||
assign adc_pd = gpio_o[35];
|
||||
assign dac_txen = gpio_o[34];
|
||||
|
||||
assign gpio_i[63:38] = 26'd0;
|
||||
assign gpio_i[37:37] = trig;
|
||||
assign gpio_i[36:36] = adc_fdb;
|
||||
assign gpio_i[35:35] = adc_fda;
|
||||
assign gpio_i[34:34] = dac_irq;
|
||||
assign gpio_i[33:32] = clkd_status;
|
||||
|
||||
// board stuff
|
||||
|
||||
assign eth_resetn = ~eth_reset;
|
||||
assign eth_mdio_i = eth_mdio;
|
||||
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
|
||||
|
||||
assign ddr3_a[14:12] = 3'd0;
|
||||
|
||||
assign gpio_i[31:27] = gpio_o[31:27];
|
||||
assign gpio_i[26:16] = gpio_bd_i;
|
||||
assign gpio_i[15: 0] = gpio_o[15:0];
|
||||
|
||||
assign gpio_bd_o = gpio_o[15:0];
|
||||
|
||||
system_bd i_system_bd (
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
|
||||
.a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
|
||||
.a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
|
||||
.a10gx_base_sys_ethernet_mdio_mdc (eth_mdc),
|
||||
.a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
|
||||
.a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
|
||||
.a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
|
||||
.a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk),
|
||||
.a10gx_base_sys_ethernet_reset_reset (eth_reset),
|
||||
.a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd),
|
||||
.a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd),
|
||||
.a10gx_base_sys_gpio_in_export (gpio_i[63:32]),
|
||||
.a10gx_base_sys_gpio_out_export (gpio_o[63:32]),
|
||||
.a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||
.a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||
.a10gx_base_sys_spi_MISO (spi_miso_s),
|
||||
.a10gx_base_sys_spi_MOSI (spi_mosi_s),
|
||||
.a10gx_base_sys_spi_SCLK (spi_clk),
|
||||
.a10gx_base_sys_spi_SS_n (spi_csn_s),
|
||||
.daq3_rx_data_rx_serial_data (rx_data),
|
||||
.daq3_rx_ref_clk_clk (rx_ref_clk),
|
||||
.daq3_rx_sync_rx_sync (rx_sync),
|
||||
.daq3_rx_sysref_rx_ext_sysref_in (rx_sysref),
|
||||
.daq3_tx_data_tx_serial_data (tx_data),
|
||||
.daq3_tx_ref_clk_clk (tx_ref_clk),
|
||||
.daq3_tx_sync_tx_sync (tx_sync),
|
||||
.daq3_tx_sysref_tx_ext_sysref_in (tx_sysref),
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_reset_reset_n (sys_resetn));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -17,7 +17,7 @@ create_bd_port -dir O -from 3 -to 0 tx_data_n
|
|||
|
||||
set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
|
||||
|
||||
set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9152_jesd]
|
||||
set axi_ad9152_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9152_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9152_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd
|
||||
|
||||
|
|
@ -41,7 +41,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9152_upack
|
|||
|
||||
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
|
||||
|
||||
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd]
|
||||
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
|
||||
|
||||
|
|
|
|||
|
|
@ -98,13 +98,11 @@ module daq3_spi (
|
|||
end
|
||||
end
|
||||
|
||||
// io butter
|
||||
// io buffer
|
||||
|
||||
assign spi_miso = spi_sdio;
|
||||
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
|
||||
|
||||
IOBUF i_iobuf_sdio (
|
||||
.T (spi_enable_s),
|
||||
.I (spi_mosi),
|
||||
.O (spi_miso),
|
||||
.IO (spi_sdio));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -47,6 +47,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $mfifo_adc
|
|||
set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
|
||||
set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
|
||||
|
||||
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
|
||||
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
|
||||
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ create_bd_port -dir I -from 7 -to 0 rx_data_n
|
|||
|
||||
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
|
||||
|
||||
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_jesd]
|
||||
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
|
||||
|
||||
|
|
|
|||
|
|
@ -37,6 +37,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0
|
|||
set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1]
|
||||
set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1
|
||||
|
||||
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd]
|
||||
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9680_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc
|
|||
set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc
|
||||
set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc
|
||||
|
||||
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
|
||||
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
|
||||
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
|
|||
set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
|
||||
set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
|
||||
|
||||
set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_0_jesd]
|
||||
set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_0_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
|
||||
set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_1_jesd]
|
||||
set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9625_1_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
|
||||
|
||||
|
|
|
|||
|
|
@ -41,6 +41,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {1}] $mfifo_adc
|
|||
set_property -dict [list CONFIG.DIN_DATA_WIDTH {512}] $mfifo_adc
|
||||
set_property -dict [list CONFIG.ADDRESS_WIDTH {6}] $mfifo_adc
|
||||
|
||||
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_adc]
|
||||
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
|
||||
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
|
||||
|
|
|
|||
|
|
@ -9,14 +9,6 @@
|
|||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element $${FILENAME}
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Arria V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element a5soc_base
|
||||
{
|
||||
datum _sortIndex
|
||||
|
|
@ -195,6 +187,9 @@
|
|||
<parameter name="AUTO_AXI_DMAC_0_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 32" />
|
||||
<parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a5soc_base_sys_hps_axi_sdram.axi_slave0' start='0x0' end='0x80000000' /><slave name='a5soc_base_sys_hps_gmac0.axi_slave0' start='0xFF700000' end='0xFF702000' /><slave name='a5soc_base_sys_hps_gmac1.axi_slave0' start='0xFF702000' end='0xFF704000' /><slave name='a5soc_base_sys_hps_sdmmc.axi_slave0' start='0xFF704000' end='0xFF705000' /><slave name='a5soc_base_sys_hps_qspi.axi_slave0' start='0xFF705000' end='0xFF705100' /><slave name='a5soc_base_sys_hps_fpgamgr.axi_slave0' start='0xFF706000' end='0xFF707000' /><slave name='a5soc_base_sys_hps_gpio0.axi_slave0' start='0xFF708000' end='0xFF708100' /><slave name='a5soc_base_sys_hps_gpio1.axi_slave0' start='0xFF709000' end='0xFF709100' /><slave name='a5soc_base_sys_hps_gpio2.axi_slave0' start='0xFF70A000' end='0xFF70A100' /><slave name='a5soc_base_sys_hps_l3regs.axi_slave0' start='0xFF800000' end='0xFF801000' /><slave name='a5soc_base_sys_hps_nand0.axi_slave0' start='0xFF900000' end='0xFF910000' /><slave name='a5soc_base_sys_hps_qspi.axi_slave1' start='0xFFA00000' end='0xFFA00100' /><slave name='a5soc_base_sys_hps_usb0.axi_slave0' start='0xFFB00000' end='0xFFB40000' /><slave name='a5soc_base_sys_hps_usb1.axi_slave0' start='0xFFB40000' end='0xFFB80000' /><slave name='a5soc_base_sys_hps_nand0.axi_slave1' start='0xFFB80000' end='0xFFB90000' /><slave name='a5soc_base_sys_hps_fpgamgr.axi_slave1' start='0xFFB90000' end='0xFFB90100' /><slave name='a5soc_base_sys_hps_dcan0.axi_slave0' start='0xFFC00000' end='0xFFC01000' /><slave name='a5soc_base_sys_hps_dcan1.axi_slave0' start='0xFFC01000' end='0xFFC02000' /><slave name='a5soc_base_sys_hps_uart0.axi_slave0' start='0xFFC02000' end='0xFFC02100' /><slave name='a5soc_base_sys_hps_uart1.axi_slave0' start='0xFFC03000' end='0xFFC03100' /><slave name='a5soc_base_sys_hps_i2c0.axi_slave0' start='0xFFC04000' end='0xFFC04100' /><slave name='a5soc_base_sys_hps_i2c1.axi_slave0' start='0xFFC05000' end='0xFFC05100' /><slave name='a5soc_base_sys_hps_i2c2.axi_slave0' start='0xFFC06000' end='0xFFC06100' /><slave name='a5soc_base_sys_hps_i2c3.axi_slave0' start='0xFFC07000' end='0xFFC07100' /><slave name='a5soc_base_sys_hps_timer0.axi_slave0' start='0xFFC08000' end='0xFFC08100' /><slave name='a5soc_base_sys_hps_timer1.axi_slave0' start='0xFFC09000' end='0xFFC09100' /><slave name='a5soc_base_sys_hps_sdrctl.axi_slave0' start='0xFFC25000' end='0xFFC26000' /><slave name='a5soc_base_sys_hps_timer2.axi_slave0' start='0xFFD00000' end='0xFFD00100' /><slave name='a5soc_base_sys_hps_timer3.axi_slave0' start='0xFFD01000' end='0xFFD01100' /><slave name='a5soc_base_sys_hps_clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' /><slave name='a5soc_base_sys_hps_rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD05100' /><slave name='a5soc_base_sys_hps_sysmgr.axi_slave0' start='0xFFD08000' end='0xFFD08400' /><slave name='a5soc_base_sys_hps_dma.axi_slave0' start='0xFFE01000' end='0xFFE02000' /><slave name='a5soc_base_sys_hps_spim0.axi_slave0' start='0xFFF00000' end='0xFFF00100' /><slave name='a5soc_base_sys_hps_spim1.axi_slave0' start='0xFFF01000' end='0xFFF01100' /><slave name='a5soc_base_sys_hps_arm_gic_0.axi_slave1' start='0xFFFEC100' end='0xFFFEC200' /><slave name='a5soc_base_sys_hps_timer.axi_slave0' start='0xFFFEC600' end='0xFFFEC700' /><slave name='a5soc_base_sys_hps_arm_gic_0.axi_slave0' start='0xFFFED000' end='0xFFFEE000' /><slave name='a5soc_base_sys_hps_L2.axi_slave0' start='0xFFFEF000' end='0xFFFF0000' /><slave name='a5soc_base_sys_hps_axi_ocram.axi_slave0' start='0xFFFF0000' end='0x100000000' /></address-map>]]></parameter>
|
||||
<parameter name="AUTO_AXI_DMAC_1_M_AXI_ADDRESS_WIDTH" value="AddressWidth = 32" />
|
||||
<parameter name="AUTO_CPU_CLK_CLOCK_DOMAIN" value="5" />
|
||||
<parameter name="AUTO_CPU_CLK_CLOCK_RATE" value="50000000" />
|
||||
<parameter name="AUTO_CPU_CLK_RESET_DOMAIN" value="5" />
|
||||
<parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="3_H3" />
|
||||
|
|
@ -205,14 +200,11 @@
|
|||
<parameter name="AUTO_RX_REF_CLK_CLOCK_DOMAIN" value="4" />
|
||||
<parameter name="AUTO_RX_REF_CLK_CLOCK_RATE" value="0" />
|
||||
<parameter name="AUTO_RX_REF_CLK_RESET_DOMAIN" value="4" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
|
||||
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
|
||||
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcjesdadc1</parameter>
|
||||
</module>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="fmcjesdadc1.axi_dmac_0_m_axi"
|
||||
end="a5soc_base.sys_hps_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
|
@ -221,7 +213,7 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="fmcjesdadc1.axi_dmac_1_m_axi"
|
||||
end="a5soc_base.sys_hps_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
|
@ -230,7 +222,7 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_cpu_interconnect_m0"
|
||||
end="fmcjesdadc1.axi_ad9250_0_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
|
@ -239,7 +231,7 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_cpu_interconnect_m0"
|
||||
end="fmcjesdadc1.axi_ad9250_1_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
|
@ -248,7 +240,7 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_cpu_interconnect_m0"
|
||||
end="fmcjesdadc1.axi_dmac_0_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
|
@ -257,7 +249,7 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_cpu_interconnect_m0"
|
||||
end="fmcjesdadc1.axi_dmac_1_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
|
@ -266,7 +258,7 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_cpu_interconnect_m0"
|
||||
end="fmcjesdadc1.axi_jesd_xcvr_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
|
|
@ -275,38 +267,38 @@
|
|||
</connection>
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_clk"
|
||||
end="fmcjesdadc1.cpu_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_clk"
|
||||
end="fmcjesdadc1.mem_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.0"
|
||||
start="a5soc_base.sys_clk"
|
||||
end="fmcjesdadc1.sys_clk" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_intr"
|
||||
end="fmcjesdadc1.axi_dmac_0_intr">
|
||||
<parameter name="irqNumber" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_intr"
|
||||
end="fmcjesdadc1.axi_dmac_1_intr">
|
||||
<parameter name="irqNumber" value="1" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_rst"
|
||||
end="fmcjesdadc1.mem_rst" />
|
||||
end="fmcjesdadc1.cpu_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.0"
|
||||
version="15.1"
|
||||
start="a5soc_base.sys_rst"
|
||||
end="fmcjesdadc1.sys_rst" />
|
||||
end="fmcjesdadc1.mem_rst" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ create_bd_port -dir I -from 3 -to 0 rx_data_n
|
|||
set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
|
||||
set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
|
||||
|
||||
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9250_jesd]
|
||||
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9250_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue