a10gx: top level fixes
Rejeesh Kutty
parent
0c6ef203c0
commit
ad3198f623
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@ -6,54 +6,69 @@ project_new daq2_a10gx -overwrite
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source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl
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set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
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set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
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set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
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set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
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# reference clock
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# lane interface
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set_location_assignment PIN_AB9 -to ref_clk
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set_location_assignment PIN_AB8 -to "ref_clk(n)"
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set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to ref_clk
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set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to ref_clk
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set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to ref_clk
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set_location_assignment PIN_AJ8 -to rx_ref_clk ; ## B20 FMCA_GBTCLK1_M2C_P
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set_location_assignment PIN_AJ7 -to "rx_ref_clk(n)" ; ## B21 FMCA_GBTCLK1_M2C_N
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set_location_assignment PIN_AV5 -to rx_data[0] ; ## A10 FMCA_DP3_M2C_P
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set_location_assignment PIN_AV6 -to "rx_data[0](n)" ; ## A11 FMCA_DP3_M2C_N
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set_location_assignment PIN_AW7 -to rx_data[1] ; ## C06 FMCA_DP0_M2C_P
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set_location_assignment PIN_AW8 -to "rx_data[1](n)" ; ## C07 FMCA_DP0_M2C_N
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set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_DP2_M2C_P
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set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_DP2_M2C_N
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set_location_assignment PIN_BA7 -to rx_data[3] ; ## A02 FMCA_DP1_M2C_P
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set_location_assignment PIN_BA8 -to "rx_data[3](n)" ; ## A03 FMCA_DP1_M2C_N
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set_location_assignment PIN_AT10 -to rx_sync ; ## D08 FMCA_LA01_CC_P
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set_location_assignment PIN_AR11 -to "rx_sync(n)" ; ## D09 FMCA_LA01_CC_N
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set_location_assignment PIN_AR20 -to rx_sysref ; ## G09 FMCA_LA03_P
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set_location_assignment PIN_AR19 -to "rx_sysref(n)" ; ## G10 FMCA_LA03_N
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set_location_assignment PIN_AL8 -to tx_ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P
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set_location_assignment PIN_AL7 -to "tx_ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N
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set_location_assignment PIN_BC3 -to tx_data[0] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[0])
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set_location_assignment PIN_BC4 -to "tx_data[0](n)" ; ## A31 FMCA_DP3_C2M_N (tx_data_n[0])
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set_location_assignment PIN_BC7 -to tx_data[1] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[3])
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set_location_assignment PIN_BC8 -to "tx_data[1](n)" ; ## C03 FMCA_DP0_C2M_N (tx_data_n[3])
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set_location_assignment PIN_BB5 -to tx_data[2] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1])
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set_location_assignment PIN_BB6 -to "tx_data[2](n)" ; ## A27 FMCA_DP2_C2M_N (tx_data_n[1])
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set_location_assignment PIN_BD5 -to tx_data[3] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[2])
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set_location_assignment PIN_BD6 -to "tx_data[3](n)" ; ## A23 FMCA_DP1_C2M_N (tx_data_n[2])
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set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_LA02_P
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set_location_assignment PIN_AT22 -to "tx_sync(n)" ; ## H08 FMCA_LA02_N
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set_location_assignment PIN_AN20 -to tx_sysref ; ## H10 FMCA_LA04_P
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set_location_assignment PIN_AP19 -to "tx_sysref(n)" ; ## H11 FMCA_LA04_N
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# lane data
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
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set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
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set_location_assignment PIN_AE1 -to rx_data[0]
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set_location_assignment PIN_AE2 -to "rx_data[0](n)"
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set_location_assignment PIN_AA1 -to rx_data[1]
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set_location_assignment PIN_AA2 -to "rx_data[1](n)"
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set_location_assignment PIN_U1 -to rx_data[2]
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set_location_assignment PIN_U2 -to "rx_data[2](n)"
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set_location_assignment PIN_R1 -to rx_data[3]
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set_location_assignment PIN_R2 -to "rx_data[3](n)"
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set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[0]
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set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[1]
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set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[2]
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set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[3]
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set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[0]
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set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[1]
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set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[2]
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set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[3]
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# gpio
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# jesd signals
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set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P
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set_location_assignment PIN_AU17 -to "trig(n)" ; ## H14 FMCA_LA07_N
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set_location_assignment PIN_AR14 -to adc_fdb ; ## H17 FMCA_LA11_N
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set_location_assignment PIN_AT14 -to adc_fda ; ## H16 FMCA_LA11_P
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set_location_assignment PIN_AR16 -to dac_irq ; ## G15 FMCA_LA12_P
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set_location_assignment PIN_AP17 -to clkd_status[1] ; ## D18 FMCA_LA13_N
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set_location_assignment PIN_AR17 -to clkd_status[0] ; ## D17 FMCA_LA13_P
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set_location_assignment PIN_AV14 -to adc_pd ; ## C10 FMCA_LA06_P
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set_location_assignment PIN_AP16 -to dac_txen ; ## G16 FMCA_LA12_N
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set_location_assignment PIN_AT15 -to dac_reset ; ## C15 FMCA_LA10_N
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set_location_assignment PIN_AP18 -to clkd_sync ; ## G12 FMCA_LA08_P
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set_location_assignment PIN_AD25 -to rx_sync
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set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sync
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set_location_assignment PIN_AC24 -to rx_sysref
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set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sysref
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set_instance_assignment -name IO_STANDARD LVDS -to trig
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# spi
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set_location_assignment PIN_AG27 -to spi_csn
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set_location_assignment PIN_AH27 -to spi_clk
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set_location_assignment PIN_AD24 -to spi_sdio
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
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set_location_assignment PIN_AV11 -to spi_csn_clk ; ## D11 FMCA_LA05_P
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set_location_assignment PIN_AR15 -to spi_csn_dac ; ## C14 FMCA_LA10_P
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set_location_assignment PIN_AV13 -to spi_csn_adc ; ## D15 FMCA_LA09_N
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set_location_assignment PIN_AW11 -to spi_clk ; ## D12 FMCA_LA05_N
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set_location_assignment PIN_AW13 -to spi_sdio ; ## D14 FMCA_LA09_P
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set_location_assignment PIN_AN19 -to spi_dir ; ## G13 FMCA_LA08_N
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execute_flow -compile
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@ -46,56 +46,69 @@ module system_top (
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// ddr3
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ddr3_a,
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ddr3_ba,
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ddr3_clk_p,
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ddr3_clk_n,
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ddr3_a,
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ddr3_ba,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_odt,
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ddr3_reset_n,
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ddr3_we_n,
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ddr3_ras_n,
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ddr3_cas_n,
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ddr3_we_n,
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ddr3_reset_n,
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ddr3_dq,
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ddr3_dqs_p,
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ddr3_dqs_n,
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ddr3_odt,
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ddr3_dq,
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ddr3_dm,
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ddr3_rzq,
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ddr3_ref_clk,
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// ethernet
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eth_rx_clk,
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eth_rx_data,
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eth_rx_cntrl,
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eth_tx_clk_out,
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eth_tx_data,
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eth_tx_cntrl,
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eth_ref_clk,
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eth_rxd,
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eth_txd,
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eth_mdc,
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eth_mdio_i,
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eth_mdio_o,
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eth_mdio_t,
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eth_phy_resetn,
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eth_mdio,
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eth_resetn,
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eth_intn,
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// board gpio
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led_grn,
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led_red,
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push_buttons,
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dip_switches,
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gpio_bd,
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// lane interface
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ref_clk,
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rx_data,
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rx_sync,
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rx_ref_clk,
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rx_sysref,
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rx_sync,
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rx_data,
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tx_ref_clk,
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tx_sysref,
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tx_sync,
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tx_data,
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// gpio
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trig,
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adc_fdb,
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adc_fda,
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dac_irq,
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clkd_status,
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adc_pd,
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dac_txen,
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dac_reset,
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clkd_sync,
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// spi
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spi_csn,
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spi_csn_clk,
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spi_csn_dac,
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spi_csn_adc,
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spi_clk,
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spi_sdio);
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spi_sdio,
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spi_dir);
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// clock and resets
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@ -104,322 +117,178 @@ module system_top (
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// ddr3
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output [ 13:0] ddr3_a;
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output [ 2:0] ddr3_ba;
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output ddr3_clk_p;
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output ddr3_clk_n;
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output [ 13:0] ddr3_a;
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output [ 2:0] ddr3_ba;
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output ddr3_cke;
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output ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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output ddr3_odt;
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output ddr3_reset_n;
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output ddr3_we_n;
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output ddr3_ras_n;
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output ddr3_cas_n;
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output ddr3_we_n;
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output ddr3_reset_n;
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inout [ 63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_p;
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inout [ 7:0] ddr3_dqs_n;
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output ddr3_odt;
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inout [ 63:0] ddr3_dq;
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output [ 7:0] ddr3_dm;
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input ddr3_rzq;
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input ddr3_ref_clk;
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// ethernet
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input eth_rx_clk;
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input [ 3:0] eth_rx_data;
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input eth_rx_cntrl;
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output eth_tx_clk_out;
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output [ 3:0] eth_tx_data;
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output eth_tx_cntrl;
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input eth_ref_clk;
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input eth_rxd;
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output eth_txd;
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output eth_mdc;
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input eth_mdio_i;
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output eth_mdio_o;
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output eth_mdio_t;
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output eth_phy_resetn;
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inout eth_mdio;
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output eth_resetn;
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input eth_intn;
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// board gpio
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output [ 7:0] led_grn;
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output [ 7:0] led_red;
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input [ 2:0] push_buttons;
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input [ 7:0] dip_switches;
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inout [ 26:0] gpio_bd;
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// lane interface
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input ref_clk;
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input [ 3:0] rx_data;
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input rx_ref_clk;
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input rx_sysref;
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output rx_sync;
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output rx_sysref;
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input [ 3:0] rx_data;
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input tx_ref_clk;
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input tx_sysref;
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input tx_sync;
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output [ 3:0] tx_data;
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// gpio
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input trig;
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inout adc_fdb;
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inout adc_fda;
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inout dac_irq;
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inout [ 1:0] clkd_status;
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inout adc_pd;
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inout dac_txen;
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inout dac_reset;
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inout clkd_sync;
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// spi
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output spi_csn;
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output spi_csn_clk;
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output spi_csn_dac;
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output spi_csn_adc;
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output spi_clk;
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inout spi_sdio;
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// internal registers
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reg rx_sysref_m1 = 'd0;
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reg rx_sysref_m2 = 'd0;
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reg rx_sysref_m3 = 'd0;
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reg rx_sysref = 'd0;
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reg dma0_wr = 'd0;
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reg [ 63:0] dma0_wdata = 'd0;
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reg dma1_wr = 'd0;
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reg [ 63:0] dma1_wdata = 'd0;
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reg [ 3:0] phy_rst_cnt = 0;
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reg phy_rst_reg = 0;
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// internal clocks and resets
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wire sys_125m_clk;
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wire sys_25m_clk;
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wire sys_2m5_clk;
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wire eth_tx_clk;
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wire rx_clk;
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wire adc0_clk;
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wire adc1_clk;
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output spi_dir;
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// internal signals
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wire sys_pll_locked_s;
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wire eth_tx_reset_s;
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wire eth_tx_mode_1g_s;
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wire eth_tx_mode_10m_100m_n_s;
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wire spi_mosi;
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wire spi_miso;
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wire adc0_enable_a_s;
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wire [ 31:0] adc0_data_a_s;
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wire adc0_enable_b_s;
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wire [ 31:0] adc0_data_b_s;
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wire adc0_dovf_s;
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wire adc1_enable_a_s;
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wire [ 31:0] adc1_data_a_s;
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wire adc1_enable_b_s;
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wire [ 31:0] adc1_data_b_s;
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wire adc1_dovf_s;
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wire [ 3:0] rx_ip_sof_s;
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wire [127:0] rx_ip_data_s;
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wire [127:0] rx_data_s;
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wire rx_sw_rstn_s;
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wire rx_sysref_s;
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wire rx_err_s;
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wire rx_ready_s;
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wire [ 3:0] rx_rst_state_s;
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wire rx_lane_aligned_s;
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wire [ 3:0] rx_analog_reset_s;
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wire [ 3:0] rx_digital_reset_s;
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wire [ 3:0] rx_cdr_locked_s;
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wire [ 3:0] rx_cal_busy_s;
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wire rx_pll_locked_s;
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wire [ 15:0] rx_xcvr_status_s;
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wire ddr3_cal_pass;
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wire ddr3_cal_fail;
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wire eth_mdio_i;
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wire eth_mdio_o;
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wire eth_mdio_t;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire spi_miso_s;
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wire spi_mosi_s;
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wire [ 7:0] spi_csn_s;
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// ethernet transmit clock
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// daq2
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assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
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(eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
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assign eth_phy_resetn = phy_rst_reg;
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always@ (posedge eth_mdc) begin
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phy_rst_cnt <= phy_rst_cnt + 4'd1;
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if (phy_rst_cnt == 4'h0) begin
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phy_rst_reg <= sys_pll_locked_s;
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end
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end
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altddio_out #(.width(1)) i_eth_tx_clk_out (
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.aset (1'b0),
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.sset (1'b0),
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.sclr (1'b0),
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.oe (1'b1),
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.oe_out (),
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.datain_h (1'b1),
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.datain_l (1'b0),
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.outclocken (1'b1),
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.aclr (eth_tx_reset_s),
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.outclock (eth_tx_clk),
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.dataout (eth_tx_clk_out));
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assign eth_tx_reset_s = ~sys_pll_locked_s;
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always @(posedge rx_clk) begin
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rx_sysref_m1 <= rx_sysref_s;
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rx_sysref_m2 <= rx_sysref_m1;
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rx_sysref_m3 <= rx_sysref_m2;
|
||||
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
|
||||
end
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
dma0_wr <= adc0_enable_a_s & adc0_enable_b_s;
|
||||
dma0_wdata <= { adc0_data_b_s[31:16],
|
||||
adc0_data_a_s[31:16],
|
||||
adc0_data_b_s[15: 0],
|
||||
adc0_data_a_s[15: 0]};
|
||||
dma1_wr <= adc1_enable_a_s & adc1_enable_b_s;
|
||||
dma1_wdata <= { adc1_data_b_s[31:16],
|
||||
adc1_data_a_s[31:16],
|
||||
adc1_data_b_s[15: 0],
|
||||
adc1_data_a_s[15: 0]};
|
||||
end
|
||||
|
||||
sld_signaltap #(
|
||||
.sld_advanced_trigger_entity ("basic,1,"),
|
||||
.sld_data_bits (130),
|
||||
.sld_data_bit_cntr_bits (8),
|
||||
.sld_enable_advanced_trigger (0),
|
||||
.sld_mem_address_bits (10),
|
||||
.sld_node_crc_bits (32),
|
||||
.sld_node_crc_hiword (10311),
|
||||
.sld_node_crc_loword (14297),
|
||||
.sld_node_info (1076736),
|
||||
.sld_ram_block_type ("AUTO"),
|
||||
.sld_sample_depth (1024),
|
||||
.sld_storage_qualifier_gap_record (0),
|
||||
.sld_storage_qualifier_mode ("OFF"),
|
||||
.sld_trigger_bits (2),
|
||||
.sld_trigger_in_enabled (0),
|
||||
.sld_trigger_level (1),
|
||||
.sld_trigger_level_pipeline (1))
|
||||
i_signaltap (
|
||||
.acq_clk (rx_clk),
|
||||
.acq_data_in ({ rx_sysref,
|
||||
rx_sync,
|
||||
adc1_data_b_s,
|
||||
adc1_data_a_s,
|
||||
adc0_data_b_s,
|
||||
adc0_data_a_s}),
|
||||
.acq_trigger_in ({rx_sysref, rx_sync}));
|
||||
|
||||
genvar n;
|
||||
generate
|
||||
for (n = 0; n < 4; n = n + 1) begin: g_align_1
|
||||
ad_jesd_align i_jesd_align (
|
||||
.rx_clk (rx_clk),
|
||||
.rx_sof (rx_ip_sof_s),
|
||||
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
|
||||
.rx_data (rx_data_s[n*32+31:n*32]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign rx_xcvr_status_s[15:15] = 1'd0;
|
||||
assign rx_xcvr_status_s[14:14] = rx_sync;
|
||||
assign rx_xcvr_status_s[13:13] = rx_ready_s;
|
||||
assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
|
||||
assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
|
||||
assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
|
||||
assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
|
||||
|
||||
ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
|
||||
.rx_clk (rx_clk),
|
||||
.rx_rstn (sys_resetn),
|
||||
.rx_sw_rstn (rx_sw_rstn_s),
|
||||
.rx_pll_locked (rx_pll_locked_s),
|
||||
.rx_cal_busy (rx_cal_busy_s),
|
||||
.rx_cdr_locked (rx_cdr_locked_s),
|
||||
.rx_analog_reset (rx_analog_reset_s),
|
||||
.rx_digital_reset (rx_digital_reset_s),
|
||||
.rx_ready (rx_ready_s),
|
||||
.rx_rst_state (rx_rst_state_s));
|
||||
assign spi_csn_adc = spi_csn_s[2];
|
||||
assign spi_csn_dac = spi_csn_s[1];
|
||||
assign spi_csn_clk = spi_csn_s[0];
|
||||
|
||||
daq2_spi i_daq2_spi (
|
||||
.spi_csn (spi_csn),
|
||||
.spi_csn (spi_csn_s[2:0]),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
.spi_miso (spi_miso),
|
||||
.spi_sdio (spi_sdio));
|
||||
.spi_mosi (spi_mosi_s),
|
||||
.spi_miso (spi_miso_s),
|
||||
.spi_sdio (spi_sdio),
|
||||
.spi_dir (spi_dir));
|
||||
|
||||
assign gpio_i[63:44] = 19'd0;
|
||||
assign gpio_i[43] = trig;
|
||||
assign gpio_i[39] = 1'd0;
|
||||
assign gpio_i[37] = 1'd0;
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
|
||||
.dio_t ({3'h0, 1'h0, 5'h1f}),
|
||||
.dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
|
||||
.dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
|
||||
.dio_p ({ adc_pd, // 42
|
||||
dac_txen, // 41
|
||||
dac_reset, // 40
|
||||
clkd_sync, // 38
|
||||
adc_fdb, // 36
|
||||
adc_fda, // 35
|
||||
dac_irq, // 34
|
||||
clkd_status})); // 32
|
||||
|
||||
// board stuff
|
||||
|
||||
assign eth_resetn = 1'b1;
|
||||
assign eth_mdio_i = eth_mdio;
|
||||
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
|
||||
|
||||
assign gpio_i[31] = 1'd0;
|
||||
assign gpio_i[30] = 1'd0;
|
||||
assign gpio_i[29] = 1'd0;
|
||||
assign gpio_i[28] = ddr3_cal_fail;
|
||||
assign gpio_i[27] = ddr3_cal_pass;
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
|
||||
.dio_t ({11'h7ff, 16'h0}),
|
||||
.dio_i (gpio_o[26:0]),
|
||||
.dio_o (gpio_i[26:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
system_bd i_system_bd (
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_reset_reset_n (sys_resetn),
|
||||
.sys_125m_clk_clk (sys_125m_clk),
|
||||
.sys_25m_clk_clk (sys_25m_clk),
|
||||
.sys_2m5_clk_clk (sys_2m5_clk),
|
||||
.sys_ddr3_phy_mem_a (ddr3_a),
|
||||
.sys_ddr3_phy_mem_ba (ddr3_ba),
|
||||
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
|
||||
.sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
|
||||
.sys_ddr3_phy_mem_cke (ddr3_cke),
|
||||
.sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
|
||||
.sys_ddr3_phy_mem_dm (ddr3_dm),
|
||||
.sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
|
||||
.sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
|
||||
.sys_ddr3_phy_mem_we_n (ddr3_we_n),
|
||||
.sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
|
||||
.sys_ddr3_phy_mem_dq (ddr3_dq),
|
||||
.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
|
||||
.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
|
||||
.sys_ddr3_phy_mem_odt (ddr3_odt),
|
||||
.sys_ddr3_oct_rzqin (ddr3_rzq),
|
||||
.sys_ethernet_tx_clk_clk (eth_tx_clk),
|
||||
.sys_ethernet_rx_clk_clk (eth_rx_clk),
|
||||
.sys_ethernet_status_set_10 (),
|
||||
.sys_ethernet_status_set_1000 (),
|
||||
.sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
|
||||
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
|
||||
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
|
||||
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
|
||||
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
|
||||
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_ck (ddr3_clk_p),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_ck_n (ddr3_clk_n),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_a (ddr3_a),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_ba (ddr3_ba),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_cke (ddr3_cke),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_cs_n (ddr3_cs_n),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_odt (ddr3_odt),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_reset_n (ddr3_reset_n),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_we_n (ddr3_we_n),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_ras_n (ddr3_ras_n),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_cas_n (ddr3_cas_n),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_dqs (ddr3_dqs_p),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_dqs_n (ddr3_dqs_n),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_dq (ddr3_dq),
|
||||
.sys_ddr3_cntrl_mem_conduit_end_mem_dm (ddr3_dm),
|
||||
.sys_ddr3_cntrl_oct_conduit_end_oct_rzqin (ddr3_rzq),
|
||||
.sys_ddr3_cntrl_ref_clk_clk (ddr3_ref_clk),
|
||||
.sys_ddr3_cntrl_status_conduit_end_local_cal_success (ddr3_cal_pass),
|
||||
.sys_ddr3_cntrl_status_conduit_end_local_cal_fail (ddr3_cal_fail),
|
||||
.sys_ethernet_mdio_mdc (eth_mdc),
|
||||
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
|
||||
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
|
||||
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
|
||||
.sys_gpio_in_port ({rx_xcvr_status_s, 5'd0, push_buttons, dip_switches}),
|
||||
.sys_gpio_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}),
|
||||
.sys_spi_MISO (spi_miso),
|
||||
.sys_spi_MOSI (spi_mosi),
|
||||
.sys_ethernet_ref_clk_clk (eth_ref_clk),
|
||||
.sys_ethernet_sgmii_rxp_0 (eth_rxd),
|
||||
.sys_ethernet_sgmii_txp_0 (eth_txd),
|
||||
.sys_gpio_in_port (gpio_i[63:32]),
|
||||
.sys_gpio_out_port (gpio_o[63:32]),
|
||||
.sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||
.sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||
.sys_reset_reset_n (sys_resetn),
|
||||
.sys_spi_MISO (spi_miso_s),
|
||||
.sys_spi_MOSI (spi_mosi_s),
|
||||
.sys_spi_SCLK (spi_clk),
|
||||
.sys_spi_SS_n (spi_csn),
|
||||
.axi_ad9250_0_xcvr_clk_clk (rx_clk),
|
||||
.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
|
||||
.axi_ad9250_0_adc_clock_clk (adc0_clk),
|
||||
.axi_ad9250_0_adc_dma_if_adc_valid_a (),
|
||||
.axi_ad9250_0_adc_dma_if_adc_enable_a (adc0_enable_a_s),
|
||||
.axi_ad9250_0_adc_dma_if_adc_data_a (adc0_data_a_s),
|
||||
.axi_ad9250_0_adc_dma_if_adc_valid_b (),
|
||||
.axi_ad9250_0_adc_dma_if_adc_enable_b (adc0_enable_b_s),
|
||||
.axi_ad9250_0_adc_dma_if_adc_data_b (adc0_data_b_s),
|
||||
.axi_ad9250_0_adc_dma_if_adc_dovf (adc0_dovf_s),
|
||||
.axi_ad9250_0_adc_dma_if_adc_dunf (1'b0),
|
||||
.axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
|
||||
.axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
|
||||
.axi_dmac_0_fifo_wr_if_wren (dma0_wr),
|
||||
.axi_dmac_0_fifo_wr_if_data (dma0_wdata),
|
||||
.axi_dmac_0_fifo_wr_if_sync (1'b1),
|
||||
.axi_ad9250_1_xcvr_clk_clk (rx_clk),
|
||||
.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
|
||||
.axi_ad9250_1_adc_clock_clk (adc1_clk),
|
||||
.axi_ad9250_1_adc_dma_if_adc_valid_a (),
|
||||
.axi_ad9250_1_adc_dma_if_adc_enable_a (adc1_enable_a_s),
|
||||
.axi_ad9250_1_adc_dma_if_adc_data_a (adc1_data_a_s),
|
||||
.axi_ad9250_1_adc_dma_if_adc_valid_b (),
|
||||
.axi_ad9250_1_adc_dma_if_adc_enable_b (adc1_enable_b_s),
|
||||
.axi_ad9250_1_adc_dma_if_adc_data_b (adc1_data_b_s),
|
||||
.axi_ad9250_1_adc_dma_if_adc_dovf (adc1_dovf_s),
|
||||
.axi_ad9250_1_adc_dma_if_adc_dunf (1'b0),
|
||||
.axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
|
||||
.axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
|
||||
.axi_dmac_1_fifo_wr_if_wren (dma1_wr),
|
||||
.axi_dmac_1_fifo_wr_if_data (dma1_wdata),
|
||||
.axi_dmac_1_fifo_wr_if_sync (1'b1),
|
||||
.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
|
||||
.sys_jesd204b_s1_rx_link_valid (),
|
||||
.sys_jesd204b_s1_rx_link_ready (1'b1),
|
||||
.sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
|
||||
.sys_jesd204b_s1_sysref_export (rx_sysref),
|
||||
.sys_jesd204b_s1_rx_ferr_export (rx_err_s),
|
||||
.sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
|
||||
.sys_jesd204b_s1_sync_n_export (rx_sync),
|
||||
.sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
|
||||
.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
|
||||
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
|
||||
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
|
||||
.sys_jesd204b_s1_locked_rx_is_lockedtodata (rx_cdr_locked_s),
|
||||
.sys_jesd204b_s1_rx_cal_busy_rx_cal_busy (rx_cal_busy_s),
|
||||
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
|
||||
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
|
||||
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
|
||||
.sys_pll_locked_export (sys_pll_locked_s));
|
||||
.sys_spi_SS_n (spi_csn_s),
|
||||
.sys_xcvr_rx_ref_clk_clk (rx_ref_clk),
|
||||
.sys_xcvr_rx_sync_n_export (rx_sync),
|
||||
.sys_xcvr_rx_sysref_export (rx_sysref),
|
||||
.sys_xcvr_rxd_rx_serial_data (rx_data),
|
||||
.sys_xcvr_tx_ref_clk_clk (tx_ref_clk),
|
||||
.sys_xcvr_tx_sync_n_export (tx_sync),
|
||||
.sys_xcvr_tx_sysref_export (tx_sysref),
|
||||
.sys_xcvr_txd_tx_serial_data (tx_data));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue