diff --git a/projects/ad9081_fmca_ebz/zc706/Makefile b/projects/ad9081_fmca_ebz/zc706/Makefile new file mode 100644 index 000000000..a2e200f09 --- /dev/null +++ b/projects/ad9081_fmca_ebz/zc706/Makefile @@ -0,0 +1,34 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9081_fmca_ebz_zc706 + +M_DEPS += timing_constr.xdc +M_DEPS += ../common/ad9081_fmca_ebz_bd.tcl +M_DEPS += ../../common/zc706/zc706_system_constr.xdc +M_DEPS += ../../common/zc706/zc706_system_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_3w_spi.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9081_fmca_ebz/zc706/system_bd.tcl b/projects/ad9081_fmca_ebz/zc706/system_bd.tcl new file mode 100644 index 000000000..0f5f484e4 --- /dev/null +++ b/projects/ad9081_fmca_ebz/zc706/system_bd.tcl @@ -0,0 +1,18 @@ + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr 32*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr 32*1024] + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl +source ../common/ad9081_fmca_ebz_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + diff --git a/projects/ad9081_fmca_ebz/zc706/system_constr.xdc b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc new file mode 100644 index 000000000..a3edb067d --- /dev/null +++ b/projects/ad9081_fmca_ebz/zc706/system_constr.xdc @@ -0,0 +1,88 @@ +# +## mxfe +# + +set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L24P_T3_13 +set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L24N_T3_13 +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L10P_T1_13 +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L10N_T1_13 +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L11P_T1_SRCC_13 +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L11N_T1_SRCC_13 +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L8P_T1_13 +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L8N_T1_13 +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L14N_T2_SRCC_11 +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L14P_T2_SRCC_11 +set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1_MRCC_13 +set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1_MRCC_13 +set_property -dict {PACKAGE_PIN AD9 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_109 +set_property -dict {PACKAGE_PIN AD10 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_109 +set_property -quiet -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTXRXN2_109 FPGA_SERDIN_0_N +set_property -quiet -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTXRXP2_109 FPGA_SERDIN_0_P +set_property -quiet -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTXRXN0_109 FPGA_SERDIN_1_N +set_property -quiet -dict {PACKAGE_PIN AH10 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTXRXP0_109 FPGA_SERDIN_1_P +set_property -quiet -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTXRXN3_110 FPGA_SERDIN_2_N +set_property -quiet -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTXRXP3_110 FPGA_SERDIN_2_P +set_property -quiet -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTXRXN2_110 FPGA_SERDIN_3_N +set_property -quiet -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTXRXP2_110 FPGA_SERDIN_3_P +set_property -quiet -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTXRXN1_110 FPGA_SERDIN_4_N +set_property -quiet -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTXRXP1_110 FPGA_SERDIN_4_P +set_property -quiet -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTXRXN0_110 FPGA_SERDIN_5_N +set_property -quiet -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTXRXP0_110 FPGA_SERDIN_5_P +set_property -quiet -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTXRXN3_109 FPGA_SERDIN_6_N +set_property -quiet -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTXRXP3_109 FPGA_SERDIN_6_P +set_property -quiet -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTXRXN1_109 FPGA_SERDIN_7_N +set_property -quiet -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTXRXP1_109 FPGA_SERDIN_7_P +set_property -quiet -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[0] ] ; ## FMC0_DP0_C2M_N MGTXTXN0_109 FPGA_SERDOUT_0_N +set_property -quiet -dict {PACKAGE_PIN AK10 } [get_ports tx_data_p[0] ] ; ## FMC0_DP0_C2M_P MGTXTXP0_109 FPGA_SERDOUT_0_P +set_property -quiet -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2] ] ; ## FMC0_DP2_C2M_N MGTXTXN2_109 FPGA_SERDOUT_1_N +set_property -quiet -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2] ] ; ## FMC0_DP2_C2M_P MGTXTXP2_109 FPGA_SERDOUT_1_P +set_property -quiet -dict {PACKAGE_PIN AD1 } [get_ports tx_data_n[7] ] ; ## FMC0_DP7_C2M_N MGTXTXN3_110 FPGA_SERDOUT_2_N +set_property -quiet -dict {PACKAGE_PIN AD2 } [get_ports tx_data_p[7] ] ; ## FMC0_DP7_C2M_P MGTXTXP3_110 FPGA_SERDOUT_2_P +set_property -quiet -dict {PACKAGE_PIN AE3 } [get_ports tx_data_n[6] ] ; ## FMC0_DP6_C2M_N MGTXTXN2_110 FPGA_SERDOUT_3_N +set_property -quiet -dict {PACKAGE_PIN AE4 } [get_ports tx_data_p[6] ] ; ## FMC0_DP6_C2M_P MGTXTXP2_110 FPGA_SERDOUT_3_P +set_property -quiet -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[1] ] ; ## FMC0_DP1_C2M_N MGTXTXN1_109 FPGA_SERDOUT_4_N +set_property -quiet -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[1] ] ; ## FMC0_DP1_C2M_P MGTXTXP1_109 FPGA_SERDOUT_4_P +set_property -quiet -dict {PACKAGE_PIN AF1 } [get_ports tx_data_n[5] ] ; ## FMC0_DP5_C2M_N MGTXTXN1_110 FPGA_SERDOUT_5_N +set_property -quiet -dict {PACKAGE_PIN AF2 } [get_ports tx_data_p[5] ] ; ## FMC0_DP5_C2M_P MGTXTXP1_110 FPGA_SERDOUT_5_P +set_property -quiet -dict {PACKAGE_PIN AH1 } [get_ports tx_data_n[4] ] ; ## FMC0_DP4_C2M_N MGTXTXN0_110 FPGA_SERDOUT_6_N +set_property -quiet -dict {PACKAGE_PIN AH2 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTXTXP0_110 FPGA_SERDOUT_6_P +set_property -quiet -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTXTXN3_109 FPGA_SERDOUT_7_N +set_property -quiet -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTXTXP3_109 FPGA_SERDOUT_7_P +set_property -quiet -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fpga_syncin_n[0] ] ; ## FMC0_LA02_N IO_L16N_T2_11 +set_property -quiet -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fpga_syncin_p[0] ] ; ## FMC0_LA02_P IO_L16P_T2_11 +set_property -quiet -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fpga_syncin_n[1] ] ; ## FMC0_LA03_N IO_L17N_T2_11 +set_property -quiet -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fpga_syncin_p[1] ] ; ## FMC0_LA03_P IO_L17P_T2_11 +set_property -quiet -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 } [get_ports fpga_syncout_n[0]] ; ## FMC0_LA01_CC_N IO_L13N_T2_MRCC_11 +set_property -quiet -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 } [get_ports fpga_syncout_p[0]] ; ## FMC0_LA01_CC_P IO_L13P_T2_MRCC_11 +set_property -quiet -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 } [get_ports fpga_syncout_n[1]] ; ## FMC0_LA06_N IO_L6N_T0_VREF_11 +set_property -quiet -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 } [get_ports fpga_syncout_p[1]] ; ## FMC0_LA06_P IO_L6P_T0_11 +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L21P_T3_DQS_11 +set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L21N_T3_DQS_11 +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L17P_T2_13 +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L17N_T2_13 +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L23P_T3_11 +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L23N_T3_11 +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1_11 +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1_11 +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L22P_T3_11 +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L22N_T3_11 +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L9N_T1_DQS_13 +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L11N_T1_SRCC_11 +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L4N_T0_11 +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L18P_T2_11 +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L18N_T2_11 +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L4P_T0_11 +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L8P_T1_11 +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L8N_T1_11 +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L5P_T0_11 +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L5N_T0_11 +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L15P_T2_DQS_11 +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L15N_T2_DQS_11 +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1_DQS_11 +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L11P_T1_SRCC_11 +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1_DQS_11 +set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1_MRCC_11 +set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1_MRCC_11 +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L10P_T1_11 +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L10N_T1_11 + diff --git a/projects/ad9081_fmca_ebz/zc706/system_project.tcl b/projects/ad9081_fmca_ebz/zc706/system_project.tcl new file mode 100644 index 000000000..b495b891a --- /dev/null +++ b/projects/ad9081_fmca_ebz/zc706/system_project.tcl @@ -0,0 +1,60 @@ +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 +# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer +# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer +# +# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode +# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode +# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode +# Encoding is: +# 0 - CPLL +# 1 - QPLL0 +# 2 - QPLL1 +# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported +# [RX/TX]_NUM_LINKS : Number of links +# +# +# !!! For this carrier only 8B10B mode is supported !!! +# + +adi_project ad9081_fmca_ebz_zc706 0 [list \ + JESD_MODE 8B10B \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ +] + +adi_project_files ad9081_fmca_ebz_zc706 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "timing_constr.xdc"\ + "../../../library/common/ad_3w_spi.v"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run ad9081_fmca_ebz_zc706 + diff --git a/projects/ad9081_fmca_ebz/zc706/system_top.v b/projects/ad9081_fmca_ebz/zc706/system_top.v new file mode 100644 index 000000000..fadf7c114 --- /dev/null +++ b/projects/ad9081_fmca_ebz/zc706/system_top.v @@ -0,0 +1,356 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_JESD_L = 8, + parameter TX_NUM_LINKS = 1, + parameter RX_JESD_L = 8, + parameter RX_NUM_LINKS = 1 + ) ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [14:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, + + output spdif, + + inout iic_scl, + inout iic_sda, + + // FMC HPC IOs + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + input clkin6_n, + input clkin6_p, + input clkin10_n, + input clkin10_p, + input fpga_refclk_in_n, + input fpga_refclk_in_p, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, + input [TX_NUM_LINKS-1:0] fpga_syncin_n, + input [TX_NUM_LINKS-1:0] fpga_syncin_p, + output [RX_NUM_LINKS-1:0] fpga_syncout_n, + output [RX_NUM_LINKS-1:0] fpga_syncout_p, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + input sysref2_n, + input sysref2_p, + output [1:0] txen + +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 2:0] spi0_csn; + + wire [ 2:0] spi1_csn; + wire spi1_mosi; + wire spi1_miso; + + wire ref_clk; + wire sysref; + wire [TX_NUM_LINKS-1:0] tx_syncin; + wire [RX_NUM_LINKS-1:0] rx_syncout; + + wire [7:0] rx_data_p_loc; + wire [7:0] rx_data_n_loc; + wire [7:0] tx_data_p_loc; + wire [7:0] tx_data_n_loc; + + wire clkin6; + wire clkin10; + wire tx_device_clk; + wire rx_device_clk; + + assign iic_rstn = 1'b1; + + // instantiations + + IBUFDS_GTE2 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (fpga_refclk_in_p), + .IB (fpga_refclk_in_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref ( + .I (sysref2_p), + .IB (sysref2_n), + .O (sysref)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clkin6_p), + .IB (clkin6_n), + .O (clkin6)); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clkin10_p), + .IB (clkin10_n), + .O (clkin10)); + + genvar i; + generate + for(i=0;i