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usdrx1: remove constraints and other changes

main
Rejeesh Kutty 2014-10-09 15:24:41 -04:00
parent 4bdb3cd262
commit adf4893a27
2 changed files with 95 additions and 124 deletions
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25
projects/usdrx1/a5gt/system_constr.sdc
View File

@ -1,34 +1,9 @@
create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
#create_clock -period "80.000 ns" -name spi_clk [get_nets {system_bd:i_system_bd|system_bd_sys_spi:sys_spi|SCLK_reg}]
derive_pll_clocks
derive_clock_uncertainty
set clk_100m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_166m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_125m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_25m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_2m5 [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -from {sys_resetn} -to *
set_false_path -from $clk_100m -to $clk_166m
set_false_path -from $clk_100m -to $clk_rxlink
set_false_path -from $clk_166m -to $clk_100m
set_false_path -from $clk_166m -to $clk_rxlink
set_false_path -from $clk_rxlink -to $clk_100m
set_false_path -from $clk_rxlink -to $clk_166m
set_false_path -from $clk_125m -to $clk_25m
set_false_path -from $clk_125m -to $clk_2m5
set_false_path -from $clk_25m -to $clk_125m
set_false_path -from $clk_25m -to $clk_2m5
set_false_path -from $clk_2m5 -to $clk_125m
set_false_path -from $clk_2m5 -to $clk_25m

24
projects/usdrx1/a5gt/system_top.v
View File

@ -195,10 +195,11 @@ module system_top (
output afe_rst;
output afe_trig;
// gpio
output dac_sleep;
output [13:0] dac_data;
output [ 13:0] dac_data;
output afe_pdn;
output afe_stby;
output clk_resetn;
@ -216,6 +217,14 @@ module system_top (
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref = 'd0;
reg dma_sync = 'd0;
reg dma_wr = 'd0;
reg adc_dovf;
reg [511:0] dma_data = 'd0;
reg rx_sof_0_s = 'd0;
reg rx_sof_1_s = 'd0;
reg rx_sof_2_s = 'd0;
reg rx_sof_3_s = 'd0;
// internal clocks and resets
@ -226,24 +235,12 @@ module system_top (
wire rx_clk;
wire adc_clk;
// internal registers
reg dma_sync = 'd0;
reg dma_wr = 'd0;
reg adc_dovf;
reg [511:0] dma_data = 'd0;
reg rx_sof_0_s = 'd0;
reg rx_sof_1_s = 'd0;
reg rx_sof_2_s = 'd0;
reg rx_sof_3_s = 'd0;
// internal signals
wire sys_pll_locked_s;
wire eth_tx_reset_s;
wire eth_tx_mode_1g_s;
wire eth_tx_mode_10m_100m_n_s;
wire [ 4:0] spi_csn;
wire spi_clk;
wire spi_mosi;
@ -267,7 +264,6 @@ module system_top (
wire adc_dovf_1;
wire adc_dovf_2;
wire adc_dovf_3;
wire [ 3:0] rx_ip_sof_s;
wire [255:0] rx_ip_data_s;
wire [255:0] rx_data_s;