diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
index 5873ace04..258b67b0f 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc
@@ -8,28 +8,45 @@ set_property ASYNC_REG TRUE \
   [get_cells -hier *dac_last_*_m*] \
   [get_cells -hier *dac_bypass_m*]
 
-set_false_path -to [get_cells  -hier -filter {name =~ *_bypass_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells  -hier -filter {name =~ *dac_xfer_out_m1_reg && IS_SEQUENTIAL}]
-set_false_path -to [get_cells  -hier -filter {name =~ *_xfer_req_m_reg[0]* && IS_SEQUENTIAL}]
+# AXI clk to DMA clk
+set_false_path -from [get_cells  -hier -filter {name =~ */axi_mem_raddr_g* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells  -hier -filter {name =~ */axi_mem_last_read_toggle* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */dma_mem_last_read_toggle_m_* && IS_SEQUENTIAL}]
 
-set_false_path -from [get_cells  -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
-               -to   [get_cells  -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
-set_false_path -from [get_cells  -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-               -to   [get_cells  -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
+# DAC clk to DMA clk
+set_false_path -from [get_cells  -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */dma_mem_raddr_m1_* && IS_SEQUENTIAL}]
+set_false_path -to   [get_cells  -hier -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}]
 
-set_false_path -from [get_cells  -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
-               -to   [get_cells  -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}]
-set_false_path -from [get_cells  -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \
-               -to   [get_cells  -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]
 
-set_false_path -from [get_cells  -hier -filter {name =~ *dac_* && IS_SEQUENTIAL}] \
-               -to   [get_cells  -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}]
-set_false_path -from [get_cells  -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \
-               -to   [get_cells  -hier -filter {name =~ *dac_*_m* && IS_SEQUENTIAL}]
+# DMA clk to AXI clk
+set_false_path -from [get_cells  -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */axi_dma_last_beats_m1* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells  -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */axi_mem_waddr_m1* && IS_SEQUENTIAL}]
+#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
+set_false_path -through [get_pins  -hier -filter {name =~ */axi_xfer_req_m_reg[0]/D}]
 
-set_false_path -from [get_cells -hier -filter {name =~ *axi_mem_laddr* && IS_SEQUENTIAL}] \
-               -to   [get_cells -hier -filter {name =~ *dac_mem_laddr* && IS_SEQUENTIAL}]
+# DAC clk to AXI clk
+set_false_path -from [get_cells  -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */axi_mem_raddr_m1* && IS_SEQUENTIAL}]
 
-set_false_path -from [get_cells -hier -filter {name =~ *i_laddress_buffer*m_ram_reg* && IS_SEQUENTIAL}] \
-               -to   [get_cells -hier -filter {name =~ *dac_mem_raddr_reg* && IS_SEQUENTIAL}]
+# DMA clk to DAC clk
+set_false_path -from [get_cells  -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells  -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */dac_last_beats_m* && IS_SEQUENTIAL}]
+#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
+set_false_path -through [get_pins  -hier -filter {name =~ */dac_xfer_out_m1_reg*/D}]
+
+# AXI clk to DAC clk
+set_false_path -from [get_cells  -hier -filter {name =~ */axi_mem_laddr* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */dac_mem_laddr* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells  -hier -filter {name =~ */axi_mem_laddr_toggle* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */dac_mem_laddr_toggle_m* && IS_SEQUENTIAL}]
+set_false_path -from [get_cells  -hier -filter {name =~ */axi_mem_waddr_g* && IS_SEQUENTIAL}] \
+               -to   [get_cells  -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}]
+#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain
+set_false_path -through [get_pins  -hier -filter {name =~ */dac_xfer_req_m_reg[0]/D}]