From ae1dd1d58e4bdd31ee6c5a7829ba3585bfadaeb2 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 7 Jun 2016 12:25:56 -0400 Subject: [PATCH] daq2/a10gx- qsys updates --- projects/daq2/a10gx/system_constr.sdc | 26 ++++---- projects/daq2/a10gx/system_project.tcl | 4 +- projects/daq2/a10gx/system_top.v | 84 +++++++++++++------------- 3 files changed, 56 insertions(+), 58 deletions(-) diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc index 7ec6b3f16..a1450327d 100644 --- a/projects/daq2/a10gx/system_constr.sdc +++ b/projects/daq2/a10gx/system_constr.sdc @@ -7,37 +7,37 @@ derive_pll_clocks derive_clock_uncertainty set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_0 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_1 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_2 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_0 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_1 \ - i_system_bd|a10gx_base|sys_ddr3_cntrl_phy_clk_l_2}] + i_system_bd|sys_ddr3_cntrl_phy_clk_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_2 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \ + i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}] set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\ - i_system_bd|a10gx_base|sys_ddr3_cntrl_core_nios_clk}] + i_system_bd|sys_ddr3_cntrl_core_nios_clk}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_tx_csr_inst*]\ - -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}] + -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_tx_ctl_inst*]\ - -to [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}] + -to [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}] set_false_path -from [get_clocks {sys_clk_100mhz}]\ -through [get_nets *altera_jesd204_rx_csr_inst*]\ - -to [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}] + -to [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}] -set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\ -through [get_nets *altera_jesd204_tx_csr_inst*]\ -to [get_clocks {sys_clk_100mhz}] -set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_tx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|xcvr_tx_pll|outclk0}]\ -through [get_nets *altera_jesd204_tx_ctl_inst*]\ -to [get_clocks {sys_clk_100mhz}] -set_false_path -from [get_clocks {i_system_bd|daq2|xcvr_rx_pll|outclk0}]\ +set_false_path -from [get_clocks {i_system_bd|xcvr_rx_pll|outclk0}]\ -through [get_nets *altera_jesd204_rx_csr_inst*]\ -to [get_clocks {sys_clk_100mhz}] diff --git a/projects/daq2/a10gx/system_project.tcl b/projects/daq2/a10gx/system_project.tcl index 664f75637..6947398c3 100644 --- a/projects/daq2/a10gx/system_project.tcl +++ b/projects/daq2/a10gx/system_project.tcl @@ -5,13 +5,11 @@ source ../../scripts/adi_env.tcl project_new daq2_a10gx -overwrite source "../../common/a10gx/a10gx_system_assign.tcl" -set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a10gx/;../../../library/**/*" -set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a10gx;../../../library/**/*" -set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v" set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v set_global_assignment -name VERILOG_FILE system_top.v +set_global_assignment -name QSYS_FILE system_bd.qsys set_global_assignment -name SDC_FILE system_constr.sdc set_global_assignment -name TOP_LEVEL_ENTITY system_top diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v index 7e3d0bfb1..ccfaa6820 100644 --- a/projects/daq2/a10gx/system_top.v +++ b/projects/daq2/a10gx/system_top.v @@ -238,49 +238,49 @@ module system_top ( assign gpio_bd_o = gpio_o[15:0]; system_bd i_system_bd ( - .a10gx_base_sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), - .a10gx_base_sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), - .a10gx_base_sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), - .a10gx_base_sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), - .a10gx_base_sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), - .a10gx_base_sys_ethernet_mdio_mdc (eth_mdc), - .a10gx_base_sys_ethernet_mdio_mdio_in (eth_mdio_i), - .a10gx_base_sys_ethernet_mdio_mdio_out (eth_mdio_o), - .a10gx_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t), - .a10gx_base_sys_ethernet_ref_clk_clk (eth_ref_clk), - .a10gx_base_sys_ethernet_reset_reset (eth_reset), - .a10gx_base_sys_ethernet_sgmii_rxp_0 (eth_rxd), - .a10gx_base_sys_ethernet_sgmii_txp_0 (eth_txd), - .a10gx_base_sys_gpio_in_export (gpio_i[63:32]), - .a10gx_base_sys_gpio_out_export (gpio_o[63:32]), - .a10gx_base_sys_gpio_bd_in_port (gpio_i[31:0]), - .a10gx_base_sys_gpio_bd_out_port (gpio_o[31:0]), - .a10gx_base_sys_spi_MISO (spi_miso_s), - .a10gx_base_sys_spi_MOSI (spi_mosi_s), - .a10gx_base_sys_spi_SCLK (spi_clk), - .a10gx_base_sys_spi_SS_n (spi_csn_s), - .daq2_rx_data_rx_serial_data (rx_data), - .daq2_rx_ref_clk_clk (rx_ref_clk), - .daq2_rx_sync_rx_sync (rx_sync), - .daq2_rx_sysref_rx_ext_sysref_in (rx_sysref), - .daq2_tx_data_tx_serial_data (tx_data), - .daq2_tx_ref_clk_clk (tx_ref_clk), - .daq2_tx_sync_tx_sync (tx_sync), - .daq2_tx_sysref_tx_ext_sysref_in (tx_sysref), + .rx_data_rx_serial_data (rx_data), + .rx_ref_clk_clk (rx_ref_clk), + .rx_sync_rx_sync (rx_sync), + .rx_sysref_rx_ext_sysref_in (rx_sysref), .sys_clk_clk (sys_clk), - .sys_reset_reset_n (sys_resetn)); + .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p), + .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n), + .sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]), + .sys_ddr3_cntrl_mem_mem_ba (ddr3_ba), + .sys_ddr3_cntrl_mem_mem_cke (ddr3_cke), + .sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n), + .sys_ddr3_cntrl_mem_mem_odt (ddr3_odt), + .sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n), + .sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n), + .sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n), + .sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n), + .sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]), + .sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]), + .sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]), + .sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]), + .sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq), + .sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk), + .sys_ethernet_mdio_mdc (eth_mdc), + .sys_ethernet_mdio_mdio_in (eth_mdio_i), + .sys_ethernet_mdio_mdio_out (eth_mdio_o), + .sys_ethernet_mdio_mdio_oen (eth_mdio_t), + .sys_ethernet_ref_clk_clk (eth_ref_clk), + .sys_ethernet_reset_reset (eth_reset), + .sys_ethernet_sgmii_rxp_0 (eth_rxd), + .sys_ethernet_sgmii_txp_0 (eth_txd), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_rst_reset_n (sys_resetn), + .sys_spi_MISO (spi_miso_s), + .sys_spi_MOSI (spi_mosi_s), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s), + .tx_data_tx_serial_data (tx_data), + .tx_ref_clk_clk (tx_ref_clk), + .tx_sync_tx_sync (tx_sync), + .tx_sysref_tx_ext_sysref_in (tx_sysref)); endmodule