zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fmcomms2:pr: Move project to a feature branch

main
Istvan Csomortani 2018-04-13 12:55:42 +01:00 committed by István Csomortáni
parent 43496cf80a
commit ae1ec06ce6
26 changed files with 0 additions and 4500 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

136
library/prcfg/bist/prcfg_adc.v
View File

@ -1,136 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc #(
parameter CHANNEL_ID = 0) (
input clk,
// control ports
input [31:0] control,
output reg [31:0] status,
// FIFO interface
input src_adc_enable,
input src_adc_valid,
input [15:0] src_adc_data,
output reg dst_adc_enable,
output reg dst_adc_valid,
output reg [15:0] dst_adc_data);
localparam RP_ID = 8'hA1;
reg [15:0] adc_pn_data = 0;
reg [ 3:0] mode;
reg [ 3:0] channel_sel;
wire adc_dvalid;
wire [15:0] adc_pn_data_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
// prbs function
function [15:0] pn;
input [15:0] din;
reg [15:0] dout;
begin
dout[15] = din[14] ^ din[15];
dout[14] = din[13] ^ din[14];
dout[13] = din[12] ^ din[13];
dout[12] = din[11] ^ din[12];
dout[11] = din[10] ^ din[11];
dout[10] = din[ 9] ^ din[10];
dout[ 9] = din[ 8] ^ din[ 9];
dout[ 8] = din[ 7] ^ din[ 8];
dout[ 7] = din[ 6] ^ din[ 7];
dout[ 6] = din[ 5] ^ din[ 6];
dout[ 5] = din[ 4] ^ din[ 5];
dout[ 4] = din[ 3] ^ din[ 4];
dout[ 3] = din[ 2] ^ din[ 3];
dout[ 2] = din[ 1] ^ din[ 2];
dout[ 1] = din[ 0] ^ din[ 1];
dout[ 0] = din[14] ^ din[15] ^ din[ 0];
pn = dout;
end
endfunction
assign adc_dvalid = src_adc_enable & src_adc_valid;
always @(posedge clk) begin
channel_sel <= control[3:0];
mode <= control[7:4];
end
// prbs generation
always @(posedge clk) begin
if(adc_dvalid == 1'b1) begin
adc_pn_data <= pn(adc_pn_data_s);
end
end
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? src_adc_ddata : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(32)
) i_pn_mon (
.adc_clk(clk),
.adc_valid_in(adc_dvalid),
.adc_data_in(src_adc_ddata),
.adc_data_pn(adc_pn_data),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// rx path are passed through on test mode
always @(posedge clk) begin
dst_adc_enable <= src_adc_enable;
dst_adc_data <= src_adc_data;
dst_adc_valid <= src_adc_valid;
end
// setup status bits for gpio_out
always @(posedge clk) begin
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule

185
library/prcfg/bist/prcfg_dac.v
View File

@ -1,185 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac#(
parameter CHANNEL_ID = 0) (
input clk,
// control ports
input [31:0] control,
output reg [31:0] status,
// FIFO interface
output reg src_dac_enable,
input [15:0] src_dac_data,
output reg src_dac_valid,
input dst_dac_enable,
output reg [15:0] dst_dac_data,
input dst_dac_valid);
localparam RP_ID = 8'hA1;
reg [15:0] dac_prbs = 32'hA2F19C;
reg [ 2:0] counter = 0;
reg pattern = 0;
reg [15:0] sin_tone = 0;
reg [15:0] cos_tone = 0;
reg [ 3:0] mode;
wire [15:0] dac_pattern_s;
// prbs function
function [15:0] pn;
input [15:0] din;
reg [15:0] dout;
begin
dout[15] = din[14] ^ din[15];
dout[14] = din[13] ^ din[14];
dout[13] = din[12] ^ din[13];
dout[12] = din[11] ^ din[12];
dout[11] = din[10] ^ din[11];
dout[10] = din[ 9] ^ din[10];
dout[ 9] = din[ 8] ^ din[ 9];
dout[ 8] = din[ 7] ^ din[ 8];
dout[ 7] = din[ 6] ^ din[ 7];
dout[ 6] = din[ 5] ^ din[ 6];
dout[ 5] = din[ 4] ^ din[ 5];
dout[ 4] = din[ 3] ^ din[ 4];
dout[ 3] = din[ 2] ^ din[ 3];
dout[ 2] = din[ 1] ^ din[ 2];
dout[ 1] = din[ 0] ^ din[ 1];
dout[ 0] = din[14] ^ din[15] ^ din[ 0];
pn = dout;
end
endfunction
always @(posedge clk) begin
status <= {24'h0, RP_ID};
mode <= control[7:4];
end
// sine tone generation
always @(posedge clk) begin
if ((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
counter <= counter + 1;
end
end
always @(counter) begin
case(counter)
3'd0 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h7FFF;
end
3'd1 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'h5A82;
end
3'd2 : begin
sin_tone <= 16'h7FFF;
cos_tone <= 16'h0000;
end
3'd3 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'hA57E;
end
3'd4 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h8001;
end
3'd5 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'hA57E;
end
3'd6 : begin
sin_tone <= 16'h8001;
cos_tone <= 16'h0000;
end
3'd7 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'h5A82;
end
endcase
end
// prbs generation
always @(posedge clk) begin
if((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
dac_prbs <= pn(dac_prbs);
end
end
// constant pattern generator
always @(posedge clk) begin
if((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
pattern <= ~pattern;
end
end
assign dac_pattern_s = (pattern == 1'h1) ? 16'h5555 : 16'hAAAA;
// output mux for tx side
always @(posedge clk) begin
src_dac_enable <= dst_dac_enable;
src_dac_valid <= (mode == 0) ? dst_dac_valid : 1'b0;
end
always @(posedge clk) begin
case(mode)
4'h0 : begin
dst_dac_data <= src_dac_data;
end
4'h1 : begin
dst_dac_data <= {cos_tone, sin_tone};
end
4'h2 : begin
dst_dac_data <= dac_prbs;
end
4'h3 : begin
dst_dac_data <= dac_pattern_s;
end
default : begin
dst_dac_data <= src_dac_data;
end
endcase
end
endmodule

243
library/prcfg/common/prcfg_top.v
View File

@ -1,243 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_top#(
parameter NUM_CHANNEL = 4,
parameter ADC_EN = 1,
parameter DAC_EN = 1) (
input clk,
// gpio
input [31:0] dac_gpio_input,
output [31:0] dac_gpio_output,
input [31:0] adc_gpio_input,
output [31:0] adc_gpio_output,
// TX side
input dma_dac_0_enable,
output [(DBUS_WIDTH-1):0] dma_dac_0_data,
input dma_dac_0_valid,
input dma_dac_1_enable,
output [(DBUS_WIDTH-1):0] dma_dac_1_data,
input dma_dac_1_valid,
input dma_dac_2_enable,
output [(DBUS_WIDTH-1):0] dma_dac_2_data,
input dma_dac_2_valid,
input dma_dac_3_enable,
output [(DBUS_WIDTH-1):0] dma_dac_3_data,
input dma_dac_3_valid,
output core_dac_0_enable,
input [(DBUS_WIDTH-1):0] core_dac_0_data,
output core_dac_0_valid,
output core_dac_1_enable,
input [(DBUS_WIDTH-1):0] core_dac_1_data,
output core_dac_1_valid,
output core_dac_2_enable,
input [(DBUS_WIDTH-1):0] core_dac_2_data,
output core_dac_2_valid,
output core_dac_3_enable,
input [(DBUS_WIDTH-1):0] core_dac_3_data,
output core_dac_3_valid,
// RX side
input dma_adc_0_enable,
input [(DBUS_WIDTH-1):0] dma_adc_0_data,
input dma_adc_0_valid,
input dma_adc_1_enable,
input [(DBUS_WIDTH-1):0] dma_adc_1_data,
input dma_adc_1_valid,
input dma_adc_2_enable,
input [(DBUS_WIDTH-1):0] dma_adc_2_data,
input dma_adc_2_valid,
input dma_adc_3_enable,
input [(DBUS_WIDTH-1):0] dma_adc_3_data,
input dma_adc_3_valid,
output core_adc_0_enable,
output [(DBUS_WIDTH-1):0] core_adc_0_data,
output core_adc_0_valid,
output core_adc_1_enable,
output [(DBUS_WIDTH-1):0] core_adc_1_data,
output core_adc_1_valid,
output core_adc_2_enable,
output [(DBUS_WIDTH-1):0] core_adc_2_data,
output core_adc_2_valid,
output core_adc_3_enable,
output [(DBUS_WIDTH-1):0] core_adc_3_data,
output core_adc_3_valid);
localparam ENABELED = 1;
localparam DATA_WIDTH = 16;
localparam DBUS_WIDTH = DATA_WIDTH * NUM_CHANNEL;
wire [31:0] adc_gpio_out_s[(NUM_CHANNEL - 1):0];
wire [(NUM_CHANNEL - 1):0] adc_gpio_out_s_inv[31:0];
wire [31:0] dac_gpio_out_s[(NUM_CHANNEL - 1):0];
wire [(NUM_CHANNEL - 1):0] dac_gpio_out_s_inv[31:0];
wire [(NUM_CHANNEL - 1):0] core_adc_enable_s;
wire [(NUM_CHANNEL - 1):0] core_adc_valid_s;
wire [(NUM_CHANNEL - 1):0] core_adc_data_s[15:0];
wire [(NUM_CHANNEL - 1):0] dma_adc_enable_s;
wire [(NUM_CHANNEL - 1):0] dma_adc_valid_s;
wire [(NUM_CHANNEL - 1):0] dma_adc_data_s[15:0];
wire [(NUM_CHANNEL - 1):0] core_dac_enable_s;
wire [(NUM_CHANNEL - 1):0] core_dac_valid_s;
wire [(NUM_CHANNEL - 1):0] core_dac_data_s[15:0];
wire [(NUM_CHANNEL - 1):0] dma_dac_enable_s;
wire [(NUM_CHANNEL - 1):0] dma_dac_valid_s;
wire [(NUM_CHANNEL - 1):0] dma_dac_data_s[15:0];
genvar l_inst;
generate
for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
if(ADC_EN == ENABELED) begin
prcfg_adc #(
.CHANNEL_ID(l_inst)
) i_prcfg_adc_i (
.clk(clk),
.control(adc_gpio_input),
.status(adc_gpio_out_s[l_inst]),
.src_adc_enable(core_adc_enable_s[l_inst]),
.src_adc_valid(core_adc_valid_s[l_inst]),
.src_adc_data(core_adc_data_s[l_inst]),
.dst_adc_enable(dma_adc_enable_s[l_inst]),
.dst_adc_valid(dma_adc_valid_s[l_inst]),
.dst_adc_data(dma_adc_data_s[l_inst])
);
end
if(DAC_EN == ENABELED) begin
prcfg_dac #(
.CHANNEL_ID(l_inst)
) i_prcfg_dac_i (
.clk(clk),
.control(dac_gpio_input),
.status(dac_gpio_out_s[l_inst]),
.src_dac_enable(dma_dac_enable_s[l_inst]),
.src_dac_data(dma_dac_data_s[l_inst]),
.src_dac_valid(dma_dac_valid_s[l_inst]),
.dst_dac_enable(core_dac_enable_s[l_inst]),
.dst_dac_data(core_dac_data_s[l_inst]),
.dst_dac_valid(core_dac_valid_s[l_inst])
);
end
end
endgenerate
genvar i;
genvar j;
generate
for(i = 0; i < 32; i = i + 1) begin
for(j = 0; j < NUM_CHANNEL; j = j + 1) begin
assign adc_gpio_out_s_inv[i][j] = adc_gpio_out_s[j][i];
assign dac_gpio_out_s_inv[i][j] = dac_gpio_out_s[j][i];
end
end
endgenerate
// generate gpio_outputs
generate
for(i = 0; i < 32; i = i + 1) begin
assign adc_gpio_output[i] = |adc_gpio_out_s_inv[i];
assign dac_gpio_output[i] = |dac_gpio_out_s_inv[i];
end
endgenerate
// port connections
assign core_dac_0_enable = core_dac_enable_s[0];
assign core_dac_0_valid = core_dac_valid_s[0];
assign core_dac_data_s[0] = core_dac_0_data;
assign core_dac_1_enable = core_dac_enable_s[1];
assign core_dac_1_valid = core_dac_valid_s[1];
assign core_dac_data_s[1] = core_dac_1_data;
assign core_dac_2_enable = core_dac_enable_s[2];
assign core_dac_2_valid = core_dac_valid_s[2];
assign core_dac_data_s[2] = core_dac_2_data;
assign core_dac_3_enable = core_dac_enable_s[3];
assign core_dac_3_valid = core_dac_valid_s[3];
assign core_dac_data_s[3] = core_dac_3_data;
assign dma_dac_enable_s[0] = dma_dac_0_enable;
assign dma_dac_valid_s[0] = dma_dac_0_valid;
assign dma_dac_0_data = dma_dac_data_s[0];
assign dma_dac_enable_s[1] = dma_dac_1_enable;
assign dma_dac_valid_s[1] = dma_dac_1_valid;
assign dma_dac_1_data = dma_dac_data_s[1];
assign dma_dac_enable_s[2] = dma_dac_2_enable;
assign dma_dac_valid_s[2] = dma_dac_2_valid;
assign dma_dac_2_data = dma_dac_data_s[2];
assign dma_dac_enable_s[3] = dma_dac_3_enable;
assign dma_dac_valid_s[3] = dma_dac_3_valid;
assign dma_dac_3_data = dma_dac_data_s[3];
assign core_adc_0_enable = core_adc_enable_s[0];
assign core_adc_0_valid = core_adc_valid_s[0];
assign core_adc_0_data = core_adc_data_s[0];
assign core_adc_1_enable = core_adc_enable_s[1];
assign core_adc_1_valid = core_adc_valid_s[1];
assign core_adc_1_data = core_adc_data_s[1];
assign core_adc_2_enable = core_adc_enable_s[2];
assign core_adc_2_valid = core_adc_valid_s[2];
assign core_adc_2_data = core_adc_data_s[2];
assign core_adc_3_enable = core_adc_enable_s[3];
assign core_adc_3_valid = core_adc_valid_s[3];
assign core_adc_3_data = core_adc_data_s[3];
assign dma_adc_enable_s[0] = dma_adc_0_enable;
assign dma_adc_valid_s[0] = dma_adc_0_valid;
assign dma_adc_data_s[0] = dma_adc_0_data;
assign dma_adc_enable_s[1] = dma_adc_1_enable;
assign dma_adc_valid_s[1] = dma_adc_1_valid;
assign dma_adc_data_s[1] = dma_adc_1_data;
assign dma_adc_enable_s[2] = dma_adc_2_enable;
assign dma_adc_valid_s[2] = dma_adc_2_valid;
assign dma_adc_data_s[2] = dma_adc_2_data;
assign dma_adc_enable_s[3] = dma_adc_3_enable;
assign dma_adc_valid_s[3] = dma_adc_3_valid;
assign dma_adc_data_s[3] = dma_adc_3_data;
endmodule

65
library/prcfg/default/prcfg_adc.v
View File

@ -1,65 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc #(
parameter CHANNEL_ID = 0) (
input clk,
// control ports
input [31:0] control,
output [31:0] status,
// FIFO interface
input src_adc_enable,
input src_adc_valid,
input [15:0] src_adc_data,
output reg dst_adc_enable,
output reg dst_adc_valid,
output reg [15:0] dst_adc_data);
localparam RP_ID = 8'hA0;
assign status = {24'h0, RP_ID};
always @(posedge clk) begin
dst_adc_enable <= src_adc_enable;
dst_adc_valid <= src_adc_valid;
dst_adc_data <= src_adc_data;
end
endmodule

66
library/prcfg/default/prcfg_dac.v
View File

@ -1,66 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac#(
parameter CHANNEL_ID = 0) (
input clk,
// control ports
input [31:0] control,
output [31:0] status,
// FIFO interface
output reg src_dac_enable,
input [15:0] src_dac_data,
output reg src_dac_valid,
input dst_dac_enable,
output reg [15:0] dst_dac_data,
input dst_dac_valid);
localparam RP_ID = 8'hA0;
assign status = {24'h0, RP_ID};
always @(posedge clk) begin
src_dac_enable <= dst_dac_enable;
dst_dac_data <= src_dac_data;
src_dac_valid <= dst_dac_valid;
end
endmodule

1532
library/prcfg/qpsk/FIR_Decimation.v
View File

File diff suppressed because it is too large Load Diff

436
library/prcfg/qpsk/FIR_Interpolation.v
View File

@ -1,436 +0,0 @@
// ------------------------------------------------------------
//
// File Name: hdlsrc\qpskhdltest\FIR_Interpolation
// Created: 2014-04-21 15:30:32
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// ------------------------------------------------------------
//
//
// ------------------------------------------------------------
//
// Module: FIR_Interpolation
// Source Path: /FIR_Interpolation
//
// ------------------------------------------------------------
//
// HDL Implementation : Fully parallel
// Multipliers : 6
// Folding Factor : 1
`timescale 1 ns / 1 ns
module FIR_Interpolation
(
clk,
enb_1_1_1,
reset,
FIR_Interpolation_in_re,
FIR_Interpolation_in_im,
FIR_Interpolation_out_re,
FIR_Interpolation_out_im
);
input clk;
input enb_1_1_1;
input reset;
input signed [15:0] FIR_Interpolation_in_re; //sfix16_En15
input signed [15:0] FIR_Interpolation_in_im; //sfix16_En15
output signed [15:0] FIR_Interpolation_out_re; //sfix16_En15
output signed [15:0] FIR_Interpolation_out_im; //sfix16_En15
////////////////////////////////////////////////////////////////
//Module Architecture: FIR_Interpolation
////////////////////////////////////////////////////////////////
// Local Functions
// Type Definitions
// Constants
parameter signed [15:0] coeffphase1_1 = 16'b1111111100110010; //sfix16_En16
parameter signed [15:0] coeffphase1_2 = 16'b1111111000101100; //sfix16_En16
parameter signed [15:0] coeffphase1_3 = 16'b1111100001010001; //sfix16_En16
parameter signed [15:0] coeffphase1_4 = 16'b0111001100111111; //sfix16_En16
parameter signed [15:0] coeffphase1_5 = 16'b1111100001010001; //sfix16_En16
parameter signed [15:0] coeffphase1_6 = 16'b1111111000101100; //sfix16_En16
parameter signed [15:0] coeffphase1_7 = 16'b1111111100110010; //sfix16_En16
parameter signed [15:0] coeffphase2_1 = 16'b1111111101100001; //sfix16_En16
parameter signed [15:0] coeffphase2_2 = 16'b1111111010000110; //sfix16_En16
parameter signed [15:0] coeffphase2_3 = 16'b1111100011000010; //sfix16_En16
parameter signed [15:0] coeffphase2_4 = 16'b0110110010100111; //sfix16_En16
parameter signed [15:0] coeffphase2_5 = 16'b1111101111000100; //sfix16_En16
parameter signed [15:0] coeffphase2_6 = 16'b1111111011011011; //sfix16_En16
parameter signed [15:0] coeffphase2_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_1 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_2 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_3 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_4 = 16'b0101101010000011; //sfix16_En16
parameter signed [15:0] coeffphase3_5 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_6 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase3_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase4_1 = 16'b0000000010111111; //sfix16_En16
parameter signed [15:0] coeffphase4_2 = 16'b0000000111111010; //sfix16_En16
parameter signed [15:0] coeffphase4_3 = 16'b0000111110000110; //sfix16_En16
parameter signed [15:0] coeffphase4_4 = 16'b0100000100110001; //sfix16_En16
parameter signed [15:0] coeffphase4_5 = 16'b0000001011001001; //sfix16_En16
parameter signed [15:0] coeffphase4_6 = 16'b0000000011101010; //sfix16_En16
parameter signed [15:0] coeffphase4_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase5_1 = 16'b0000000100101010; //sfix16_En16
parameter signed [15:0] coeffphase5_2 = 16'b0000001101001011; //sfix16_En16
parameter signed [15:0] coeffphase5_3 = 16'b0010011001101010; //sfix16_En16
parameter signed [15:0] coeffphase5_4 = 16'b0010011001101010; //sfix16_En16
parameter signed [15:0] coeffphase5_5 = 16'b0000001101001011; //sfix16_En16
parameter signed [15:0] coeffphase5_6 = 16'b0000000100101010; //sfix16_En16
parameter signed [15:0] coeffphase5_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase6_1 = 16'b0000000011101010; //sfix16_En16
parameter signed [15:0] coeffphase6_2 = 16'b0000001011001001; //sfix16_En16
parameter signed [15:0] coeffphase6_3 = 16'b0100000100110001; //sfix16_En16
parameter signed [15:0] coeffphase6_4 = 16'b0000111110000110; //sfix16_En16
parameter signed [15:0] coeffphase6_5 = 16'b0000000111111010; //sfix16_En16
parameter signed [15:0] coeffphase6_6 = 16'b0000000010111111; //sfix16_En16
parameter signed [15:0] coeffphase6_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_1 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_2 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_3 = 16'b0101101010000011; //sfix16_En16
parameter signed [15:0] coeffphase7_4 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_5 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_6 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase7_7 = 16'b0000000000000000; //sfix16_En16
parameter signed [15:0] coeffphase8_1 = 16'b1111111011011011; //sfix16_En16
parameter signed [15:0] coeffphase8_2 = 16'b1111101111000100; //sfix16_En16
parameter signed [15:0] coeffphase8_3 = 16'b0110110010100111; //sfix16_En16
parameter signed [15:0] coeffphase8_4 = 16'b1111100011000010; //sfix16_En16
parameter signed [15:0] coeffphase8_5 = 16'b1111111010000110; //sfix16_En16
parameter signed [15:0] coeffphase8_6 = 16'b1111111101100001; //sfix16_En16
parameter signed [15:0] coeffphase8_7 = 16'b0000000000000000; //sfix16_En16
// Signals
reg [2:0] cur_count; // ufix3
wire phase_7; // boolean
reg signed [15:0] delay_pipeline_re [0:5] ; // sfix16_En15
reg signed [15:0] delay_pipeline_im [0:5] ; // sfix16_En15
wire signed [15:0] product_re; // sfix16_En15
wire signed [15:0] product_im; // sfix16_En15
wire signed [15:0] product_mux; // sfix16_En16
wire signed [31:0] mul_temp; // sfix32_En31
wire signed [31:0] mul_temp_1; // sfix32_En31
wire signed [15:0] product_1_re; // sfix16_En15
wire signed [15:0] product_1_im; // sfix16_En15
wire signed [15:0] product_mux_1; // sfix16_En16
wire signed [31:0] mul_temp_2; // sfix32_En31
wire signed [31:0] mul_temp_3; // sfix32_En31
wire signed [15:0] product_2_re; // sfix16_En15
wire signed [15:0] product_2_im; // sfix16_En15
wire signed [15:0] product_mux_2; // sfix16_En16
wire signed [31:0] mul_temp_4; // sfix32_En31
wire signed [31:0] mul_temp_5; // sfix32_En31
wire signed [15:0] product_3_re; // sfix16_En15
wire signed [15:0] product_3_im; // sfix16_En15
wire signed [15:0] product_mux_3; // sfix16_En16
wire signed [31:0] mul_temp_6; // sfix32_En31
wire signed [31:0] mul_temp_7; // sfix32_En31
wire signed [15:0] product_4_re; // sfix16_En15
wire signed [15:0] product_4_im; // sfix16_En15
wire signed [15:0] product_mux_4; // sfix16_En16
wire signed [31:0] mul_temp_8; // sfix32_En31
wire signed [31:0] mul_temp_9; // sfix32_En31
wire signed [15:0] product_5_re; // sfix16_En15
wire signed [15:0] product_5_im; // sfix16_En15
wire signed [15:0] product_mux_5; // sfix16_En16
wire signed [31:0] mul_temp_10; // sfix32_En31
wire signed [31:0] mul_temp_11; // sfix32_En31
wire signed [15:0] product_6_re; // sfix16_En15
wire signed [15:0] product_6_im; // sfix16_En15
wire signed [15:0] product_mux_6; // sfix16_En16
wire signed [31:0] mul_temp_12; // sfix32_En31
wire signed [31:0] mul_temp_13; // sfix32_En31
wire signed [15:0] sum1_re; // sfix16_En15
wire signed [15:0] sum1_im; // sfix16_En15
wire signed [15:0] add_cast; // sfix16_En15
wire signed [15:0] add_cast_1; // sfix16_En15
wire signed [16:0] add_temp; // sfix17_En15
wire signed [15:0] add_cast_2; // sfix16_En15
wire signed [15:0] add_cast_3; // sfix16_En15
wire signed [16:0] add_temp_1; // sfix17_En15
wire signed [15:0] sum2_re; // sfix16_En15
wire signed [15:0] sum2_im; // sfix16_En15
wire signed [15:0] add_cast_4; // sfix16_En15
wire signed [15:0] add_cast_5; // sfix16_En15
wire signed [16:0] add_temp_2; // sfix17_En15
wire signed [15:0] add_cast_6; // sfix16_En15
wire signed [15:0] add_cast_7; // sfix16_En15
wire signed [16:0] add_temp_3; // sfix17_En15
wire signed [15:0] sum3_re; // sfix16_En15
wire signed [15:0] sum3_im; // sfix16_En15
wire signed [15:0] add_cast_8; // sfix16_En15
wire signed [15:0] add_cast_9; // sfix16_En15
wire signed [16:0] add_temp_4; // sfix17_En15
wire signed [15:0] add_cast_10; // sfix16_En15
wire signed [15:0] add_cast_11; // sfix16_En15
wire signed [16:0] add_temp_5; // sfix17_En15
wire signed [15:0] sum4_re; // sfix16_En15
wire signed [15:0] sum4_im; // sfix16_En15
wire signed [15:0] add_cast_12; // sfix16_En15
wire signed [15:0] add_cast_13; // sfix16_En15
wire signed [16:0] add_temp_6; // sfix17_En15
wire signed [15:0] add_cast_14; // sfix16_En15
wire signed [15:0] add_cast_15; // sfix16_En15
wire signed [16:0] add_temp_7; // sfix17_En15
wire signed [15:0] sum5_re; // sfix16_En15
wire signed [15:0] sum5_im; // sfix16_En15
wire signed [15:0] add_cast_16; // sfix16_En15
wire signed [15:0] add_cast_17; // sfix16_En15
wire signed [16:0] add_temp_8; // sfix17_En15
wire signed [15:0] add_cast_18; // sfix16_En15
wire signed [15:0] add_cast_19; // sfix16_En15
wire signed [16:0] add_temp_9; // sfix17_En15
wire signed [15:0] sum6_re; // sfix16_En15
wire signed [15:0] sum6_im; // sfix16_En15
wire signed [15:0] add_cast_20; // sfix16_En15
wire signed [15:0] add_cast_21; // sfix16_En15
wire signed [16:0] add_temp_10; // sfix17_En15
wire signed [15:0] add_cast_22; // sfix16_En15
wire signed [15:0] add_cast_23; // sfix16_En15
wire signed [16:0] add_temp_11; // sfix17_En15
reg signed [15:0] regout_re; // sfix16_En15
reg signed [15:0] regout_im; // sfix16_En15
wire signed [15:0] muxout_re; // sfix16_En15
wire signed [15:0] muxout_im; // sfix16_En15
// Block Statements
always @ (posedge clk or posedge reset)
begin: ce_output
if (reset == 1'b1) begin
cur_count <= 3'b000;
end
else begin
if (enb_1_1_1 == 1'b1) begin
if (cur_count == 3'b111) begin
cur_count <= 3'b000;
end
else begin
cur_count <= cur_count + 1;
end
end
end
end // ce_output
assign phase_7 = (cur_count == 3'b111 && enb_1_1_1 == 1'b1)? 1 : 0;
// ---------------- Delay Registers ----------------
always @( posedge clk or posedge reset)
begin: Delay_Pipeline_process
if (reset == 1'b1) begin
delay_pipeline_re[0] <= 0;
delay_pipeline_re[1] <= 0;
delay_pipeline_re[2] <= 0;
delay_pipeline_re[3] <= 0;
delay_pipeline_re[4] <= 0;
delay_pipeline_re[5] <= 0;
delay_pipeline_im[0] <= 0;
delay_pipeline_im[1] <= 0;
delay_pipeline_im[2] <= 0;
delay_pipeline_im[3] <= 0;
delay_pipeline_im[4] <= 0;
delay_pipeline_im[5] <= 0;
end
else begin
if (phase_7 == 1'b1) begin
delay_pipeline_re[0] <= FIR_Interpolation_in_re;
delay_pipeline_re[1] <= delay_pipeline_re[0];
delay_pipeline_re[2] <= delay_pipeline_re[1];
delay_pipeline_re[3] <= delay_pipeline_re[2];
delay_pipeline_re[4] <= delay_pipeline_re[3];
delay_pipeline_re[5] <= delay_pipeline_re[4];
delay_pipeline_im[0] <= FIR_Interpolation_in_im;
delay_pipeline_im[1] <= delay_pipeline_im[0];
delay_pipeline_im[2] <= delay_pipeline_im[1];
delay_pipeline_im[3] <= delay_pipeline_im[2];
delay_pipeline_im[4] <= delay_pipeline_im[3];
delay_pipeline_im[5] <= delay_pipeline_im[4];
end
end
end // Delay_Pipeline_process
assign product_mux = (cur_count == 3'b000) ? coeffphase1_7 :
(cur_count == 3'b001) ? coeffphase2_7 :
(cur_count == 3'b010) ? coeffphase3_7 :
(cur_count == 3'b011) ? coeffphase4_7 :
(cur_count == 3'b100) ? coeffphase5_7 :
(cur_count == 3'b101) ? coeffphase6_7 :
(cur_count == 3'b110) ? coeffphase7_7 :
coeffphase8_7;
assign mul_temp = delay_pipeline_re[5] * product_mux;
assign product_re = mul_temp[31:16];
assign mul_temp_1 = delay_pipeline_im[5] * product_mux;
assign product_im = mul_temp_1[31:16];
assign product_mux_1 = (cur_count == 3'b000) ? coeffphase1_6 :
(cur_count == 3'b001) ? coeffphase2_6 :
(cur_count == 3'b010) ? coeffphase3_6 :
(cur_count == 3'b011) ? coeffphase4_6 :
(cur_count == 3'b100) ? coeffphase5_6 :
(cur_count == 3'b101) ? coeffphase6_6 :
(cur_count == 3'b110) ? coeffphase7_6 :
coeffphase8_6;
assign mul_temp_2 = delay_pipeline_re[4] * product_mux_1;
assign product_1_re = mul_temp_2[31:16];
assign mul_temp_3 = delay_pipeline_im[4] * product_mux_1;
assign product_1_im = mul_temp_3[31:16];
assign product_mux_2 = (cur_count == 3'b000) ? coeffphase1_5 :
(cur_count == 3'b001) ? coeffphase2_5 :
(cur_count == 3'b010) ? coeffphase3_5 :
(cur_count == 3'b011) ? coeffphase4_5 :
(cur_count == 3'b100) ? coeffphase5_5 :
(cur_count == 3'b101) ? coeffphase6_5 :
(cur_count == 3'b110) ? coeffphase7_5 :
coeffphase8_5;
assign mul_temp_4 = delay_pipeline_re[3] * product_mux_2;
assign product_2_re = mul_temp_4[31:16];
assign mul_temp_5 = delay_pipeline_im[3] * product_mux_2;
assign product_2_im = mul_temp_5[31:16];
assign product_mux_3 = (cur_count == 3'b000) ? coeffphase1_4 :
(cur_count == 3'b001) ? coeffphase2_4 :
(cur_count == 3'b010) ? coeffphase3_4 :
(cur_count == 3'b011) ? coeffphase4_4 :
(cur_count == 3'b100) ? coeffphase5_4 :
(cur_count == 3'b101) ? coeffphase6_4 :
(cur_count == 3'b110) ? coeffphase7_4 :
coeffphase8_4;
assign mul_temp_6 = delay_pipeline_re[2] * product_mux_3;
assign product_3_re = mul_temp_6[31:16];
assign mul_temp_7 = delay_pipeline_im[2] * product_mux_3;
assign product_3_im = mul_temp_7[31:16];
assign product_mux_4 = (cur_count == 3'b000) ? coeffphase1_3 :
(cur_count == 3'b001) ? coeffphase2_3 :
(cur_count == 3'b010) ? coeffphase3_3 :
(cur_count == 3'b011) ? coeffphase4_3 :
(cur_count == 3'b100) ? coeffphase5_3 :
(cur_count == 3'b101) ? coeffphase6_3 :
(cur_count == 3'b110) ? coeffphase7_3 :
coeffphase8_3;
assign mul_temp_8 = delay_pipeline_re[1] * product_mux_4;
assign product_4_re = mul_temp_8[31:16];
assign mul_temp_9 = delay_pipeline_im[1] * product_mux_4;
assign product_4_im = mul_temp_9[31:16];
assign product_mux_5 = (cur_count == 3'b000) ? coeffphase1_2 :
(cur_count == 3'b001) ? coeffphase2_2 :
(cur_count == 3'b010) ? coeffphase3_2 :
(cur_count == 3'b011) ? coeffphase4_2 :
(cur_count == 3'b100) ? coeffphase5_2 :
(cur_count == 3'b101) ? coeffphase6_2 :
(cur_count == 3'b110) ? coeffphase7_2 :
coeffphase8_2;
assign mul_temp_10 = delay_pipeline_re[0] * product_mux_5;
assign product_5_re = mul_temp_10[31:16];
assign mul_temp_11 = delay_pipeline_im[0] * product_mux_5;
assign product_5_im = mul_temp_11[31:16];
assign product_mux_6 = (cur_count == 3'b000) ? coeffphase1_1 :
(cur_count == 3'b001) ? coeffphase2_1 :
(cur_count == 3'b010) ? coeffphase3_1 :
(cur_count == 3'b011) ? coeffphase4_1 :
(cur_count == 3'b100) ? coeffphase5_1 :
(cur_count == 3'b101) ? coeffphase6_1 :
(cur_count == 3'b110) ? coeffphase7_1 :
coeffphase8_1;
assign mul_temp_12 = FIR_Interpolation_in_re * product_mux_6;
assign product_6_re = mul_temp_12[31:16];
assign mul_temp_13 = FIR_Interpolation_in_im * product_mux_6;
assign product_6_im = mul_temp_13[31:16];
assign add_cast = product_6_re;
assign add_cast_1 = product_5_re;
assign add_temp = add_cast + add_cast_1;
assign sum1_re = add_temp[15:0];
assign add_cast_2 = product_6_im;
assign add_cast_3 = product_5_im;
assign add_temp_1 = add_cast_2 + add_cast_3;
assign sum1_im = add_temp_1[15:0];
assign add_cast_4 = sum1_re;
assign add_cast_5 = product_4_re;
assign add_temp_2 = add_cast_4 + add_cast_5;
assign sum2_re = add_temp_2[15:0];
assign add_cast_6 = sum1_im;
assign add_cast_7 = product_4_im;
assign add_temp_3 = add_cast_6 + add_cast_7;
assign sum2_im = add_temp_3[15:0];
assign add_cast_8 = sum2_re;
assign add_cast_9 = product_3_re;
assign add_temp_4 = add_cast_8 + add_cast_9;
assign sum3_re = add_temp_4[15:0];
assign add_cast_10 = sum2_im;
assign add_cast_11 = product_3_im;
assign add_temp_5 = add_cast_10 + add_cast_11;
assign sum3_im = add_temp_5[15:0];
assign add_cast_12 = sum3_re;
assign add_cast_13 = product_2_re;
assign add_temp_6 = add_cast_12 + add_cast_13;
assign sum4_re = add_temp_6[15:0];
assign add_cast_14 = sum3_im;
assign add_cast_15 = product_2_im;
assign add_temp_7 = add_cast_14 + add_cast_15;
assign sum4_im = add_temp_7[15:0];
assign add_cast_16 = sum4_re;
assign add_cast_17 = product_1_re;
assign add_temp_8 = add_cast_16 + add_cast_17;
assign sum5_re = add_temp_8[15:0];
assign add_cast_18 = sum4_im;
assign add_cast_19 = product_1_im;
assign add_temp_9 = add_cast_18 + add_cast_19;
assign sum5_im = add_temp_9[15:0];
assign add_cast_20 = sum5_re;
assign add_cast_21 = product_re;
assign add_temp_10 = add_cast_20 + add_cast_21;
assign sum6_re = add_temp_10[15:0];
assign add_cast_22 = sum5_im;
assign add_cast_23 = product_im;
assign add_temp_11 = add_cast_22 + add_cast_23;
assign sum6_im = add_temp_11[15:0];
always @ (posedge clk or posedge reset)
begin: DataHoldRegister_process
if (reset == 1'b1) begin
regout_re <= 0;
regout_im <= 0;
end
else begin
if (enb_1_1_1 == 1'b1) begin
regout_re <= sum6_re;
regout_im <= sum6_im;
end
end
end // DataHoldRegister_process
assign muxout_re = (enb_1_1_1 == 1'b1) ? sum6_re :
regout_re;
assign muxout_im = (enb_1_1_1 == 1'b1) ? sum6_im :
regout_im;
// Assignment Statements
assign FIR_Interpolation_out_re = muxout_re;
assign FIR_Interpolation_out_im = muxout_im;
endmodule // FIR_Interpolation

90
library/prcfg/qpsk/QPSK_Demodulator_Baseband.v
View File

@ -1,90 +0,0 @@
// -------------------------------------------------------------
//
// File Name: hdlsrc\qpskhdltest\QPSK_Demodulator_Baseband.v
// Created: 2014-04-21 15:30:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: QPSK_Demodulator_Baseband
// Source Path: qpskhdltest/QPSK Demodulator Baseband
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module QPSK_Demodulator_Baseband
(
in0_re,
in0_im,
out0
);
input signed [15:0] in0_re; // sfix16_En15
input signed [15:0] in0_im; // sfix16_En15
output [1:0] out0; // ufix2
wire inphase_lt_zero;
wire inphase_eq_zero;
wire quadrature_lt_zero;
wire quadrature_eq_zero;
wire [3:0] decisionLUTaddr; // ufix4
wire [1:0] DirectLookupTable_1 [0:15]; // ufix2 [16]
wire [1:0] hardDecision; // ufix2
assign inphase_lt_zero = (in0_re < 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign inphase_eq_zero = (in0_re == 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign quadrature_lt_zero = (in0_im < 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign quadrature_eq_zero = (in0_im == 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign decisionLUTaddr = {inphase_lt_zero, inphase_eq_zero, quadrature_lt_zero, quadrature_eq_zero};
assign DirectLookupTable_1[0] = 2'b00;
assign DirectLookupTable_1[1] = 2'b00;
assign DirectLookupTable_1[2] = 2'b10;
assign DirectLookupTable_1[3] = 2'b00;
assign DirectLookupTable_1[4] = 2'b01;
assign DirectLookupTable_1[5] = 2'b00;
assign DirectLookupTable_1[6] = 2'b10;
assign DirectLookupTable_1[7] = 2'b00;
assign DirectLookupTable_1[8] = 2'b01;
assign DirectLookupTable_1[9] = 2'b11;
assign DirectLookupTable_1[10] = 2'b11;
assign DirectLookupTable_1[11] = 2'b00;
assign DirectLookupTable_1[12] = 2'b00;
assign DirectLookupTable_1[13] = 2'b00;
assign DirectLookupTable_1[14] = 2'b00;
assign DirectLookupTable_1[15] = 2'b00;
assign hardDecision = DirectLookupTable_1[decisionLUTaddr];
assign out0 = hardDecision;
endmodule // QPSK_Demodulator_Baseband

65
library/prcfg/qpsk/QPSK_Modulator_Baseband.v
View File

@ -1,65 +0,0 @@
// -------------------------------------------------------------
//
// File Name: hdlsrc\qpsk\QPSK_Modulator_Baseband.v
// Created: 2014-10-24 12:50:40
//
// Generated by MATLAB 8.3 and HDL Coder 3.4
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: QPSK_Modulator_Baseband
// Source Path: qpsk/Subsystem/QPSK Modulator Baseband
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module QPSK_Modulator_Baseband
(
in0,
out0_re,
out0_im
);
input [7:0] in0; // uint8
output signed [15:0] out0_re; // sfix16_En15
output signed [15:0] out0_im; // sfix16_En15
parameter signed [15:0] t1_re_0 = 23170; // sfix16
parameter signed [15:0] t1_re_1 = -23170; // sfix16
parameter signed [15:0] t1_re_2 = 23170; // sfix16
parameter signed [15:0] t1_re_3 = -23170; // sfix16
parameter signed [15:0] t1_im_0 = 23170; // sfix16
parameter signed [15:0] t1_im_1 = 23170; // sfix16
parameter signed [15:0] t1_im_2 = -23170; // sfix16
parameter signed [15:0] t1_im_3 = -23170; // sfix16
wire [1:0] constellationLUTaddress; // ufix2
wire signed [15:0] constellationLUT_t1_re [0:3]; // sfix16_En15 [4]
wire signed [15:0] constellationLUT_t1_im [0:3]; // sfix16_En15 [4]
assign constellationLUTaddress = in0[1:0];
assign constellationLUT_t1_re[0] = t1_re_0;
assign constellationLUT_t1_re[1] = t1_re_1;
assign constellationLUT_t1_re[2] = t1_re_2;
assign constellationLUT_t1_re[3] = t1_re_3;
assign constellationLUT_t1_im[0] = t1_im_0;
assign constellationLUT_t1_im[1] = t1_im_1;
assign constellationLUT_t1_im[2] = t1_im_2;
assign constellationLUT_t1_im[3] = t1_im_3;
assign out0_re = constellationLUT_t1_re[constellationLUTaddress];
assign out0_im = constellationLUT_t1_im[constellationLUTaddress];
endmodule // QPSK_Modulator_Baseband

60
library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v
View File

@ -1,60 +0,0 @@
// -------------------------------------------------------------
//
// File Name: hdlsrc\qpsk\Raised_Cosine_Receive_Filter.v
// Created: 2014-10-24 12:50:39
//
// Generated by MATLAB 8.3 and HDL Coder 3.4
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Raised_Cosine_Receive_Filter
// Source Path: qpsk/Subsystem/Raised Cosine Receive Filter
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Raised_Cosine_Receive_Filter
(
clk,
reset,
enb_1_1_1,
In1_re,
In1_im,
Out1_re,
Out1_im
);
input clk;
input reset;
input enb_1_1_1;
input signed [15:0] In1_re; // sfix16_En15
input signed [15:0] In1_im; // sfix16_En15
output signed [15:0] Out1_re; // sfix16_En15
output signed [15:0] Out1_im; // sfix16_En15
wire signed [15:0] FIR_Decimation_out1_re; // sfix16_En15
wire signed [15:0] FIR_Decimation_out1_im; // sfix16_En15
FIR_Decimation u_FIR_Decimation (.clk(clk),
.enb_1_1_1(enb_1_1_1),
.reset(reset),
.FIR_Decimation_in_re(In1_re), // sfix16_En15
.FIR_Decimation_in_im(In1_im), // sfix16_En15
.FIR_Decimation_out_re(FIR_Decimation_out1_re), // sfix16_En15
.FIR_Decimation_out_im(FIR_Decimation_out1_im) // sfix16_En15
);
assign Out1_re = FIR_Decimation_out1_re;
assign Out1_im = FIR_Decimation_out1_im;
endmodule // Raised_Cosine_Receive_Filter

60
library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v
View File

@ -1,60 +0,0 @@
// -------------------------------------------------------------
//
// File Name: hdlsrc\qpsk\Raised_Cosine_Transmit_Filter.v
// Created: 2014-10-24 12:50:40
//
// Generated by MATLAB 8.3 and HDL Coder 3.4
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Raised_Cosine_Transmit_Filter
// Source Path: qpsk/Subsystem/Raised Cosine Transmit Filter
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Raised_Cosine_Transmit_Filter
(
clk,
reset,
enb_1_1_1,
In1_re,
In1_im,
Out1_re,
Out1_im
);
input clk;
input reset;
input enb_1_1_1;
input signed [15:0] In1_re; // sfix16_En15
input signed [15:0] In1_im; // sfix16_En15
output signed [15:0] Out1_re; // sfix16_En15
output signed [15:0] Out1_im; // sfix16_En15
wire signed [15:0] FIR_Interpolation_out1_re; // sfix16_En15
wire signed [15:0] FIR_Interpolation_out1_im; // sfix16_En15
FIR_Interpolation u_FIR_Interpolation (.clk(clk),
.enb_1_1_1(enb_1_1_1),
.reset(reset),
.FIR_Interpolation_in_re(In1_re), // sfix16_En15
.FIR_Interpolation_in_im(In1_im), // sfix16_En15
.FIR_Interpolation_out_re(FIR_Interpolation_out1_re), // sfix16_En15
.FIR_Interpolation_out_im(FIR_Interpolation_out1_im) // sfix16_En15
);
assign Out1_re = FIR_Interpolation_out1_re;
assign Out1_im = FIR_Interpolation_out1_im;
endmodule // Raised_Cosine_Transmit_Filter

154
library/prcfg/qpsk/prcfg_adc.v
View File

@ -1,154 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_adc #(
parameter CHANNEL_ID = 0,
parameter DATA_WIDTH = 32) (
input clk,
// control ports
input [31:0] control,
output reg [31:0] status,
// FIFO interface
input src_adc_valid,
input [(DATA_WIDTH-1):0] src_adc_data,
input src_adc_enable,
output reg dst_adc_valid,
output reg [(DATA_WIDTH-1):0] dst_adc_data,
output reg dst_adc_enable);
localparam SYMBOL_WIDTH = 2;
localparam RP_ID = 8'hA2;
reg [ 7:0] adc_pn_data = 'hF1;
reg [ 3:0] mode = 'h0;
reg [ 3:0] channel_sel = 'h0;
wire adc_valid;
wire [(SYMBOL_WIDTH-1):0] adc_data_s;
wire [ 7:0] adc_pn_data_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
reg [ 7:0] dout;
begin
dout[7] = din[6];
dout[6] = din[5];
dout[5] = din[4];
dout[4] = din[3];
dout[3] = din[2];
dout[2] = din[1];
dout[1] = din[7] ^ din[4];
dout[0] = din[6] ^ din[3];
pn = dout;
end
endfunction
// update control and status registers
always @(posedge clk) begin
channel_sel <= control[ 3:0];
mode <= control[ 7:4];
end
assign adc_valid = src_adc_valid & src_adc_enable;
assign adc_pn_data_s = (adc_pn_oos_s == 1'b1) ? {adc_pn_data[7:2], adc_data_s} : adc_pn_data;
ad_pnmon #(
.DATA_WIDTH(8)
) i_pn_mon (
.adc_clk(clk),
.adc_valid_in(adc_valid),
.adc_data_in({adc_pn_data[7:2], adc_data_s}),
.adc_data_pn(adc_pn_data_s),
.adc_pn_oos(adc_pn_oos_s),
.adc_pn_err(adc_pn_err_s));
// prbs generation
always @(posedge clk) begin
if(adc_valid == 1'b1) begin
adc_pn_data <= pn(adc_pn_data);
end
end
// qpsk demodulator
qpsk_demod i_qpsk_demod1 (
.clk(clk),
.data_qpsk_i(src_adc_data[15: 0]),
.data_qpsk_q(src_adc_data[31:16]),
.data_valid(adc_valid),
.data_output(adc_data_s)
);
// output logic for data ans status
always @(posedge clk) begin
dst_adc_valid <= src_adc_valid;
dst_adc_enable <= src_adc_enable;
case(mode)
4'h0 : begin
dst_adc_data <= src_adc_data;
end
4'h1 : begin
dst_adc_data <= 32'h0;
end
4'h2 : begin
dst_adc_data <= {30'h0, adc_data_s};
end
default : begin
dst_adc_data <= src_adc_data;
end
endcase
if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
end else begin
status <= {24'h0, RP_ID};
end
end
endmodule

137
library/prcfg/qpsk/prcfg_dac.v
View File

@ -1,137 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac#(
parameter CHANNEL_ID = 0,
parameter DATA_WIDTH = 16) (
input clk,
// control ports
input [31:0] control,
output reg [31:0] status,
// FIFO interface
output reg src_dac_enable,
input [(DATA_WIDTH-1):0] src_dac_data,
output reg src_dac_valid,
input dst_dac_enable,
output reg [(DATA_WIDTH-1):0] dst_dac_data,
input dst_dac_valid);
localparam SYMBOL_WIDTH = 2;
localparam RP_ID = 8'hA2;
// output register to improve timing
// internal registers
reg [ 7:0] pn_data = 'hF2;
reg [ 3:0] mode = 'h0;
// internal wires
wire [(SYMBOL_WIDTH-1):0] mod_data;
wire [15:0] dac_data_fltr_i;
wire [15:0] dac_data_fltr_q;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
reg [ 7:0] dout;
begin
dout[7] = din[6];
dout[6] = din[5];
dout[5] = din[4];
dout[4] = din[3];
dout[3] = din[2];
dout[2] = din[1];
dout[1] = din[7] ^ din[4];
dout[0] = din[6] ^ din[3];
pn = dout;
end
endfunction
// update control and status registers
always @(posedge clk) begin
status <= { 24'h0, RP_ID };
mode <= control[ 7:4];
end
// prbs generation
always @(posedge clk) begin
if((dst_dac_en == 1) && (dst_dac_enable == 1)) begin
pn_data <= pn(pn_data);
end
end
// data for the modulator (prbs or dma)
assign mod_data = (mode == 1) ? pn_data[ 1:0] : src_dac_data[ 1:0];
// qpsk modulator
qpsk_mod i_qpsk_mod (
.clk(clk),
.data_input(mod_data),
.data_valid(dst_dac_en),
.data_qpsk_i(dac_data_fltr_i),
.data_qpsk_q(dac_data_fltr_q)
);
// output logic
always @(posedge clk) begin
src_dac_enable <= dst_dac_en;
src_dac_valid <= dst_dac_valid;
case(mode)
4'h0 : begin
dst_dac_data <= src_dac_data;
end
4'h1 : begin
dst_dac_data <= { dac_data_fltr_q, dac_data_fltr_i };
end
4'h2 : begin
dst_dac_data <= { dac_data_fltr_q, dac_data_fltr_i };
end
default : begin
end
endcase
end
endmodule

BIN
library/prcfg/qpsk/qpsk.slx
View File

Binary file not shown.

68
library/prcfg/qpsk/qpsk_demod.v
View File

@ -1,68 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module qpsk_demod (
input clk,
input [15:0] data_qpsk_i,
input [15:0] data_qpsk_q,
input data_valid,
output [ 1:0] data_output);
wire [15:0] filtered_data_i;
wire [15:0] filtered_data_q;
wire [ 7:0] demodulated_data;
// output logic
assign data_output = demodulated_data[1:0];
// instantiation
Raised_Cosine_Receive_Filter i_rx_filter (
.clk(clk),
.reset(1'b0),
.enb_1_1_1(data_valid),
.In1_re(data_qpsk_i),
.In1_im(data_qpsk_q),
.Out1_re(filtered_data_i),
.Out1_im(filtered_data_q)
);
QPSK_Demodulator_Baseband i_qpsk_demod(
.in0_re(filtered_data_i),
.in0_im(filtered_data_q),
.out0(demodulated_data)
);
endmodule

70
library/prcfg/qpsk/qpsk_mod.v
View File

@ -1,70 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module qpsk_mod (
input clk,
input [ 1:0] data_input,
input data_valid,
output [15:0] data_qpsk_i,
output [15:0] data_qpsk_q);
wire [15:0] modulated_data_i;
wire [15:0] modulated_data_q;
wire [15:0] filtered_data_i;
wire [15:0] filtered_data_q;
// output logic
assign data_qpsk_i = filtered_data_i;
assign data_qpsk_q = filtered_data_q;
// instantiations
QPSK_Modulator_Baseband i_qpsk_mod (
.in0({6'b0, data_input}),
.out0_re(modulated_data_i),
.out0_im(modulated_data_q)
);
Raised_Cosine_Transmit_Filter i_tx_filter (
.clk(clk),
.reset(),
.enb_1_1_1(data_valid),
.In1_re(modulated_data_i),
.In1_im(modulated_data_q),
.Out1_re(filtered_data_i),
.Out1_im(filtered_data_q)
);
endmodule

175
projects/fmcomms2/common/prcfg.v
View File

@ -1,175 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg (
input clk,
// gpio
input [31:0] dac_gpio_input,
output [31:0] dac_gpio_output,
input [31:0] adc_gpio_input,
output [31:0] adc_gpio_output,
// tx side
input dma_dac_i0_enable,
output [15:0] dma_dac_i0_data,
input dma_dac_i0_valid,
input dma_dac_q0_enable,
output [15:0] dma_dac_q0_data,
input dma_dac_q0_valid,
input dma_dac_i1_enable,
output [15:0] dma_dac_i1_data,
input dma_dac_i1_valid,
input dma_dac_q1_enable,
output [15:0] dma_dac_q1_data,
input dma_dac_q1_valid,
output core_dac_i0_enable,
input [15:0] core_dac_i0_data,
output core_dac_i0_valid,
output core_dac_q0_enable,
input [15:0] core_dac_q0_data,
output core_dac_q0_valid,
output core_dac_i1_enable,
input [15:0] core_dac_i1_data,
output core_dac_i1_valid,
output core_dac_q1_enable,
input [15:0] core_dac_q1_data,
output core_dac_q1_valid,
// rx side
input dma_adc_i0_enable,
input [15:0] dma_adc_i0_data,
input dma_adc_i0_valid,
input dma_adc_q0_enable,
input [15:0] dma_adc_q0_data,
input dma_adc_q0_valid,
input dma_adc_i1_enable,
input [15:0] dma_adc_i1_data,
input dma_adc_i1_valid,
input dma_adc_q1_enable,
input [15:0] dma_adc_q1_data,
input dma_adc_q1_valid,
output core_adc_i0_enable,
output [15:0] core_adc_i0_data,
output core_adc_i0_valid,
output core_adc_q0_enable,
output [15:0] core_adc_q0_data,
output core_adc_q0_valid,
output core_adc_i1_enable,
output [15:0] core_adc_i1_data,
output core_adc_i1_valid,
output core_adc_q1_enable,
output [15:0] core_adc_q1_data,
output core_adc_q1_valid);
// fmcomms2 configuration
localparam NUM_OF_CHANNELS = 4;
localparam ADC_ENABLE = 1;
localparam DAC_ENABLE = 1;
// default top
prcfg_top # (
.NUM_CHANNEL (NUM_OF_CHANNELS),
.ADC_EN (ADC_ENABLE),
.DAC_EN (DAC_ENABLE))
i_prcfg_top (
.clk (clk),
.dac_gpio_input (dac_gpio_input),
.dac_gpio_output (dac_gpio_output),
.adc_gpio_input (adc_gpio_input),
.adc_gpio_output (adc_gpio_output),
.dma_dac_0_enable (dma_dac_i0_enable),
.dma_dac_0_data (dma_dac_i0_data),
.dma_dac_0_valid (dma_dac_i0_valid),
.dma_dac_1_enable (dma_dac_q0_enable),
.dma_dac_1_data (dma_dac_q0_data),
.dma_dac_1_valid (dma_dac_q0_valid),
.dma_dac_2_enable (dma_dac_i1_enable),
.dma_dac_2_data (dma_dac_i1_data),
.dma_dac_2_valid (dma_dac_i1_valid),
.dma_dac_3_enable (dma_dac_q1_enable),
.dma_dac_3_data (dma_dac_q1_data),
.dma_dac_3_valid (dma_dac_q1_valid),
.core_dac_0_enable (core_dac_i0_enable),
.core_dac_0_data (core_dac_i0_data),
.core_dac_0_valid (core_dac_i0_valid),
.core_dac_1_enable (core_dac_q0_enable),
.core_dac_1_data (core_dac_q0_data),
.core_dac_1_valid (core_dac_q0_valid),
.core_dac_2_enable (core_dac_i1_enable),
.core_dac_2_data (core_dac_i1_data),
.core_dac_2_valid (core_dac_i1_valid),
.core_dac_3_enable (core_dac_q1_enable),
.core_dac_3_data (core_dac_q1_data),
.core_dac_3_valid (core_dac_q1_valid),
.dma_adc_0_enable (dma_adc_i0_enable),
.dma_adc_0_data (dma_adc_i0_data),
.dma_adc_0_valid (dma_adc_i0_valid),
.dma_adc_1_enable (dma_adc_q0_enable),
.dma_adc_1_data (dma_adc_q0_data),
.dma_adc_1_valid (dma_adc_q0_valid),
.dma_adc_2_enable (dma_adc_i1_enable),
.dma_adc_2_data (dma_adc_i1_data),
.dma_adc_2_valid (dma_adc_i1_valid),
.dma_adc_3_enable (dma_adc_q1_enable),
.dma_adc_3_data (dma_adc_q1_data),
.dma_adc_3_valid (dma_adc_q1_valid),
.core_adc_0_enable (core_adc_i0_enable),
.core_adc_0_data (core_adc_i0_data),
.core_adc_0_valid (core_adc_i0_valid),
.core_adc_1_enable (core_adc_q0_enable),
.core_adc_1_data (core_adc_q0_data),
.core_adc_1_valid (core_adc_q0_valid),
.core_adc_2_enable (core_adc_i1_enable),
.core_adc_2_data (core_adc_i1_data),
.core_adc_2_valid (core_adc_i1_valid),
.core_adc_3_enable (core_adc_q1_enable),
.core_adc_3_data (core_adc_q1_data),
.core_adc_3_valid (core_adc_q1_valid));
endmodule
// ***************************************************************************
// ***************************************************************************

16
projects/fmcomms2/common/prcfg.xdc
View File

@ -1,16 +0,0 @@
create_pblock pb_prcfg
add_cells_to_pblock [get_pblocks pb_prcfg] [get_cells -quiet [list i_prcfg]]
resize_pblock [get_pblocks pb_prcfg] -add {SLICE_X90Y0:SLICE_X161Y149}
resize_pblock [get_pblocks pb_prcfg] -add {SLICE_X90Y150:SLICE_X122Y199}
resize_pblock [get_pblocks pb_prcfg] -add {RAMB18_X4Y0:RAMB18_X7Y59}
resize_pblock [get_pblocks pb_prcfg] -add {RAMB18_X4Y60:RAMB18_X4Y79}
resize_pblock [get_pblocks pb_prcfg] -add {RAMB36_X4Y0:RAMB36_X7Y29}
resize_pblock [get_pblocks pb_prcfg] -add {DSP48_X4Y0:DSP48_X6Y59}
resize_pblock [get_pblocks pb_prcfg] -add {DSP48_X4Y60:DSP48_X4Y79}
set_property SNAPPING_MODE ON [get_pblocks pb_prcfg]
set_property RESET_AFTER_RECONFIG 1 [get_pblocks pb_prcfg]

101
projects/fmcomms2/common/prcfg_bb.v
View File

@ -1,101 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// black box definition for pr module
`timescale 1ns/100ps
(* black_box *)
module prcfg (
input clk,
input [31:0] adc_gpio_input,
output [31:0] adc_gpio_output,
input [31:0] dac_gpio_input,
output [31:0] dac_gpio_output,
input dma_dac_i0_enable,
output [15:0] dma_dac_i0_data,
input dma_dac_i0_valid,
input dma_dac_q0_enable,
output [15:0] dma_dac_q0_data,
input dma_dac_q0_valid,
input dma_dac_i1_enable,
output [15:0] dma_dac_i1_data,
input dma_dac_i1_valid,
input dma_dac_q1_enable,
output [15:0] dma_dac_q1_data,
input dma_dac_q1_valid,
output core_dac_i0_enable,
input [15:0] core_dac_i0_data,
output core_dac_i0_valid,
output core_dac_q0_enable,
input [15:0] core_dac_q0_data,
output core_dac_q0_valid,
output core_dac_i1_enable,
input [15:0] core_dac_i1_data,
output core_dac_i1_valid,
output core_dac_q1_enable,
input [15:0] core_dac_q1_data,
output core_dac_q1_valid,
input dma_adc_i0_enable,
input [15:0] dma_adc_i0_data,
input dma_adc_i0_valid,
input dma_adc_q0_enable,
input [15:0] dma_adc_q0_data,
input dma_adc_q0_valid,
input dma_adc_i1_enable,
input [15:0] dma_adc_i1_data,
input dma_adc_i1_valid,
input dma_adc_q1_enable,
input [15:0] dma_adc_q1_data,
input dma_adc_q1_valid,
output core_adc_i0_enable,
output [15:0] core_adc_i0_data,
output core_adc_i0_valid,
output core_adc_q0_enable,
output [15:0] core_adc_q0_data,
output core_adc_q0_valid,
output core_adc_i1_enable,
output [15:0] core_adc_i1_data,
output core_adc_i1_valid,
output core_adc_q1_enable,
output [15:0] core_adc_q1_data,
output core_adc_q1_valid
);
endmodule
// ***************************************************************************
// ***************************************************************************

121
projects/fmcomms2/common/prcfg_bd.tcl
View File

@ -1,121 +0,0 @@
# prcfg io
create_bd_port -dir O clk
create_bd_port -dir O core_dac_i0_enable
create_bd_port -dir O core_dac_q0_enable
create_bd_port -dir O core_dac_i1_enable
create_bd_port -dir O core_dac_q1_enable
create_bd_port -dir O core_dac_i0_valid
create_bd_port -dir O core_dac_q0_valid
create_bd_port -dir O core_dac_i1_valid
create_bd_port -dir O core_dac_q1_valid
create_bd_port -dir I -from 15 -to 0 core_dac_i0_data
create_bd_port -dir I -from 15 -to 0 core_dac_q0_data
create_bd_port -dir I -from 15 -to 0 core_dac_i1_data
create_bd_port -dir I -from 15 -to 0 core_dac_q1_data
create_bd_port -dir I dma_dac_i0_enable
create_bd_port -dir I dma_dac_q0_enable
create_bd_port -dir I dma_dac_i1_enable
create_bd_port -dir I dma_dac_q1_enable
create_bd_port -dir I dma_dac_i0_valid
create_bd_port -dir I dma_dac_q0_valid
create_bd_port -dir I dma_dac_i1_valid
create_bd_port -dir I dma_dac_q1_valid
create_bd_port -dir O -from 15 -to 0 dma_dac_i0_data
create_bd_port -dir O -from 15 -to 0 dma_dac_q0_data
create_bd_port -dir O -from 15 -to 0 dma_dac_i1_data
create_bd_port -dir O -from 15 -to 0 dma_dac_q1_data
create_bd_port -dir O core_adc_i0_enable
create_bd_port -dir O core_adc_q0_enable
create_bd_port -dir O core_adc_i1_enable
create_bd_port -dir O core_adc_q1_enable
create_bd_port -dir O core_adc_i0_valid
create_bd_port -dir O core_adc_q0_valid
create_bd_port -dir O core_adc_i1_valid
create_bd_port -dir O core_adc_q1_valid
create_bd_port -dir O -from 15 -to 0 core_adc_i0_data
create_bd_port -dir O -from 15 -to 0 core_adc_q0_data
create_bd_port -dir O -from 15 -to 0 core_adc_i1_data
create_bd_port -dir O -from 15 -to 0 core_adc_q1_data
create_bd_port -dir I dma_adc_i0_enable
create_bd_port -dir I dma_adc_q0_enable
create_bd_port -dir I dma_adc_i1_enable
create_bd_port -dir I dma_adc_q1_enable
create_bd_port -dir I dma_adc_i0_valid
create_bd_port -dir I dma_adc_q0_valid
create_bd_port -dir I dma_adc_i1_valid
create_bd_port -dir I dma_adc_q1_valid
create_bd_port -dir I -from 15 -to 0 dma_adc_i0_data
create_bd_port -dir I -from 15 -to 0 dma_adc_q0_data
create_bd_port -dir I -from 15 -to 0 dma_adc_i1_data
create_bd_port -dir I -from 15 -to 0 dma_adc_q1_data
create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in
create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in
create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out
create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out
# re-wiring, split between ad9361 core & upack/cpack modules
ad_connect axi_ad9361_clk clk
ad_reconct util_ad9361_dac_upack/dac_enable_0 dma_dac_i0_enable
ad_reconct util_ad9361_dac_upack/dac_enable_1 dma_dac_q0_enable
ad_reconct util_ad9361_dac_upack/dac_enable_2 dma_dac_i1_enable
ad_reconct util_ad9361_dac_upack/dac_enable_3 dma_dac_q1_enable
ad_reconct util_ad9361_dac_upack/dac_valid_0 dma_dac_i0_valid
ad_reconct util_ad9361_dac_upack/dac_valid_1 dma_dac_q0_valid
ad_reconct util_ad9361_dac_upack/dac_valid_2 dma_dac_i1_valid
ad_reconct util_ad9361_dac_upack/dac_valid_3 dma_dac_q1_valid
ad_reconct util_ad9361_dac_upack/dac_data_0 dma_dac_i0_data
ad_reconct util_ad9361_dac_upack/dac_data_1 dma_dac_q0_data
ad_reconct util_ad9361_dac_upack/dac_data_2 dma_dac_i1_data
ad_reconct util_ad9361_dac_upack/dac_data_3 dma_dac_q1_data
ad_reconct axi_ad9361/dac_enable_i0 core_dac_i0_enable
ad_reconct axi_ad9361/dac_enable_q0 core_dac_q0_enable
ad_reconct axi_ad9361/dac_enable_i1 core_dac_i1_enable
ad_reconct axi_ad9361/dac_enable_q1 core_dac_q1_enable
ad_reconct axi_ad9361/dac_valid_i0 core_dac_i0_valid
ad_reconct axi_ad9361/dac_valid_q0 core_dac_q0_valid
ad_reconct axi_ad9361/dac_valid_i1 core_dac_i1_valid
ad_reconct axi_ad9361/dac_valid_q1 core_dac_q1_valid
ad_reconct axi_ad9361/dac_data_i0 core_dac_i0_data
ad_reconct axi_ad9361/dac_data_q0 core_dac_q0_data
ad_reconct axi_ad9361/dac_data_i1 core_dac_i1_data
ad_reconct axi_ad9361/dac_data_q1 core_dac_q1_data
ad_reconct util_ad9361_adc_fifo/din_enable_0 dma_adc_i0_enable
ad_reconct util_ad9361_adc_fifo/din_enable_1 dma_adc_q0_enable
ad_reconct util_ad9361_adc_fifo/din_enable_2 dma_adc_i1_enable
ad_reconct util_ad9361_adc_fifo/din_enable_3 dma_adc_q1_enable
ad_reconct util_ad9361_adc_fifo/din_valid_0 dma_adc_i0_valid
ad_reconct util_ad9361_adc_fifo/din_valid_1 dma_adc_q0_valid
ad_reconct util_ad9361_adc_fifo/din_valid_2 dma_adc_i1_valid
ad_reconct util_ad9361_adc_fifo/din_valid_3 dma_adc_q1_valid
ad_reconct util_ad9361_adc_fifo/din_data_0 dma_adc_i0_data
ad_reconct util_ad9361_adc_fifo/din_data_1 dma_adc_q0_data
ad_reconct util_ad9361_adc_fifo/din_data_2 dma_adc_i1_data
ad_reconct util_ad9361_adc_fifo/din_data_3 dma_adc_q1_data
ad_reconct axi_ad9361/adc_enable_i0 core_adc_i0_enable
ad_reconct axi_ad9361/adc_enable_q0 core_adc_q0_enable
ad_reconct axi_ad9361/adc_enable_i1 core_adc_i1_enable
ad_reconct axi_ad9361/adc_enable_q1 core_adc_q1_enable
ad_reconct axi_ad9361/adc_valid_i0 core_adc_i0_valid
ad_reconct axi_ad9361/adc_valid_q0 core_adc_q0_valid
ad_reconct axi_ad9361/adc_valid_i1 core_adc_i1_valid
ad_reconct axi_ad9361/adc_valid_q1 core_adc_q1_valid
ad_reconct axi_ad9361/adc_data_i0 core_adc_i0_data
ad_reconct axi_ad9361/adc_data_q0 core_adc_q0_data
ad_reconct axi_ad9361/adc_data_i1 core_adc_i1_data
ad_reconct axi_ad9361/adc_data_q1 core_adc_q1_data
ad_reconct axi_ad9361/up_dac_gpio_in up_dac_gpio_in
ad_reconct axi_ad9361/up_adc_gpio_in up_adc_gpio_in
ad_reconct axi_ad9361/up_dac_gpio_out up_dac_gpio_out
ad_reconct axi_ad9361/up_adc_gpio_out up_adc_gpio_out

47
projects/fmcomms2/zc706pr/Makefile
View File

@ -1,47 +0,0 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := fmcomms2_zc706
M_DEPS += ../zc706/system_constr.xdc
M_DEPS += ../zc706/system_bd.tcl
M_DEPS += ../common/prcfg_bd.tcl
M_DEPS += ../common/prcfg_bb.v
M_DEPS += ../common/prcfg.xdc
M_DEPS += ../common/prcfg.v
M_DEPS += ../common/fmcomms2_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/prcfg/qpsk/qpsk_mod.v
M_DEPS += ../../../library/prcfg/qpsk/qpsk_demod.v
M_DEPS += ../../../library/prcfg/qpsk/prcfg_dac.v
M_DEPS += ../../../library/prcfg/qpsk/prcfg_adc.v
M_DEPS += ../../../library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v
M_DEPS += ../../../library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v
M_DEPS += ../../../library/prcfg/qpsk/QPSK_Modulator_Baseband.v
M_DEPS += ../../../library/prcfg/qpsk/QPSK_Demodulator_Baseband.v
M_DEPS += ../../../library/prcfg/qpsk/FIR_Interpolation.v
M_DEPS += ../../../library/prcfg/qpsk/FIR_Decimation.v
M_DEPS += ../../../library/prcfg/default/prcfg_dac.v
M_DEPS += ../../../library/prcfg/default/prcfg_adc.v
M_DEPS += ../../../library/prcfg/common/prcfg_top.v
M_DEPS += ../../../library/prcfg/bist/prcfg_dac.v
M_DEPS += ../../../library/prcfg/bist/prcfg_adc.v
M_DEPS += ../../../library/common/ad_pnmon.v
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_clkdiv
LIB_DEPS += util_cpack
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_upack
LIB_DEPS += util_wfifo
include ../../scripts/project-xilinx.mk

4
projects/fmcomms2/zc706pr/system_bd.tcl
View File

@ -1,4 +0,0 @@
source ../zc706/system_bd.tcl
source ../common/prcfg_bd.tcl

0
projects/fmcomms2/zc706pr/system_constr.xdc
View File

72
projects/fmcomms2/zc706pr/system_project.tcl
View File

@ -1,72 +0,0 @@
## requires partial reconfiguration license
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set mode 1
if {$::argc > 0} {
set mode [lindex $argv 0]
}
if {$mode == 0} {
adi_project_xilinx fmcomms2_zc706
adi_project_files fmcomms2_zc706 [list \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \
"$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \
"$ad_hdl_dir/library/prcfg/default/prcfg_adc.v" \
"../common/prcfg.v" \
"../zc706/system_constr.xdc" \
"system_top.v" ]
adi_project_run fmcomms2_zc706
return
}
adi_project_xilinx fmcomms2_zc706 1
adi_project_synth fmcomms2_zc706 "" \
[list "system_top.v" \
"../common/prcfg_bb.v" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] \
[list "../zc706/system_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
adi_project_synth fmcomms2_zc706 "default" \
[list "../common/prcfg.v" \
"$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \
"$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \
"$ad_hdl_dir/library/prcfg/default/prcfg_adc.v"]
adi_project_impl fmcomms2_zc706 "default" \
[list "../common/prcfg.xdc" \
"system_constr.xdc"]
adi_project_synth fmcomms2_zc706 "bist" \
[list "../common/prcfg.v" \
"$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/prcfg/bist/prcfg_dac.v" \
"$ad_hdl_dir/library/prcfg/bist/prcfg_adc.v"]
adi_project_impl fmcomms2_zc706 "bist" "system_constr.xdc"
adi_project_synth fmcomms2_zc706 "qpsk" \
[list "../common/prcfg.v" \
"$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/prcfg/qpsk/prcfg_dac.v" \
"$ad_hdl_dir/library/prcfg/qpsk/prcfg_adc.v" \
"$ad_hdl_dir/library/prcfg/qpsk/qpsk_mod.v" \
"$ad_hdl_dir/library/prcfg/qpsk/qpsk_demod.v" \
"$ad_hdl_dir/library/prcfg/qpsk/QPSK_Modulator_Baseband.v" \
"$ad_hdl_dir/library/prcfg/qpsk/QPSK_Demodulator_Baseband.v" \
"$ad_hdl_dir/library/prcfg/qpsk/FIR_Interpolation.v" \
"$ad_hdl_dir/library/prcfg/qpsk/FIR_Decimation.v" \
"$ad_hdl_dir/library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v" \
"$ad_hdl_dir/library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v"]
adi_project_impl fmcomms2_zc706 "qpsk" "system_constr.xdc"
adi_project_verify fmcomms2_zc706

396
projects/fmcomms2/zc706pr/system_top.v
View File

@ -1,396 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
inout iic_scl,
inout iic_sda,
input rx_clk_in_p,
input rx_clk_in_n,
input rx_frame_in_p,
input rx_frame_in_n,
input [ 5:0] rx_data_in_p,
input [ 5:0] rx_data_in_n,
output tx_clk_out_p,
output tx_clk_out_n,
output tx_frame_out_p,
output tx_frame_out_n,
output [ 5:0] tx_data_out_p,
output [ 5:0] tx_data_out_n,
output enable,
output txnrx,
inout tdd_sync,
inout gpio_muxout_tx,
inout gpio_muxout_rx,
inout gpio_resetb,
inout gpio_sync,
inout gpio_en_agc,
inout [ 3:0] gpio_ctl,
inout [ 7:0] gpio_status,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso,
output spi_udc_csn_tx,
output spi_udc_csn_rx,
output spi_udc_sclk,
output spi_udc_data);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire clk;
wire dma_dac_i0_enable;
wire [15:0] dma_dac_i0_data;
wire dma_dac_i0_valid;
wire dma_dac_q0_enable;
wire [15:0] dma_dac_q0_data;
wire dma_dac_q0_valid;
wire dma_dac_i1_enable;
wire [15:0] dma_dac_i1_data;
wire dma_dac_i1_valid;
wire dma_dac_q1_enable;
wire [15:0] dma_dac_q1_data;
wire dma_dac_q1_valid;
wire core_dac_i0_enable;
wire [15:0] core_dac_i0_data;
wire core_dac_i0_valid;
wire core_dac_q0_enable;
wire [15:0] core_dac_q0_data;
wire core_dac_q0_valid;
wire core_dac_i1_enable;
wire [15:0] core_dac_i1_data;
wire core_dac_i1_valid;
wire core_dac_q1_enable;
wire [15:0] core_dac_q1_data;
wire core_dac_q1_valid;
wire dma_adc_i0_enable;
wire [15:0] dma_adc_i0_data;
wire dma_adc_i0_valid;
wire dma_adc_q0_enable;
wire [15:0] dma_adc_q0_data;
wire dma_adc_q0_valid;
wire dma_adc_i1_enable;
wire [15:0] dma_adc_i1_data;
wire dma_adc_i1_valid;
wire dma_adc_q1_enable;
wire [15:0] dma_adc_q1_data;
wire dma_adc_q1_valid;
wire core_adc_i0_enable;
wire [15:0] core_adc_i0_data;
wire core_adc_i0_valid;
wire core_adc_q0_enable;
wire [15:0] core_adc_q0_data;
wire core_adc_q0_valid;
wire core_adc_i1_enable;
wire [15:0] core_adc_i1_data;
wire core_adc_i1_valid;
wire core_adc_q1_enable;
wire [15:0] core_adc_q1_data;
wire core_adc_q1_valid;
wire [31:0] adc_gpio_input;
wire [31:0] adc_gpio_output;
wire [31:0] dac_gpio_input;
wire [31:0] dac_gpio_output;
wire tdd_sync_t;
wire tdd_sync_o;
wire tdd_sync_i;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t ({gpio_t[50:49], gpio_t[46:32]}),
.dio_i ({gpio_o[50:49], gpio_o[46:32]}),
.dio_o ({gpio_i[50:49], gpio_i[46:32]}),
.dio_p ({ gpio_muxout_tx, // 50:50
gpio_muxout_rx, // 49:49
gpio_resetb, // 46:46
gpio_sync, // 45:45
gpio_en_agc, // 44:44
gpio_ctl, // 43:40
gpio_status})); // 39:32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
.dio_t (tdd_sync_t),
.dio_i (tdd_sync_o),
.dio_o (tdd_sync_i),
.dio_p (tdd_sync));
// prcfg instance
prcfg i_prcfg (
.clk (clk),
.adc_gpio_input (adc_gpio_input),
.adc_gpio_output (adc_gpio_output),
.dac_gpio_input (dac_gpio_input),
.dac_gpio_output (dac_gpio_output),
.dma_dac_i0_enable (dma_dac_i0_enable),
.dma_dac_i0_data (dma_dac_i0_data),
.dma_dac_i0_valid (dma_dac_i0_valid),
.dma_dac_q0_enable (dma_dac_q0_enable),
.dma_dac_q0_data (dma_dac_q0_data),
.dma_dac_q0_valid (dma_dac_q0_valid),
.dma_dac_i1_enable (dma_dac_i1_enable),
.dma_dac_i1_data (dma_dac_i1_data),
.dma_dac_i1_valid (dma_dac_i1_valid),
.dma_dac_q1_enable (dma_dac_q1_enable),
.dma_dac_q1_data (dma_dac_q1_data),
.dma_dac_q1_valid (dma_dac_q1_valid),
.core_dac_i0_enable (core_dac_i0_enable),
.core_dac_i0_data (core_dac_i0_data),
.core_dac_i0_valid (core_dac_i0_valid),
.core_dac_q0_enable (core_dac_q0_enable),
.core_dac_q0_data (core_dac_q0_data),
.core_dac_q0_valid (core_dac_q0_valid),
.core_dac_i1_enable (core_dac_i1_enable),
.core_dac_i1_data (core_dac_i1_data),
.core_dac_i1_valid (core_dac_i1_valid),
.core_dac_q1_enable (core_dac_q1_enable),
.core_dac_q1_data (core_dac_q1_data),
.core_dac_q1_valid (core_dac_q1_valid),
.dma_adc_i0_enable (dma_adc_i0_enable),
.dma_adc_i0_data (dma_adc_i0_data),
.dma_adc_i0_valid (dma_adc_i0_valid),
.dma_adc_q0_enable (dma_adc_q0_enable),
.dma_adc_q0_data (dma_adc_q0_data),
.dma_adc_q0_valid (dma_adc_q0_valid),
.dma_adc_i1_enable (dma_adc_i1_enable),
.dma_adc_i1_data (dma_adc_i1_data),
.dma_adc_i1_valid (dma_adc_i1_valid),
.dma_adc_q1_enable (dma_adc_q1_enable),
.dma_adc_q1_data (dma_adc_q1_data),
.dma_adc_q1_valid (dma_adc_q1_valid),
.core_adc_i0_enable (core_adc_i0_enable),
.core_adc_i0_data (core_adc_i0_data),
.core_adc_i0_valid (core_adc_i0_valid),
.core_adc_q0_enable (core_adc_q0_enable),
.core_adc_q0_data (core_adc_q0_data),
.core_adc_q0_valid (core_adc_q0_valid),
.core_adc_i1_enable (core_adc_i1_enable),
.core_adc_i1_data (core_adc_i1_data),
.core_adc_i1_valid (core_adc_i1_valid),
.core_adc_q1_enable (core_adc_q1_enable),
.core_adc_q1_data (core_adc_q1_data),
.core_adc_q1_valid (core_adc_q1_valid));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.rx_clk_in_n (rx_clk_in_n),
.rx_clk_in_p (rx_clk_in_p),
.rx_data_in_n (rx_data_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_frame_in_p (rx_frame_in_p),
.spdif (spdif),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (spi_udc_sclk),
.spi1_csn_0_o (spi_udc_csn_tx),
.spi1_csn_1_o (spi_udc_csn_rx),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (spi_udc_data),
.spi1_sdo_o (spi_udc_data),
.tdd_sync_i (tdd_sync_i),
.tdd_sync_o (tdd_sync_o),
.tdd_sync_t (tdd_sync_t),
.tx_clk_out_n (tx_clk_out_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx),
.up_enable (gpio_o[47]),
.up_txnrx (gpio_o[48]),
.clk (clk),
.up_adc_gpio_in (adc_gpio_input),
.up_adc_gpio_out (adc_gpio_output),
.up_dac_gpio_in (dac_gpio_input),
.up_dac_gpio_out (dac_gpio_output),
.dma_dac_i0_enable (dma_dac_i0_enable),
.dma_dac_i0_data (dma_dac_i0_data),
.dma_dac_i0_valid (dma_dac_i0_valid),
.dma_dac_q0_enable (dma_dac_q0_enable),
.dma_dac_q0_data (dma_dac_q0_data),
.dma_dac_q0_valid (dma_dac_q0_valid),
.dma_dac_i1_enable (dma_dac_i1_enable),
.dma_dac_i1_data (dma_dac_i1_data),
.dma_dac_i1_valid (dma_dac_i1_valid),
.dma_dac_q1_enable (dma_dac_q1_enable),
.dma_dac_q1_data (dma_dac_q1_data),
.dma_dac_q1_valid (dma_dac_q1_valid),
.core_dac_i0_enable (core_dac_i0_enable),
.core_dac_i0_data (core_dac_i0_data),
.core_dac_i0_valid (core_dac_i0_valid),
.core_dac_q0_enable (core_dac_q0_enable),
.core_dac_q0_data (core_dac_q0_data),
.core_dac_q0_valid (core_dac_q0_valid),
.core_dac_i1_enable (core_dac_i1_enable),
.core_dac_i1_data (core_dac_i1_data),
.core_dac_i1_valid (core_dac_i1_valid),
.core_dac_q1_enable (core_dac_q1_enable),
.core_dac_q1_data (core_dac_q1_data),
.core_dac_q1_valid (core_dac_q1_valid),
.dma_adc_i0_enable (dma_adc_i0_enable),
.dma_adc_i0_data (dma_adc_i0_data),
.dma_adc_i0_valid (dma_adc_i0_valid),
.dma_adc_q0_enable (dma_adc_q0_enable),
.dma_adc_q0_data (dma_adc_q0_data),
.dma_adc_q0_valid (dma_adc_q0_valid),
.dma_adc_i1_enable (dma_adc_i1_enable),
.dma_adc_i1_data (dma_adc_i1_data),
.dma_adc_i1_valid (dma_adc_i1_valid),
.dma_adc_q1_enable (dma_adc_q1_enable),
.dma_adc_q1_data (dma_adc_q1_data),
.dma_adc_q1_valid (dma_adc_q1_valid),
.core_adc_i0_enable (core_adc_i0_enable),
.core_adc_i0_data (core_adc_i0_data),
.core_adc_i0_valid (core_adc_i0_valid),
.core_adc_q0_enable (core_adc_q0_enable),
.core_adc_q0_data (core_adc_q0_data),
.core_adc_q0_valid (core_adc_q0_valid),
.core_adc_i1_enable (core_adc_i1_enable),
.core_adc_i1_data (core_adc_i1_data),
.core_adc_i1_valid (core_adc_i1_valid),
.core_adc_q1_enable (core_adc_q1_enable),
.core_adc_q1_data (core_adc_q1_data),
.core_adc_q1_valid (core_adc_q1_valid));
endmodule
// ***************************************************************************
// ***************************************************************************

201
projects/scripts/adi_prcfg_project.tcl
View File

@ -1,201 +0,0 @@
#-------------------------------------------------------------------------------
# Processes for non-project mode development flow used for partial reconfiguration
#-------------------------------------------------------------------------------
# Initialize the workspace
proc prcfg_init_workspace {prcfg_name_list} {
# directory names
set static_dir "prcfg_static"
set sdk_dir "sdk_export"
# make/clean all directory for design files
if {![file exists $static_dir]} {
file mkdir $static_dir
} else {
file delete -force $static_dir
file mkdir $static_dir
}
foreach i $prcfg_name_list {
if {![file exists prcfg_$i]} {
file mkdir prcfg_$i
} else {
file delete -force prcfg_$i
file mkdir prcfg_$i
}
}
if {![file exists $sdk_dir]} {
file mkdir $sdk_dir
} else {
file delete -force $sdk_dir
file mkdir $sdk_dir
}
}
# Create and synthesize the static part of the project
proc prcfg_synth_static { verilog_files xdc_files } {
global ad_hdl_dir
global ad_phdl_dir
global part
global board
# location of the generated block design file
set system_project_dir ".srcs/sources_1/bd/system"
# create project in mememory
create_project -in_memory -part $part
set_property board $board [current_project]
# setup repo for library
set lib_dirs $ad_hdl_dir/library
lappend lib_dirs $ad_phdl_dir/library
set_property ip_repo_paths $lib_dirs [current_fileset]
update_ip_catalog
# create bd design
create_bd_design "system"
source system_bd.tcl
generate_target all [get_files $system_project_dir/system.bd]
make_wrapper -files [get_files $system_project_dir/system.bd] -top
read_verilog $system_project_dir/hdl/system_wrapper.v
# add project files
read_verilog $verilog_files
read_xdc $xdc_files
# run shyntesis
file mkdir "./prcfg_static/logs"
synth_design -mode default -top system_top -part $part > "./prcfg_static/logs/synth_static.rds"
# generate hardware specification file for sdk
export_hardware [get_files .srcs/sources_1/bd/system/system.bd] -dir "./sdk_export"
# write checkpoint
file mkdir "./prcfg_static/checkpoints"
write_checkpoint -force "./prcfg_static/checkpoints/synth_static.dcp"
close_project
}
# Create and synthesize the reconfigurable part of the project
proc prcfg_synth_reconf { prcfg_name verilog_files } {
global ad_hdl_dir
global ad_phdl_dir
global part
create_project -in_memory -part $part
# add project files
read_verilog $verilog_files
# run OOC synthesis
file mkdir "./prcfg_${prcfg_name}/logs"
synth_design -mode out_of_context -top "prcfg_system_top" -part $part > "./prcfg_${prcfg_name}/logs/synth_${prcfg_name}.rds"
# write checkpoint
file mkdir "./prcfg_${prcfg_name}/checkpoints"
write_checkpoint -force "./prcfg_${prcfg_name}/checkpoints/synth_${prcfg_name}.dcp"
close_project
}
# Make the implementation of the project
proc prcfg_impl { xdc_file reconfig_name_list } {
global part
for { set i 0 } { $i < [llength $reconfig_name_list] } { incr i } {
set prcfg_name [lindex $reconfig_name_list $i]
if { $i == 0 } {
open_checkpoint "./prcfg_static/checkpoints/synth_static.dcp" -part $part
# Create the RP area on the fabric and load the default logic on it
read_xdc $xdc_file
read_checkpoint -cell i_prcfg_system_top "./prcfg_${prcfg_name}/checkpoints/synth_${prcfg_name}.dcp"
set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg_system_top]
# implement the first configurations
opt_design > "./prcfg_${prcfg_name}/logs/opt_${prcfg_name}.rds"
# generate ltx file for debug probes
write_debug_probes -force "./debug_nets.ltx"
place_design > "./prcfg_${prcfg_name}/logs/place_${prcfg_name}.rds"
route_design > "./prcfg_${prcfg_name}/logs/route_${prcfg_name}.rds"
# save results
save_results $prcfg_name
# clear out RM
update_design -cell i_prcfg_system_top -black_box
# save static-only route
write_checkpoint -force "./prcfg_static/checkpoints/route_static_only.dcp"
close_project
} else {
open_checkpoint "./prcfg_static/checkpoints/route_static_only.dcp" -part $part
# implement the next configuration
# with the static-only design loaded in memory, lock down all placement and route
lock_design -level routing
read_checkpoint -cell i_prcfg_system_top "./prcfg_${prcfg_name}/checkpoints/synth_${prcfg_name}.dcp"
opt_design > "./prcfg_${prcfg_name}/logs/opt_${prcfg_name}.rds"
place_design > "./prcfg_${prcfg_name}/logs/place_${prcfg_name}.rds"
route_design > "./prcfg_${prcfg_name}/logs/route_${prcfg_name}.rds"
# save results
save_results $prcfg_name
close_project
}
}
}
# Save the result of an implementation, generate reports
proc save_results { prcfg_name } {
file mkdir "./prcfg_${prcfg_name}/results"
# checkpoint to the routed design
write_checkpoint -force "./prcfg_${prcfg_name}/results/top_route_design.dcp"
# reports
report_utilization -pblocks pblock_adi -file "./prcfg_${prcfg_name}/results/top_utilization.rpt"
report_timing_summary -file "./prcfg_${prcfg_name}/results/top_timing_summary.rpt"
# checkpoint to the routed RP
write_checkpoint -force -cell i_prcfg_system_top "./prcfg_${prcfg_name}/checkpoints/route_rm_${prcfg_name}.dcp"
}
# Verify the compatibility of different configurations
proc prcfg_verify { prcfg_name_list } {
file mkdir "./verify_design"
set prcfg_init_path "./prcfg_[lindex $prcfg_name_list 0]/results/top_route_design.dcp"
set prcfg_additional_paths ""
for {set i 1} {$i < [llength $prcfg_name_list]} {incr i} {
lappend prcfg_additional_paths "./prcfg_[lindex $prcfg_name_list $i]/results/top_route_design.dcp"
}
pr_verify -full_check -initial $prcfg_init_path -additional $prcfg_additional_paths -file ./verify_design/pr_verify.log
}
# Generate bitstream
proc prcfg_gen_bit { prcfg_name_list } {
global part
foreach i $prcfg_name_list {
open_checkpoint "./prcfg_${i}/results/top_route_design.dcp" -part $part
file mkdir "./prcfg_${i}/bit"
write_bitstream -force -bin_file -file "./prcfg_${i}/bit/config_${i}.bit"
close_project
}
}