From ae4e7a0c37a4ac7db5f9cef8e32a8124561e980b Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 10 Apr 2015 09:43:16 +0200 Subject: [PATCH] util_axis_fifo: Add option to disable registered output Add a option to specify whether the FIFO should have a registered output stage or not. This is useful if the user wants to implement that stage itself. Signed-off-by: Lars-Peter Clausen --- library/util_axis_fifo/util_axis_fifo.v | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v index 2ccc6c10d..9b8c914a7 100644 --- a/library/util_axis_fifo/util_axis_fifo.v +++ b/library/util_axis_fifo/util_axis_fifo.v @@ -54,6 +54,7 @@ module util_axis_fifo ( parameter C_DATA_WIDTH = 64; parameter C_CLKS_ASYNC = 1; parameter C_ADDRESS_WIDTH = 4; +parameter C_S_AXIS_REGISTERED = 1; generate if (C_ADDRESS_WIDTH == 0) begin @@ -168,6 +169,8 @@ always @(posedge s_axis_aclk) begin ram[s_axis_waddr] <= s_axis_data; end +if (C_S_AXIS_REGISTERED == 1) begin + reg [C_DATA_WIDTH-1:0] data; reg valid; @@ -191,6 +194,14 @@ assign _m_axis_ready = ~valid || m_axis_ready; assign m_axis_data = data; assign m_axis_valid = valid; +end else begin + +assign _m_axis_ready = m_axis_ready; +assign m_axis_valid = _m_axis_valid; +assign m_axis_data = ram[m_axis_raddr]; + +end + end endgenerate endmodule