From aece3f55559591e712a9082a2649bf5370ad3723 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 1 Aug 2016 15:05:30 +0300
Subject: [PATCH] axi_ad9680: Update IP core

- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
---
 library/axi_ad9680/axi_ad9680.v      |  6 ++++++
 library/axi_ad9680/axi_ad9680_hw.tcl | 17 ++++++++++++++++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v
index 321384f95..66e54937b 100644
--- a/library/axi_ad9680/axi_ad9680.v
+++ b/library/axi_ad9680/axi_ad9680.v
@@ -45,6 +45,8 @@ module axi_ad9680 (
   rx_clk,
   rx_sof,
   rx_data,
+  rx_valid,
+  rx_ready,
 
   // dma interface
 
@@ -93,6 +95,9 @@ module axi_ad9680 (
   input  [  3:0]  rx_sof;
   input  [127:0]  rx_data;
 
+  input           rx_valid;
+  output          rx_ready;
+
   // dma interface
 
   output          adc_clk;
@@ -172,6 +177,7 @@ module axi_ad9680 (
 
   assign adc_valid_0 = 1'b1;
   assign adc_valid_1 = 1'b1;
+  assign rx_ready = 1'b1;
 
   // processor read interface
 
diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl
index b103f2d9c..eb90f4386 100755
--- a/library/axi_ad9680/axi_ad9680_hw.tcl
+++ b/library/axi_ad9680/axi_ad9680_hw.tcl
@@ -24,6 +24,7 @@ add_fileset_file up_clock_mon.v       VERILOG PATH $ad_hdl_dir/library/common/up
 add_fileset_file up_delay_cntrl.v     VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
 add_fileset_file up_adc_common.v      VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
 add_fileset_file up_adc_channel.v     VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
+add_fileset_file ad_xcvr_rx_if.v      VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
 add_fileset_file axi_ad9680_pnmon.v   VERILOG PATH axi_ad9680_pnmon.v
 add_fileset_file axi_ad9680_channel.v VERILOG PATH axi_ad9680_channel.v
 add_fileset_file axi_ad9680_if.v      VERILOG PATH axi_ad9680_if.v
@@ -39,6 +40,13 @@ set_parameter_property ID TYPE INTEGER
 set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
+add_parameter DEVICE_TYPE INTEGER 0
+set_parameter_property DEVICE_TYPE DEFAULT_VALUE 1
+set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
+set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+
 # axi4 slave
 
 add_interface s_axi_clock clock end
@@ -74,7 +82,14 @@ add_interface_port s_axi s_axi_rready rready Input 1
 # transceiver interface
 
 ad_alt_intf clock   rx_clk        input   1
-ad_alt_intf signal  rx_data       input   128 data
+ad_alt_intf signal  rx_sof        input   4 export
+
+add_interface if_rx_ip_avl avalon_streaming sink
+add_interface_port if_rx_ip_avl rx_data  data  input 128
+add_interface_port if_rx_ip_avl rx_valid valid input 1
+add_interface_port if_rx_ip_avl rx_ready ready output 1
+set_interface_property if_rx_ip_avl associatedClock if_rx_clk
+set_interface_property if_rx_ip_avl dataBitsPerSymbol 128
 
 # dma interface