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jesd204/ad_ip_jesd204_tpl_dac: add I/Q roation

main
Laszlo Nagy 2020-03-06 13:22:18 +00:00 committed by Laszlo Nagy
parent 78aa56f9d2
commit af060700b8
6 changed files with 83 additions and 11 deletions
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1
library/jesd204/ad_ip_jesd204_tpl_dac/Makefile
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@ -11,6 +11,7 @@ GENERIC_DEPS += ../../common/ad_dds_2.v
GENERIC_DEPS += ../../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../../common/ad_dds_sine.v
GENERIC_DEPS += ../../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../../common/ad_iqcor.v
GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/up_axi.v

20
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
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@ -38,7 +38,8 @@ module ad_ip_jesd204_tpl_dac #(
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1
) (
// jesd interface
// link_clk is (line-rate/40)
@ -105,11 +106,16 @@ module ad_ip_jesd204_tpl_dac #(
wire [NUM_CHANNELS*16-1:0] dac_pat_data_0_s;
wire [NUM_CHANNELS*16-1:0] dac_pat_data_1_s;
wire [NUM_CHANNELS*4-1:0] dac_data_sel_s;
wire [NUM_CHANNELS-1:0] dac_iqcor_enb;
wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1;
wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2;
// regmap
ad_ip_jesd204_tpl_dac_regmap #(
.ID (ID),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -158,6 +164,10 @@ module ad_ip_jesd204_tpl_dac #(
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (dac_iqcor_enb),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2),
.jesd_m (NUM_CHANNELS),
.jesd_l (NUM_LANES),
.jesd_s (SAMPLES_PER_FRAME),
@ -171,6 +181,7 @@ module ad_ip_jesd204_tpl_dac #(
ad_ip_jesd204_tpl_dac_core #(
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
@ -206,7 +217,12 @@ module ad_ip_jesd204_tpl_dac #(
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_pat_data_0 (dac_pat_data_0_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_data_sel (dac_data_sel_s)
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (dac_iqcor_enb),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2)
);
endmodule

32
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
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@ -25,12 +25,14 @@
module ad_ip_jesd204_tpl_dac_channel #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16,
parameter BITS_PER_SAMPLE = 16,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16
parameter DDS_CORDIC_PHASE_DW = 16,
parameter Q_OR_I_N = 0
) (
// dac interface
@ -59,7 +61,13 @@ module ad_ip_jesd204_tpl_dac_channel #(
input [15:0] dac_dds_incr_1,
input [15:0] dac_pat_data_0,
input [15:0] dac_pat_data_1,
input [15:0] dac_pat_data_1,
input dac_iqcor_enb,
input [15:0] dac_iqcor_coeff_1,
input [15:0] dac_iqcor_coeff_2,
input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dac_iqcor_data_in,
output reg dac_enable = 1'b0
);
@ -72,6 +80,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
wire [CHANNEL_DATA_WIDTH-1:0] dac_dds_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_dma_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_pat_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_iqcor_data_s;
generate
if (DATA_PATH_WIDTH > 1) begin
@ -98,6 +107,23 @@ module ad_ip_jesd204_tpl_dac_channel #(
end
endgenerate
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE),
.CR (CR),
.DPW (DATA_PATH_WIDTH)
) i_ad_iqcor (
.clk (clk),
.valid (1'b1),
.data_in (dac_dma_data_s),
.data_iq (dac_iqcor_data_in),
.valid_out (),
.data_out (dac_iqcor_data_s),
.iqcor_enable (dac_iqcor_enb),
.iqcor_coeff_1 (dac_iqcor_coeff_1),
.iqcor_coeff_2 (dac_iqcor_coeff_2));
// dac data select
always @(posedge clk) begin
@ -108,7 +134,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
4'h5: dac_data <= ~pn15_data;
4'h4: dac_data <= ~pn7_data;
4'h3: dac_data <= 'h00;
4'h2: dac_data <= dac_dma_data_s;
4'h2: dac_data <= dac_iqcor_data_s;
4'h1: dac_data <= dac_pat_data_s;
default: dac_data <= dac_dds_data_s;
endcase

24
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
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@ -25,6 +25,7 @@
module ad_ip_jesd204_tpl_dac_core #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter BITS_PER_SAMPLE = 16,
@ -66,6 +67,10 @@ module ad_ip_jesd204_tpl_dac_core #(
input [NUM_CHANNELS*16-1:0] dac_pat_data_0,
input [NUM_CHANNELS*16-1:0] dac_pat_data_1,
input [NUM_CHANNELS-1:0] dac_iqcor_enb,
input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1,
input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2,
output [NUM_CHANNELS-1:0] enable
);
@ -116,6 +121,13 @@ module ad_ip_jesd204_tpl_dac_core #(
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
// Find the pair of the current channel for I/Q channels
// Assuming even channels are I, odd channels are Q
// Assuming channel count is even other case do not pair channels
localparam IQ_PAIR_CH_INDEX = (NUM_CHANNELS%2) ? i :
(i%2) ? i-1 : i+1;
ad_ip_jesd204_tpl_dac_channel #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
@ -123,7 +135,9 @@ module ad_ip_jesd204_tpl_dac_core #(
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW)
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE),
.Q_OR_I_N(i%2)
) i_channel (
.clk (clk),
.dac_enable (enable[i]),
@ -146,7 +160,13 @@ module ad_ip_jesd204_tpl_dac_core #(
.dac_dds_incr_1 (dac_dds_incr_1[16*i+:16]),
.dac_pat_data_0 (dac_pat_data_0[16*i+:16]),
.dac_pat_data_1 (dac_pat_data_1[16*i+:16])
.dac_pat_data_1 (dac_pat_data_1[16*i+:16]),
.dac_iqcor_enb (dac_iqcor_enb[i]),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
.dac_iqcor_data_in (dac_ddata[DMA_CDW*IQ_PAIR_CH_INDEX+:DMA_CDW])
);
end
endgenerate

2
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
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@ -33,6 +33,7 @@ adi_ip_files ad_ip_jesd204_tpl_dac [list \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
@ -144,6 +145,7 @@ set i 0
foreach {k v w} {
"DATAPATH_DISABLE" "Disable Datapath" "checkBox" \
"IQCORRECTION_DISABLE" "Disable IQ Correction" "checkBox" \
"DDS_TYPE" "DDS Type" "comboBox" \
"DDS_CORDIC_DW" "CORDIC DDS Data Width" "text" \
"DDS_CORDIC_PHASE_DW" "CORDIC DDS Phase Width" "text" \

15
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
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@ -25,6 +25,8 @@
module ad_ip_jesd204_tpl_dac_regmap #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
@ -79,6 +81,10 @@ module ad_ip_jesd204_tpl_dac_regmap #(
output [NUM_CHANNELS*16-1:0] dac_pat_data_0,
output [NUM_CHANNELS*16-1:0] dac_pat_data_1,
output [NUM_CHANNELS-1:0] dac_iqcor_enb,
output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1,
output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2,
// Framer interface
input [NUM_PROFILES*8-1: 0] jesd_m,
input [NUM_PROFILES*8-1: 0] jesd_l,
@ -179,6 +185,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
up_dac_common #(
.COMMON_ID(6'h0),
.ID (ID),
.CONFIG((DATAPATH_DISABLE << 6) | (IQCORRECTION_DISABLE << 0)),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -237,7 +244,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
.COMMON_ID(6'h1 + i/16),
.CHANNEL_ID (i % 16),
.USERPORTS_DISABLE (1),
.IQCORRECTION_DISABLE (1)
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_up_dac_channel (
.dac_clk (link_clk),
.dac_rst (dac_rst),
@ -251,9 +258,9 @@ module ad_ip_jesd204_tpl_dac_regmap #(
.dac_pat_data_2 (dac_pat_data_1[16*i+:16]),
.dac_data_sel (dac_data_sel[4*i+:4]),
.dac_iq_mode (),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.dac_iqcor_enb (dac_iqcor_enb[i]),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),