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axi|util_adxcvr: Delete reset interface inference for PLL resets 

The Xilinx's reset interface expect that every reset have an associated
interface and clock signal. The tool will try to find its clock and interface,
and automatically associated clock signal to it.

The PLL resets are individual asynchronous resets. To simplify the design
and avoid invalid critical warnings all the reset interface inference
for the PLL resets were removed.
main
Istvan Csomortani 2018-07-16 12:29:40 +01:00 committed by István Csomortáni
parent 985f35225c
commit af5c71a9b2
2 changed files with 0 additions and 43 deletions
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1
library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
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@ -61,7 +61,6 @@ for {set n 0} {$n < 16} {incr n} {
ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_pll_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]

42
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
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@ -108,48 +108,6 @@ ipx::infer_bus_interface tx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current
ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_0 -reset up_cpll_rst_0 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_1 -reset up_cpll_rst_1 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_2 -reset up_cpll_rst_2 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_3 -reset up_cpll_rst_3 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_4 -reset up_cpll_rst_4 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_5 -reset up_cpll_rst_5 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_6 -reset up_cpll_rst_6 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_7 -reset up_cpll_rst_7 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_8 -reset up_cpll_rst_8 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_9 -reset up_cpll_rst_9 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_10 -reset up_cpll_rst_10 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_11 -reset up_cpll_rst_11 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_12 -reset up_cpll_rst_12 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_13 -reset up_cpll_rst_13 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_14 -reset up_cpll_rst_14 -clear [ipx::current_core]
ipx::infer_bus_interface up_cpll_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_15 -reset up_cpll_rst_15 -clear [ipx::current_core]
ipx::infer_bus_interface up_qpll_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_0 -reset up_qpll_rst_0 -clear [ipx::current_core]
ipx::infer_bus_interface up_qpll_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_4 -reset up_qpll_rst_4 -clear [ipx::current_core]
ipx::infer_bus_interface up_qpll_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_8 -reset up_qpll_rst_8 -clear [ipx::current_core]
ipx::infer_bus_interface up_qpll_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::associate_bus_interfaces -clock cpll_ref_clk_12 -reset up_qpll_rst_12 -clear [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]