From af913863d4d7cccd14430c91e45203ac73a5af69 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Thu, 20 Apr 2017 19:20:26 +0200
Subject: [PATCH] axi_clkgen: Infer CLKIN period

Instead of having to manually specify the input clock period infer the
values from the block design. This means that less configuration parameters
need to be changed if the clock input frequency changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/axi_clkgen/axi_clkgen_ip.tcl |  2 ++
 library/axi_clkgen/bd/bd.tcl         | 30 ++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 library/axi_clkgen/bd/bd.tcl

diff --git a/library/axi_clkgen/axi_clkgen_ip.tcl b/library/axi_clkgen/axi_clkgen_ip.tcl
index 6b93ee10e..4ca6d18b2 100644
--- a/library/axi_clkgen/axi_clkgen_ip.tcl
+++ b/library/axi_clkgen/axi_clkgen_ip.tcl
@@ -10,9 +10,11 @@ adi_ip_files axi_clkgen [list \
   "$ad_hdl_dir/library/common/up_axi.v" \
   "$ad_hdl_dir/library/common/up_clkgen.v" \
   "axi_clkgen_constr.xdc" \
+  "bd/bd.tcl" \
   "axi_clkgen.v" ]
 
 adi_ip_properties axi_clkgen
+adi_ip_bd axi_clkgen "bd/bd.tcl"
 
 ipx::remove_bus_interface {clk} [ipx::current_core]
 ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
diff --git a/library/axi_clkgen/bd/bd.tcl b/library/axi_clkgen/bd/bd.tcl
new file mode 100644
index 000000000..4bd7756e0
--- /dev/null
+++ b/library/axi_clkgen/bd/bd.tcl
@@ -0,0 +1,30 @@
+proc init {cellpath otherInfo} {
+  set ip [get_bd_cells $cellpath]
+
+  bd::mark_propagate_override $ip \
+    "CLKIN_PERIOD CLKIN2_PERIOD"
+}
+
+proc axi_clkgen_get_infer_period {ip param clk_name} {
+  set param_src [get_property "CONFIG.$param.VALUE_SRC" $ip]
+  if {[string equal $param_src "USER"]} {
+    return;
+  }
+
+  set clk [get_bd_pins "$ip/$clk_name"]
+  set clk_freq [get_property CONFIG.FREQ_HZ $clk]
+
+  if {$clk_freq != {}} {
+    set clk_period [expr 1000000000.0 / $clk_freq]
+    set_property "CONFIG.$param" [format "%.6f" $clk_period] $ip
+  }
+}
+
+proc post_propagate {cellpath otherinfo} {
+  set ip [get_bd_cells $cellpath]
+
+  axi_clkgen_get_infer_period $ip CLKIN_PERIOD clk
+  if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
+    axi_clkgen_get_infer_period $ip CLKIN2_PERIOD clk2
+  }
+}