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axi_clkgen: Infer CLKIN period 

Instead of having to manually specify the input clock period infer the
values from the block design. This means that less configuration parameters
need to be changed if the clock input frequency changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-20 19:20:26 +02:00
parent fdedc9568c
commit af913863d4
2 changed files with 32 additions and 0 deletions
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2
library/axi_clkgen/axi_clkgen_ip.tcl
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@ -10,9 +10,11 @@ adi_ip_files axi_clkgen [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_clkgen.v" \
"axi_clkgen_constr.xdc" \
"bd/bd.tcl" \
"axi_clkgen.v" ]
adi_ip_properties axi_clkgen
adi_ip_bd axi_clkgen "bd/bd.tcl"
ipx::remove_bus_interface {clk} [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]

30
library/axi_clkgen/bd/bd.tcl Normal file
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@ -0,0 +1,30 @@
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_override $ip \
"CLKIN_PERIOD CLKIN2_PERIOD"
}
proc axi_clkgen_get_infer_period {ip param clk_name} {
set param_src [get_property "CONFIG.$param.VALUE_SRC" $ip]
if {[string equal $param_src "USER"]} {
return;
}
set clk [get_bd_pins "$ip/$clk_name"]
set clk_freq [get_property CONFIG.FREQ_HZ $clk]
if {$clk_freq != {}} {
set clk_period [expr 1000000000.0 / $clk_freq]
set_property "CONFIG.$param" [format "%.6f" $clk_period] $ip
}
}
proc post_propagate {cellpath otherinfo} {
set ip [get_bd_cells $cellpath]
axi_clkgen_get_infer_period $ip CLKIN_PERIOD clk
if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
axi_clkgen_get_infer_period $ip CLKIN2_PERIOD clk2
}
}