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fmcadc2: xcvr updates

main
AndreiGrozav 2016-11-21 18:45:38 +02:00
parent 69ee410d3d
commit aff45eae5f
9 changed files with 81 additions and 172 deletions
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171
projects/fmcadc2/common/fmcadc2_bd.tcl
View File

@ -1,12 +1,3 @@
# ad9625
create_bd_port -dir I rx_ref_clk
create_bd_port -dir O rx_sync
create_bd_port -dir O rx_sysref
create_bd_port -dir I -from 7 -to 0 rx_data_p
create_bd_port -dir I -from 7 -to 0 rx_data_n
# adc peripherals
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
@ -15,76 +6,10 @@ set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
set axi_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_gt]
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_1 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_2 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_3 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_4 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_5 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_6 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_7 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_ad9625_gt
set util_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9625_gt]
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9625_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9625_gt
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_ad9625_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9625_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_ad9625_gt
set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9625_gt
set axi_ad9625_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9625_xcvr]
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_xcvr
set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9625_xcvr
set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9625_xcvr
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
@ -99,76 +24,30 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
set util_fmcadc2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc2_xcvr]
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc2_xcvr
set_property -dict [list CONFIG.CPLL_TX_OR_RX_N {0}] $util_fmcadc2_xcvr
# connections (gt)
ad_connect util_ad9625_gt/qpll_ref_clk rx_ref_clk
ad_connect util_ad9625_gt/cpll_ref_clk rx_ref_clk
ad_connect axi_ad9625_gt/gt_pll_0 util_ad9625_gt/gt_pll_0
ad_connect axi_ad9625_gt/gt_pll_1 util_ad9625_gt/gt_pll_1
ad_connect axi_ad9625_gt/gt_pll_2 util_ad9625_gt/gt_pll_2
ad_connect axi_ad9625_gt/gt_pll_3 util_ad9625_gt/gt_pll_3
ad_connect axi_ad9625_gt/gt_pll_4 util_ad9625_gt/gt_pll_4
ad_connect axi_ad9625_gt/gt_pll_5 util_ad9625_gt/gt_pll_5
ad_connect axi_ad9625_gt/gt_pll_6 util_ad9625_gt/gt_pll_6
ad_connect axi_ad9625_gt/gt_pll_7 util_ad9625_gt/gt_pll_7
ad_connect axi_ad9625_gt/gt_rx_0 util_ad9625_gt/gt_rx_0
ad_connect axi_ad9625_gt/gt_rx_1 util_ad9625_gt/gt_rx_1
ad_connect axi_ad9625_gt/gt_rx_2 util_ad9625_gt/gt_rx_2
ad_connect axi_ad9625_gt/gt_rx_3 util_ad9625_gt/gt_rx_3
ad_connect axi_ad9625_gt/gt_rx_4 util_ad9625_gt/gt_rx_4
ad_connect axi_ad9625_gt/gt_rx_5 util_ad9625_gt/gt_rx_5
ad_connect axi_ad9625_gt/gt_rx_6 util_ad9625_gt/gt_rx_6
ad_connect axi_ad9625_gt/gt_rx_7 util_ad9625_gt/gt_rx_7
ad_connect axi_ad9625_gt/gt_rx_ip_0 axi_ad9625_jesd/gt0_rx
ad_connect axi_ad9625_gt/gt_rx_ip_1 axi_ad9625_jesd/gt1_rx
ad_connect axi_ad9625_gt/gt_rx_ip_2 axi_ad9625_jesd/gt2_rx
ad_connect axi_ad9625_gt/gt_rx_ip_3 axi_ad9625_jesd/gt3_rx
ad_connect axi_ad9625_gt/gt_rx_ip_4 axi_ad9625_jesd/gt4_rx
ad_connect axi_ad9625_gt/gt_rx_ip_5 axi_ad9625_jesd/gt5_rx
ad_connect axi_ad9625_gt/gt_rx_ip_6 axi_ad9625_jesd/gt6_rx
ad_connect axi_ad9625_gt/gt_rx_ip_7 axi_ad9625_jesd/gt7_rx
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_0 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_1 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_2 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_3 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_4 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_5 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_6 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_7 axi_ad9625_jesd/rxencommaalign_out
ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd
ad_connect sys_cpu_resetn util_fmcadc2_xcvr/up_rstn
ad_connect sys_cpu_clk util_fmcadc2_xcvr/up_clk
ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/rx_clk
ad_connect axi_ad9625_jesd/rx_tdata axi_ad9625_core/rx_data
ad_connect axi_ad9625_jesd/rx_start_of_frame axi_ad9625_core/rx_sof
# connections (adc)
ad_connect util_ad9625_gt/rx_p rx_data_p
ad_connect util_ad9625_gt/rx_n rx_data_n
ad_connect util_ad9625_gt/rx_sync rx_sync
ad_connect util_ad9625_gt/rx_ip_sysref rx_sysref
ad_connect util_ad9625_gt/rx_out_clk util_ad9625_gt/rx_clk
ad_connect util_ad9625_gt/rx_out_clk axi_ad9625_jesd/rx_core_clk
ad_connect util_ad9625_gt/rx_ip_rst axi_ad9625_jesd/rx_reset
ad_connect util_ad9625_gt/rx_ip_rst_done axi_ad9625_jesd/rx_reset_done
ad_connect util_ad9625_gt/rx_ip_sysref axi_ad9625_jesd/rx_sysref
ad_connect util_ad9625_gt/rx_ip_sync axi_ad9625_jesd/rx_sync
ad_connect util_ad9625_gt/rx_ip_sof axi_ad9625_jesd/rx_start_of_frame
ad_connect util_ad9625_gt/rx_ip_data axi_ad9625_jesd/rx_tdata
ad_connect util_ad9625_gt/rx_out_clk axi_ad9625_core/rx_clk
ad_connect util_ad9625_gt/rx_data axi_ad9625_core/rx_data
ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk
ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst
ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr
ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk
ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst
ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr
ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
@ -176,7 +55,7 @@ ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9625_gt
ad_cpu_interconnect 0x44A60000 axi_ad9625_xcvr
ad_cpu_interconnect 0x44A10000 axi_ad9625_core
ad_cpu_interconnect 0x44A91000 axi_ad9625_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
@ -184,7 +63,7 @@ ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_gt/m_axi
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9625_xcvr/m_axi
# interconnect (mem/adc)

9
projects/fmcadc2/vc707/Makefile
View File

@ -20,9 +20,10 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
M_DEPS += ../../common/vc707/vc707_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
M_VIVADO := vivado -mode batch -source
@ -53,9 +54,10 @@ clean:
clean-all:clean
make -C ../../../library/axi_ad9625 clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/util_adcfifo clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_jesd_gt clean
@ -66,9 +68,10 @@ fmcadc2_vc707.sdk/system_top.hdf: $(M_DEPS)
lib:
make -C ../../../library/axi_ad9625
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_dmac
make -C ../../../library/axi_jesd_gt
make -C ../../../library/util_adcfifo
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_jesd_gt
####################################################################################

4
projects/fmcadc2/vc707/system_constr.xdc
View File

@ -38,4 +38,6 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd]
# clocks
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

2
projects/fmcadc2/vc707/system_project.tcl
View File

@ -13,8 +13,6 @@ adi_project_files fmcadc2_vc707 [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc]
adi_project_run fmcadc2_vc707

24
projects/fmcadc2/vc707/system_top.v
View File

@ -290,11 +290,25 @@ module system_top (
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.phy_sd (1'b1),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_data_4_n (rx_data_n[4]),
.rx_data_4_p (rx_data_p[4]),
.rx_data_5_n (rx_data_n[5]),
.rx_data_5_p (rx_data_p[5]),
.rx_data_6_n (rx_data_n[6]),
.rx_data_6_p (rx_data_p[6]),
.rx_data_7_n (rx_data_n[7]),
.rx_data_7_p (rx_data_p[7]),
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),

9
projects/fmcadc2/zc706/Makefile
View File

@ -22,11 +22,12 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
M_VIVADO := vivado -mode batch -source
@ -58,11 +59,12 @@ clean:
clean-all:clean
make -C ../../../library/axi_ad9625 clean
make -C ../../../library/xilinx/axi_adcfifo clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_jesd_gt clean
@ -74,11 +76,12 @@ fmcadc2_zc706.sdk/system_top.hdf: $(M_DEPS)
lib:
make -C ../../../library/axi_ad9625
make -C ../../../library/xilinx/axi_adcfifo
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_jesd_gt
make -C ../../../library/axi_spdif_tx
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_jesd_gt
####################################################################################

4
projects/fmcadc2/zc706/system_constr.xdc
View File

@ -38,4 +38,6 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd]
# clocks
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

6
projects/fmcadc2/zc706/system_project.tcl
View File

@ -1,6 +1,4 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
@ -14,8 +12,4 @@ adi_project_files fmcadc2_zc706 [list \
"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc]
adi_project_run fmcadc2_zc706

24
projects/fmcadc2/zc706/system_top.v
View File

@ -322,11 +322,25 @@ module system_top (
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_data_4_n (rx_data_n[4]),
.rx_data_4_p (rx_data_p[4]),
.rx_data_5_n (rx_data_n[5]),
.rx_data_5_p (rx_data_p[5]),
.rx_data_6_n (rx_data_n[6]),
.rx_data_6_p (rx_data_p[6]),
.rx_data_7_n (rx_data_n[7]),
.rx_data_7_p (rx_data_p[7]),
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),