From b03fac4b37ca8aa929be1c630435ff3d6af84e9f Mon Sep 17 00:00:00 2001 From: Bogdan Luncan Date: Tue, 9 May 2023 09:15:10 +0100 Subject: [PATCH] ad9209: Initial vck190 design Signed-off-by: Bogdan Luncan --- projects/ad9209_fmca_ebz/Makefile | 7 + projects/ad9209_fmca_ebz/Readme.md | 8 + projects/ad9209_fmca_ebz/vck190/Makefile | 48 ++++ .../ad9209_fmca_ebz/vck190/ad9209_fmc.txt | 68 +++++ projects/ad9209_fmca_ebz/vck190/system_bd.tcl | 13 + .../ad9209_fmca_ebz/vck190/system_constr.xdc | 64 +++++ .../ad9209_fmca_ebz/vck190/system_project.tcl | 52 ++++ projects/ad9209_fmca_ebz/vck190/system_top.v | 263 ++++++++++++++++++ .../ad9209_fmca_ebz/vck190/timing_constr.xdc | 12 + 9 files changed, 535 insertions(+) create mode 100644 projects/ad9209_fmca_ebz/Makefile create mode 100644 projects/ad9209_fmca_ebz/Readme.md create mode 100644 projects/ad9209_fmca_ebz/vck190/Makefile create mode 100644 projects/ad9209_fmca_ebz/vck190/ad9209_fmc.txt create mode 100644 projects/ad9209_fmca_ebz/vck190/system_bd.tcl create mode 100644 projects/ad9209_fmca_ebz/vck190/system_constr.xdc create mode 100644 projects/ad9209_fmca_ebz/vck190/system_project.tcl create mode 100644 projects/ad9209_fmca_ebz/vck190/system_top.v create mode 100644 projects/ad9209_fmca_ebz/vck190/timing_constr.xdc diff --git a/projects/ad9209_fmca_ebz/Makefile b/projects/ad9209_fmca_ebz/Makefile new file mode 100644 index 000000000..1402069e1 --- /dev/null +++ b/projects/ad9209_fmca_ebz/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad9209_fmca_ebz/Readme.md b/projects/ad9209_fmca_ebz/Readme.md new file mode 100644 index 000000000..f8af013c6 --- /dev/null +++ b/projects/ad9209_fmca_ebz/Readme.md @@ -0,0 +1,8 @@ +# AD9209 HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/EVAL-AD9081) + * Parts : [12-Bit, 4GSPS, JESD204B/C, Quad Analog-to-Digital Converter](https://www.analog.com/en/products/ad9209.html) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081 diff --git a/projects/ad9209_fmca_ebz/vck190/Makefile b/projects/ad9209_fmca_ebz/vck190/Makefile new file mode 100644 index 000000000..d804ed476 --- /dev/null +++ b/projects/ad9209_fmca_ebz/vck190/Makefile @@ -0,0 +1,48 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9209_fmca_ebz_vck190 + +M_DEPS += timing_constr.xdc +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../common/vmk180/vmk180_system_bd.tcl +M_DEPS += ../../common/vck190/vck190_system_constr.xdc +M_DEPS += ../../common/vck190/vck190_system_bd.tcl +M_DEPS += ../../ad9081_fmca_ebz/vck190/system_bd.tcl +M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl +M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v +M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += axi_tdd +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9209_fmca_ebz/vck190/ad9209_fmc.txt b/projects/ad9209_fmca_ebz/vck190/ad9209_fmc.txt new file mode 100644 index 000000000..decf1aff8 --- /dev/null +++ b/projects/ad9209_fmca_ebz/vck190/ad9209_fmc.txt @@ -0,0 +1,68 @@ +# ad9209 + +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination + +A6 DP2_M2C_P FPGA_SERDIN_P<0> rx_data_p[2] #N/A #N/A +A7 DP2_M2C_N FPGA_SERDIN_N<0> rx_data_n[2] #N/A #N/A +C6 DP0_M2C_P FPGA_SERDIN_P<1> rx_data_p[0] #N/A #N/A +C7 DP0_M2C_N FPGA_SERDIN_N<1> rx_data_n[0] #N/A #N/A +B12 DP7_M2C_P FPGA_SERDIN_P<2> rx_data_p[7] #N/A #N/A +B13 DP7_M2C_N FPGA_SERDIN_N<2> rx_data_n[7] #N/A #N/A +B16 DP6_M2C_P FPGA_SERDIN_P<3> rx_data_p[6] #N/A #N/A +B17 DP6_M2C_N FPGA_SERDIN_N<3> rx_data_n[6] #N/A #N/A +A18 DP5_M2C_P FPGA_SERDIN_P<4> rx_data_p[5] #N/A #N/A +A19 DP5_M2C_N FPGA_SERDIN_N<4> rx_data_n[5] #N/A #N/A +A14 DP4_M2C_P FPGA_SERDIN_P<5> rx_data_p[4] #N/A #N/A +A15 DP4_M2C_N FPGA_SERDIN_N<5> rx_data_n[4] #N/A #N/A +A10 DP3_M2C_P FPGA_SERDIN_P<6> rx_data_p[3] #N/A #N/A +A11 DP3_M2C_N FPGA_SERDIN_N<6> rx_data_n[3] #N/A #N/A +A2 DP1_M2C_P FPGA_SERDIN_P<7> rx_data_p[1] #N/A #N/A +A3 DP1_M2C_N FPGA_SERDIN_N<7> rx_data_n[1] #N/A #N/A + +D8 LA01_P_CC FPGA_SYNCOUT_P<0> fpga_syncout_0_p LVDS15 #N/A +D9 LA01_N_CC FPGA_SYNCOUT_N<0> fpga_syncout_0_n LVDS15 #N/A +C10 LA06_P FPGA_SYNCOUT_P<1> fpga_syncout_1_p LVCMOS15 #N/A +C11 LA06_N FPGA_SYNCOUT_N<1> fpga_syncout_1_n LVCMOS15 #N/A + +D4 GBTCLK0_M2C_P FPGA_REFCLK_IN_P fpga_refclk_in_p #N/A #N/A +D5 GBTCLK0_M2C_N FPGA_REFCLK_IN_N fpga_refclk_in_n #N/A #N/A +H4 CLK0_M2C_P SYSREF2_P sysref2_p LVDS15 DIFF_TERM_ADV TERM_100 +H5 CLK0_M2C_N SYSREF2_N sysref2_n LVDS15 DIFF_TERM_ADV TERM_100 +G6 LA00_P_CC CLKIN10_P clkin10_p LVDS15 DIFF_TERM_ADV TERM_100 +G7 LA00_N_CC CLKIN10_N clkin10_n LVDS15 DIFF_TERM_ADV TERM_100 +H14 LA07_N HMC_SYNC hmc_sync LVCMOS15 #N/A + +H13 LA07_P RSTB rstb LVCMOS15 #N/A +C14 LA10_P RXEN<0> rxen[0] LVCMOS15 #N/A +C15 LA10_N RXEN<1> rxen[1] LVCMOS15 #N/A +H19 LA15_P GPIO<0> gpio[0] LVCMOS15 #N/A +H20 LA15_N GPIO<1> gpio[1] LVCMOS15 #N/A +H22 LA19_P GPIO<2> gpio[2] LVCMOS15 #N/A +H23 LA19_N GPIO<3> gpio[3] LVCMOS15 #N/A +D17 LA13_P GPIO<4> gpio[4] LVCMOS15 #N/A +D18 LA13_N GPIO<5> gpio[5] LVCMOS15 #N/A +C18 LA14_P GPIO<6> gpio[6] LVCMOS15 #N/A +C19 LA14_N GPIO<7> gpio[7] LVCMOS15 #N/A +G18 LA16_P GPIO<8> gpio[8] LVCMOS15 #N/A +G19 LA16_N GPIO<9> gpio[9] LVCMOS15 #N/A +G25 LA22_N GPIO<10> gpio[10] LVCMOS15 #N/A +G12 LA08_P IRQB<0> irqb[0] LVCMOS15 #N/A +G13 LA08_N IRQB<1> irqb[1] LVCMOS15 #N/A +H17 LA11_N HMC_GPIO1 hmc_gpio1 LVCMOS15 #N/A + +D11 LA05_P SPI0_CSB spi0_csb LVCMOS15 #N/A +H10 LA04_N SPI0_SCLK spi0_sclk LVCMOS15 #N/A +H11 LA04_P SPI0_MOSI spi0_mosi LVCMOS15 #N/A +D12 LA05_N SPI0_MISO spi0_miso LVCMOS15 #N/A +G15 LA12_P SPI1_CSB spi1_csb LVCMOS15 #N/A +H16 LA11_P SPI1_SCLK spi1_sclk LVCMOS15 #N/A +G16 LA12_N SPI1_SDIO spi1_sdio LVCMOS15 #N/A + +D20 LA17_P_CC AGC0<0> agc0[0] LVCMOS15 #N/A +D21 LA17_N_CC AGC0<1> agc0[1] LVCMOS15 #N/A +C22 LA18_P_CC AGC1<0> agc1[0] LVCMOS15 #N/A +C23 LA18_N_CC AGC1<1> agc1[1] LVCMOS15 #N/A +G21 LA20_P AGC2<0> agc2[0] LVCMOS15 #N/A +G22 LA20_N AGC2<1> agc2[1] LVCMOS15 #N/A +H25 LA21_P AGC3<0> agc3[0] LVCMOS15 #N/A +H26 LA21_N AGC3<1> agc3[1] LVCMOS15 #N/A diff --git a/projects/ad9209_fmca_ebz/vck190/system_bd.tcl b/projects/ad9209_fmca_ebz/vck190/system_bd.tcl new file mode 100644 index 000000000..5839bf407 --- /dev/null +++ b/projects/ad9209_fmca_ebz/vck190/system_bd.tcl @@ -0,0 +1,13 @@ +# Create only the RX path +set INTF_CFG RX + +# Dummy parameters for TX +set ad_project_params(TX_LANE_RATE) 0 +set ad_project_params(TX_JESD_M) 1 +set ad_project_params(TX_JESD_L) 1 +set ad_project_params(TX_JESD_S) 1 +set ad_project_params(TX_JESD_NP) 12 +set ad_project_params(TX_NUM_LINKS) 1 +set ad_project_params(TX_KS_PER_CHANNEL) 1 + +source $ad_hdl_dir/projects/ad9081_fmca_ebz/vck190/system_bd.tcl diff --git a/projects/ad9209_fmca_ebz/vck190/system_constr.xdc b/projects/ad9209_fmca_ebz/vck190/system_constr.xdc new file mode 100644 index 000000000..e5c57688e --- /dev/null +++ b/projects/ad9209_fmca_ebz/vck190/system_constr.xdc @@ -0,0 +1,64 @@ +# +## mxfe +# + +set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS15 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN BC16 IOSTANDARD LVCMOS15 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67 +set_property -dict {PACKAGE_PIN BE17 IOSTANDARD LVCMOS15 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN BD17 IOSTANDARD LVCMOS15 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN BE16 IOSTANDARD LVCMOS15 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN BF17 IOSTANDARD LVCMOS15 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67 +set_property -dict {PACKAGE_PIN BE19 IOSTANDARD LVCMOS15 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67 +set_property -dict {PACKAGE_PIN BD19 IOSTANDARD LVCMOS15 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN BD24 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN BD23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN M14 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229 +set_property -dict {PACKAGE_PIN M15 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229 +set_property -dict {PACKAGE_PIN Y1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N +set_property -dict {PACKAGE_PIN Y2 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTHRXP3_229 FPGA_SERDIN_0_P +set_property -dict {PACKAGE_PIN AB1 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTHRXN2_229 FPGA_SERDIN_1_N +set_property -dict {PACKAGE_PIN AB2 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTHRXP2_229 FPGA_SERDIN_1_P +set_property -dict {PACKAGE_PIN R3 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTHRXN2_228 FPGA_SERDIN_2_N +set_property -dict {PACKAGE_PIN R4 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTHRXP2_228 FPGA_SERDIN_2_P +set_property -dict {PACKAGE_PIN T1 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTHRXN0_228 FPGA_SERDIN_3_N +set_property -dict {PACKAGE_PIN T2 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTHRXP0_228 FPGA_SERDIN_3_P +set_property -dict {PACKAGE_PIN U3 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTHRXN1_228 FPGA_SERDIN_4_N +set_property -dict {PACKAGE_PIN U4 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTHRXP1_228 FPGA_SERDIN_4_P +set_property -dict {PACKAGE_PIN V1 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTHRXN3_228 FPGA_SERDIN_5_N +set_property -dict {PACKAGE_PIN V2 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTHRXP3_228 FPGA_SERDIN_5_P +set_property -dict {PACKAGE_PIN W3 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTHRXN0_229 FPGA_SERDIN_6_N +set_property -dict {PACKAGE_PIN W4 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTHRXP0_229 FPGA_SERDIN_6_P +set_property -dict {PACKAGE_PIN AA3 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTHRXN1_229 FPGA_SERDIN_7_N +set_property -dict {PACKAGE_PIN AA4 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTHRXP1_229 FPGA_SERDIN_7_P +set_property -dict {PACKAGE_PIN BD22 IOSTANDARD LVDS15 } [get_ports fpga_syncout_0_n ] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -dict {PACKAGE_PIN BC23 IOSTANDARD LVDS15 } [get_ports fpga_syncout_0_p ] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -dict {PACKAGE_PIN BD20 IOSTANDARD LVCMOS15 } [get_ports fpga_syncout_1_n ] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -dict {PACKAGE_PIN BC20 IOSTANDARD LVCMOS15 } [get_ports fpga_syncout_1_p ] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS15 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS15 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN BA17 IOSTANDARD LVCMOS15 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN BA16 IOSTANDARD LVCMOS15 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN BE21 IOSTANDARD LVCMOS15 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN BE20 IOSTANDARD LVCMOS15 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN AU24 IOSTANDARD LVCMOS15 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN AU23 IOSTANDARD LVCMOS15 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN BF21 IOSTANDARD LVCMOS15 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN BG20 IOSTANDARD LVCMOS15 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN BG18 IOSTANDARD LVCMOS15 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN BE22 IOSTANDARD LVCMOS15 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN BD25 IOSTANDARD LVCMOS15 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN BC22 IOSTANDARD LVCMOS15 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN BC21 IOSTANDARD LVCMOS15 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN BC25 IOSTANDARD LVCMOS15 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN BG25 IOSTANDARD LVCMOS15 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN BG24 IOSTANDARD LVCMOS15 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN BF24 IOSTANDARD LVCMOS15 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN BG23 IOSTANDARD LVCMOS15 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVCMOS15 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS15 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN BG21 IOSTANDARD LVCMOS15 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN BF23 IOSTANDARD LVCMOS15 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN BF22 IOSTANDARD LVCMOS15 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN AW23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66 +set_property -dict {PACKAGE_PIN AV23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66 + diff --git a/projects/ad9209_fmca_ebz/vck190/system_project.tcl b/projects/ad9209_fmca_ebz/vck190/system_project.tcl new file mode 100644 index 000000000..35d235470 --- /dev/null +++ b/projects/ad9209_fmca_ebz/vck190/system_project.tcl @@ -0,0 +1,52 @@ +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 +# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 + +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer +# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer +# +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode +# RX_JESD_M : Number of converters per link +# RX_JESD_L : Number of lanes per link +# RX_JESD_S : Number of samples per frame +# RX_JESD_NP : Number of bits per sample, only 16 is supported +# RX_NUM_LINKS : Number of links, matches numer of MxFE devices +# RX_KS_PER_CHANNEL : Number of samples stored in internal buffers in kilosamples per converter (M) + +# make JESD_MODE=64B66B RX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 + +adi_project ad9209_fmca_ebz_vck190 0 [list \ + JESD_MODE [get_env_param JESD_MODE 64B66B ]\ + RX_LANE_RATE [get_env_param RX_LANE_RATE 24.75 ] \ + REF_CLK_RATE [get_env_param REF_CLK_RATE 375 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 8 ] \ + RX_JESD_S [get_env_param RX_JESD_S 4 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 12 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ +] + +adi_project_files ad9209_fmca_ebz_vck190 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "timing_constr.xdc"\ + "../../../library/common/ad_3w_spi.v"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc" ] + +set_property strategy Performance_Explore [get_runs impl_1] + +adi_project_run ad9209_fmca_ebz_vck190 diff --git a/projects/ad9209_fmca_ebz/vck190/system_top.v b/projects/ad9209_fmca_ebz/vck190/system_top.v new file mode 100644 index 000000000..1e6eda9cc --- /dev/null +++ b/projects/ad9209_fmca_ebz/vck190/system_top.v @@ -0,0 +1,263 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter RX_JESD_L = 8, + parameter RX_NUM_LINKS = 1, + parameter JESD_MODE = "64B66B" +) ( + input sys_clk_n, + input sys_clk_p, + output ddr4_act_n, + output [16:0] ddr4_adr, + output [ 1:0] ddr4_ba, + output [ 1:0] ddr4_bg, + output ddr4_ck_c, + output ddr4_ck_t, + output ddr4_cke, + output ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_c, + inout [ 7:0] ddr4_dqs_t, + output ddr4_odt, + output ddr4_reset_n, + // GPIOs + output [ 3:0] gpio_led, + input [ 3:0] gpio_dip_sw, + input [ 1:0] gpio_pb, + + // FMC HPC IOs + input [ 1:0] agc0, + input [ 1:0] agc1, + input [ 1:0] agc2, + input [ 1:0] agc3, + input clkin10_n, + input clkin10_p, + input fpga_refclk_in_n, + input fpga_refclk_in_p, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, + output fpga_syncout_0_n, + output fpga_syncout_0_p, + inout fpga_syncout_1_n, + inout fpga_syncout_1_p, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [ 1:0] irqb, + output rstb, + output [ 1:0] rxen, + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + input sysref2_n, + input sysref2_p +); + + // internal signals + + wire [95:0] gpio_i; + wire [95:0] gpio_o; + wire [95:0] gpio_t; + + wire [ 2:0] spi0_csn; + + wire [ 2:0] spi1_csn; + wire spi1_mosi; + wire spi1_miso; + + wire sysref; + wire [RX_NUM_LINKS-1:0] rx_syncout; + + wire [ 7:0] rx_data_p_loc; + wire [ 7:0] rx_data_n_loc; + + wire clkin10; + wire rx_device_clk; + + // instantiations + IBUFDS_GTE5 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (fpga_refclk_in_p), + .IB (fpga_refclk_in_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref ( + .I (sysref2_p), + .IB (sysref2_n), + .O (sysref)); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clkin10_p), + .IB (clkin10_n), + .O (clkin10)); + + OBUFDS i_obufds_syncout_0 ( + .I (rx_syncout[0]), + .O (fpga_syncout_0_p), + .OB (fpga_syncout_0_n)); + + BUFG i_rx_device_clk ( + .I (clkin10), + .O (rx_device_clk)); + + // spi + + assign spi0_csb = spi0_csn[0]; + assign spi1_csb = spi1_csn[0]; + + ad_3w_spi #( + .NUM_OF_SLAVES(1) + ) i_spi ( + .spi_csn (spi1_csn[0]), + .spi_clk (spi1_sclk), + .spi_mosi (spi1_mosi), + .spi_miso (spi1_miso), + .spi_sdio (spi1_sdio), + .spi_dir ()); + + // gpios + + ad_iobuf #( + .DATA_WIDTH(12) + ) i_iobuf ( + .dio_t (gpio_t[43:32]), + .dio_i (gpio_o[43:32]), + .dio_o (gpio_i[43:32]), + .dio_p ({hmc_gpio1, // 43 + gpio[10:0]})); // 42-32 + + assign gpio_i[44] = agc0[0]; + assign gpio_i[45] = agc0[1]; + assign gpio_i[46] = agc1[0]; + assign gpio_i[47] = agc1[1]; + assign gpio_i[48] = agc2[0]; + assign gpio_i[49] = agc2[1]; + assign gpio_i[50] = agc3[0]; + assign gpio_i[51] = agc3[1]; + assign gpio_i[52] = irqb[0]; + assign gpio_i[53] = irqb[1]; + + assign hmc_sync = gpio_o[54]; + assign rstb = gpio_o[55]; + assign rxen[0] = gpio_o[56]; + assign rxen[1] = gpio_o[57]; + + generate + if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign fpga_syncout_1_p = rx_syncout[1]; + assign fpga_syncout_1_n = 0; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncout_iobuf ( + .dio_t (gpio_t[63:62]), + .dio_i (gpio_o[63:62]), + .dio_o (gpio_i[63:62]), + .dio_p ({fpga_syncout_1_n, // 63 + fpga_syncout_1_p})); // 62 + end + endgenerate + + /* Board GPIOS. Buttons, LEDs, etc... */ + assign gpio_led = gpio_o[3:0]; + assign gpio_i[3:0] = gpio_o[3:0]; + assign gpio_i[7: 4] = gpio_dip_sw; + assign gpio_i[9: 8] = gpio_pb; + + // Unused GPIOs + assign gpio_i[59:54] = gpio_o[59:54]; + assign gpio_i[94:64] = gpio_o[94:64]; + assign gpio_i[31:10] = gpio_o[31:10]; + + system_wrapper i_system_wrapper ( + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .gpio2_i (gpio_i[95:64]), + .gpio2_o (gpio_o[95:64]), + .gpio2_t (gpio_t[95:64]), + .ddr4_dimm1_sma_clk_clk_n (sys_clk_n), + .ddr4_dimm1_sma_clk_clk_p (sys_clk_p), + .ddr4_dimm1_act_n (ddr4_act_n), + .ddr4_dimm1_adr (ddr4_adr), + .ddr4_dimm1_ba (ddr4_ba), + .ddr4_dimm1_bg (ddr4_bg), + .ddr4_dimm1_ck_c (ddr4_ck_c), + .ddr4_dimm1_ck_t (ddr4_ck_t), + .ddr4_dimm1_cke (ddr4_cke), + .ddr4_dimm1_cs_n (ddr4_cs_n), + .ddr4_dimm1_dm_n (ddr4_dm_n), + .ddr4_dimm1_dq (ddr4_dq), + .ddr4_dimm1_dqs_c (ddr4_dqs_c), + .ddr4_dimm1_dqs_t (ddr4_dqs_t), + .ddr4_dimm1_odt (ddr4_odt), + .ddr4_dimm1_reset_n (ddr4_reset_n), + .spi0_csn (spi0_csn), + .spi0_miso (spi0_miso), + .spi0_mosi (spi0_mosi), + .spi0_sclk (spi0_sclk), + .spi1_csn (spi1_csn), + .spi1_miso (spi1_miso), + .spi1_mosi (spi1_mosi), + .spi1_sclk (spi1_sclk), + // FMC HPC + .GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]), + .GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]), + .GT_Serial_1_0_grx_p (rx_data_p_loc[7:4]), + .GT_Serial_1_0_grx_n (rx_data_n_loc[7:4]), + + .ref_clk_q0 (ref_clk), + .ref_clk_q1 (ref_clk), + + .rx_device_clk (rx_device_clk), + .rx_sync_0 (rx_syncout), + .rx_sysref_0 (sysref)); + + assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0]; + assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0]; + +endmodule diff --git a/projects/ad9209_fmca_ebz/vck190/timing_constr.xdc b/projects/ad9209_fmca_ebz/vck190/timing_constr.xdc new file mode 100644 index 000000000..12f4f4339 --- /dev/null +++ b/projects/ad9209_fmca_ebz/vck190/timing_constr.xdc @@ -0,0 +1,12 @@ +# Primary clock definitions +create_clock -name refclk -period 2.667 [get_ports fpga_refclk_in_p] + +# device clock +create_clock -name rx_device_clk -period 2.667 [get_ports clkin10_p] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay -clock [get_clocks rx_device_clk] \ + [get_property PERIOD [get_clocks rx_device_clk]] \ + [get_ports {sysref2_*}]