From b0a5be85653714dbc58ed9d1ce0ead176a97b8f5 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Tue, 6 Dec 2016 14:49:33 +0200
Subject: [PATCH] axi_ad9122: Add loaden port for altera support

---
 library/axi_ad9122/axi_ad9122_if.v | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v
index 7f5a64658..4eb921561 100644
--- a/library/axi_ad9122/axi_ad9122_if.v
+++ b/library/axi_ad9122/axi_ad9122_if.v
@@ -169,6 +169,7 @@ module axi_ad9122_if (
   // internal signals
 
   wire            dac_out_clk;
+  wire            loaden_s;
 
   // dac status
 
@@ -192,7 +193,7 @@ module axi_ad9122_if (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
+    .loaden (loaden_s),
     .data_s0 (dac_data_i0),
     .data_s1 (dac_data_q0),
     .data_s2 (dac_data_i1),
@@ -214,7 +215,7 @@ module axi_ad9122_if (
     .rst (dac_rst),
     .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
+    .loaden (loaden_s),
     .data_s0 (dac_frame_i0),
     .data_s1 (dac_frame_q0),
     .data_s2 (dac_frame_i1),
@@ -234,9 +235,9 @@ module axi_ad9122_if (
     .DATA_WIDTH (1))
   i_serdes_out_clk (
     .rst (dac_rst),
-    .clk (dac_out_clk),
+    .clk (dac_clk),
     .div_clk (dac_div_clk),
-    .loaden (1'b0),
+    .loaden (loaden_s),
     .data_s0 (1'b1),
     .data_s1 (1'b0),
     .data_s2 (1'b1),
@@ -266,7 +267,7 @@ module axi_ad9122_if (
     .clk (dac_clk),
     .div_clk (dac_div_clk),
     .out_clk (dac_out_clk),
-    .loaden (),
+    .loaden (loaden_s),
     .phase (),
     .up_clk (up_clk),
     .up_rstn (up_rstn),