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axi_ad9122: Add loaden port for altera support

main
Istvan Csomortani 2016-12-06 14:49:33 +02:00 committed by Csomortani
parent cedca30cd6
commit b0a5be8565
1 changed files with 6 additions and 5 deletions
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11
library/axi_ad9122/axi_ad9122_if.v
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@ -169,6 +169,7 @@ module axi_ad9122_if (
// internal signals
wire dac_out_clk;
wire loaden_s;
// dac status
@ -192,7 +193,7 @@ module axi_ad9122_if (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.loaden (loaden_s),
.data_s0 (dac_data_i0),
.data_s1 (dac_data_q0),
.data_s2 (dac_data_i1),
@ -214,7 +215,7 @@ module axi_ad9122_if (
.rst (dac_rst),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.loaden (loaden_s),
.data_s0 (dac_frame_i0),
.data_s1 (dac_frame_q0),
.data_s2 (dac_frame_i1),
@ -234,9 +235,9 @@ module axi_ad9122_if (
.DATA_WIDTH (1))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_out_clk),
.clk (dac_clk),
.div_clk (dac_div_clk),
.loaden (1'b0),
.loaden (loaden_s),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),
@ -266,7 +267,7 @@ module axi_ad9122_if (
.clk (dac_clk),
.div_clk (dac_div_clk),
.out_clk (dac_out_clk),
.loaden (),
.loaden (loaden_s),
.phase (),
.up_clk (up_clk),
.up_rstn (up_rstn),