From b0ebf2df0654d7b1411e3033edcb1f355ceb1f0d Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 30 Jun 2017 15:17:14 +0200 Subject: [PATCH] daq3: Provide DAC JESD204 lane mapping The DAQ3 does not use a 1-to-1 lane mapping for the DAC JESD204 link. Provide the proper mapping when setting up the transceiver connections. Without this the payload data will be mapped incorrectly and the transmitted signals are scrambled. Signed-off-by: Lars-Peter Clausen --- projects/daq3/common/daq3_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index 4f16baecc..a711df999 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -77,7 +77,7 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_* # connections (dac) -ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd +ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd {0 2 3 1} ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk ad_connect axi_ad9152_jesd/tx_data_tdata axi_ad9152_core/tx_data ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk