zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

daq3: Provide DAC JESD204 lane mapping 

The DAQ3 does not use a 1-to-1 lane mapping for the DAC JESD204 link.
Provide the proper mapping when setting up the transceiver connections.
Without this the payload data will be mapped incorrectly and the
transmitted signals are scrambled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-06-30 15:17:14 +02:00
parent d65a543854
commit b0ebf2df06
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
projects/daq3/common/daq3_bd.tcl
View File

@ -77,7 +77,7 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq3_xcvr/up_cpll_rst_*
# connections (dac) # connections (dac)
ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd ad_xcvrcon util_daq3_xcvr axi_ad9152_xcvr axi_ad9152_jesd {0 2 3 1}
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_core/tx_clk
ad_connect axi_ad9152_jesd/tx_data_tdata axi_ad9152_core/tx_data ad_connect axi_ad9152_jesd/tx_data_tdata axi_ad9152_core/tx_data
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_upack/dac_clk