From b14721b8ae6ef08ccab4a9eb4017d37fac85bcfc Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Tue, 14 Apr 2015 18:54:26 +0200
Subject: [PATCH] library: Use common prefix for CDC signal names

Use a common naming scheme for CDC signals to make it easier to create
constraints for them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/common/sync_bits.v              | 14 +++++++-------
 library/common/sync_gray.v              | 20 ++++++++++----------
 library/util_axis_fifo/util_axis_fifo.v |  6 +++---
 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/library/common/sync_bits.v b/library/common/sync_bits.v
index a39c25d76..674d95627 100644
--- a/library/common/sync_bits.v
+++ b/library/common/sync_bits.v
@@ -57,20 +57,20 @@ parameter NUM_BITS = 1;
 // be bypassed and the output signal equals the input signal.
 parameter CLK_ASYNC = 1;
 
-reg [NUM_BITS-1:0] out_m1 = 'h0;
-reg [NUM_BITS-1:0] out_m2 = 'h0;
+reg [NUM_BITS-1:0] cdc_sync_stage1 = 'h0;
+reg [NUM_BITS-1:0] cdc_sync_stage2 = 'h0;
 
 always @(posedge out_clk)
 begin
 	if (out_resetn == 1'b0) begin
-		out_m1 <= 'b0;
-		out_m2 <= 'b0;
+		cdc_sync_stage1 <= 'b0;
+		cdc_sync_stage2 <= 'b0;
 	end else begin
-		out_m1 <= in;
-	    out_m2 <= out_m1;	
+		cdc_sync_stage1 <= in;
+		cdc_sync_stage2 <= cdc_sync_stage1;
 	end
 end
 
-assign out = CLK_ASYNC ? out_m2 : in;
+assign out = CLK_ASYNC ? cdc_sync_stage2 : in;
 
 endmodule
diff --git a/library/common/sync_gray.v b/library/common/sync_gray.v
index 460ce4249..06d7d4472 100644
--- a/library/common/sync_gray.v
+++ b/library/common/sync_gray.v
@@ -57,9 +57,9 @@ parameter DATA_WIDTH = 1;
 // synchronizer will be bypassed and out_count will be in_count.
 parameter CLK_ASYNC = 1;
 
-reg [DATA_WIDTH-1:0] in_count_gray = 'h0;
-reg [DATA_WIDTH-1:0] out_count_gray_m1 = 'h0;
-reg [DATA_WIDTH-1:0] out_count_gray_m2 = 'h0;
+reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
+reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
+reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
 reg [DATA_WIDTH-1:0] out_count_m = 'h0;
 
 function [DATA_WIDTH-1:0] g2b;
@@ -88,21 +88,21 @@ endfunction
 
 always @(posedge in_clk) begin
 	if (in_resetn == 1'b0) begin
-		in_count_gray <= 'h00;
+		cdc_sync_stage0 <= 'h00;
 	end else begin
-		in_count_gray <= b2g(in_count);
+		cdc_sync_stage0 <= b2g(in_count);
 	end
 end
 
 always @(posedge out_clk) begin
 	if (out_resetn == 1'b0) begin
-		out_count_gray_m1 <= 'h00;
-		out_count_gray_m2 <= 'h00;
+		cdc_sync_stage1 <= 'h00;
+		cdc_sync_stage2 <= 'h00;
 		out_count_m <= 'h00;
 	end else begin
-		out_count_gray_m1 <= in_count_gray;
-		out_count_gray_m2 <= out_count_gray_m1;
-		out_count_m <= g2b(out_count_gray_m2);
+		cdc_sync_stage1 <= cdc_sync_stage0;
+		cdc_sync_stage2 <= cdc_sync_stage1;
+		out_count_m <= g2b(cdc_sync_stage2);
 	end
 end
 
diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v
index a991df16b..9b209dba7 100644
--- a/library/util_axis_fifo/util_axis_fifo.v
+++ b/library/util_axis_fifo/util_axis_fifo.v
@@ -60,7 +60,7 @@ parameter C_S_AXIS_REGISTERED = 1;
 
 generate if (C_ADDRESS_WIDTH == 0) begin
 
-reg [C_DATA_WIDTH-1:0] ram;
+reg [C_DATA_WIDTH-1:0] cdc_sync_fifo_ram;
 reg s_axis_waddr = 1'b0;
 reg m_axis_raddr = 1'b0;
 
@@ -95,7 +95,7 @@ assign s_axis_room = s_axis_ready;
 
 always @(posedge s_axis_aclk) begin
 	if (s_axis_ready)
-		ram <= s_axis_data;
+		cdc_sync_fifo_ram <= s_axis_data;
 end
 
 always @(posedge s_axis_aclk) begin
@@ -117,7 +117,7 @@ always @(posedge m_axis_aclk) begin
 	end
 end
 
-assign m_axis_data = ram;
+assign m_axis_data = cdc_sync_fifo_ram;
 
 end else begin