diff --git a/projects/Makefile b/projects/Makefile index 5b6e63562..db53c0806 100644 --- a/projects/Makefile +++ b/projects/Makefile @@ -34,6 +34,7 @@ all: -make -C fmcomms5 all -make -C fmcomms7 all -make -C imageon all + -make -C m2k all -make -C motcon2_fmc all -make -C pluto all -make -C pzsdr1 all @@ -71,6 +72,7 @@ clean: make -C fmcomms5 clean make -C fmcomms7 clean make -C imageon clean + make -C m2k clean make -C motcon2_fmc clean make -C pluto clean make -C pzsdr1 clean @@ -108,6 +110,7 @@ clean-all: make -C fmcomms5 clean-all make -C fmcomms7 clean-all make -C imageon clean-all + make -C m2k clean-all make -C motcon2_fmc clean-all make -C pluto clean-all make -C pzsdr1 clean-all diff --git a/projects/m2k/Makefile b/projects/m2k/Makefile new file mode 100644 index 000000000..882e9f2ee --- /dev/null +++ b/projects/m2k/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +.PHONY: all clean clean-all +all: + -make -C standalone all + -make -C zed all + + +clean: + make -C standalone clean + make -C zed clean + + +clean-all: + make -C standalone clean-all + make -C zed clean-all + +#################################################################################### +#################################################################################### diff --git a/projects/m2k/common/m2k_bd.tcl b/projects/m2k/common/m2k_bd.tcl new file mode 100644 index 000000000..236d579c9 --- /dev/null +++ b/projects/m2k/common/m2k_bd.tcl @@ -0,0 +1,225 @@ + +create_bd_port -dir I -from 15 -to 0 data_i +create_bd_port -dir I -from 1 -to 0 trigger_i + +create_bd_port -dir O -from 15 -to 0 data_o +create_bd_port -dir O -from 15 -to 0 data_t +create_bd_port -dir O -from 1 -to 0 trigger_o +create_bd_port -dir O -from 1 -to 0 trigger_t + +create_bd_port -dir I rx_clk +create_bd_port -dir I rxiq +create_bd_port -dir I -from 11 -to 0 rxd +create_bd_port -dir O tx_clk +create_bd_port -dir O txiq +create_bd_port -dir O -from 11 -to 0 txd + +set clk_generator [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 clk_generator] +set_property -dict [list CONFIG.VCO_DIV {1}] $clk_generator +set_property -dict [list CONFIG.VCO_MUL {8}] $clk_generator +set_property -dict [list CONFIG.CLK0_DIV {10}] $clk_generator +set_property -dict [list CONFIG.CLK1_DIV {5}] $clk_generator +set_property -dict [list CONFIG.CLK0_PHASE {180}] $clk_generator +set_property -dict [list CONFIG.CLK1_PHASE {180}] $clk_generator +set_property -dict [list CONFIG.CLKIN_PERIOD {10}] $clk_generator +set_property -dict [list CONFIG.CLKIN2_PERIOD {12.5}] $clk_generator + +set logic_analyzer [create_bd_cell -type ip -vlnv analog.com:user:axi_logic_analyzer:1.0 logic_analyzer] + +set la_trigger_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_var_fifo:1.0 la_trigger_fifo] +set_property -dict [list CONFIG.DATA_WIDTH {16} ] $la_trigger_fifo +set_property -dict [list CONFIG.ADDRESS_WIDTH {13} ] $la_trigger_fifo + +set logic_analyzer_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 logic_analyzer_dmac] +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16} ] $logic_analyzer_dmac +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1} ] $logic_analyzer_dmac +set_property -dict [list CONFIG.SYNC_TRANSFER_START {true} ] $logic_analyzer_dmac + +set pattern_generator_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 pattern_generator_dmac] +set_property -dict [list CONFIG.DMA_TYPE_DEST {2} ] $pattern_generator_dmac +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $pattern_generator_dmac +set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {32}] $pattern_generator_dmac +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $pattern_generator_dmac +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16} ] $pattern_generator_dmac +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $pattern_generator_dmac +set_property -dict [list CONFIG.CYCLIC {true}] $pattern_generator_dmac + +set axi_ad9963 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9963:1.0 axi_ad9963] + +set adc_trigger_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_var_fifo:1.0 adc_trigger_fifo] +set_property -dict [list CONFIG.DATA_WIDTH {32} ] $adc_trigger_fifo +set_property -dict [list CONFIG.ADDRESS_WIDTH {13} ] $adc_trigger_fifo + +set adc_trigger_extract [create_bd_cell -type ip -vlnv analog.com:user:util_extract:1.0 adc_trigger_extract] + +set util_cpack_ad9963 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9963] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9963 +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_cpack_ad9963 + +set ad9963_adc_dmac [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_adc_dmac] +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_adc_dmac +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1}] $ad9963_adc_dmac +set_property -dict [list CONFIG.SYNC_TRANSFER_START {true}] $ad9963_adc_dmac + +set ad9963_dac_dmac_a [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_dac_dmac_a] +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {64}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.CYCLIC {true}] $ad9963_dac_dmac_a + +set ad9963_dac_dmac_b [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad9963_dac_dmac_b] +set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.MAX_BYTES_PER_BURST {64}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {16}] $ad9963_dac_dmac_b +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $ad9963_dac_dmac_a +set_property -dict [list CONFIG.CYCLIC {true}] $ad9963_dac_dmac_b + +set adc_trigger [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_trigger:1.0 adc_trigger] + +set axi_adc_decimate [create_bd_cell -type ip -vlnv analog.com:user:axi_adc_decimate:1.0 axi_adc_decimate] +set axi_dac_interpolate [create_bd_cell -type ip -vlnv analog.com:user:axi_dac_interpolate:1.0 axi_dac_interpolate] + +ad_connect data_i logic_analyzer/data_i +ad_connect trigger_i logic_analyzer/trigger_i +ad_connect data_o logic_analyzer/data_o +ad_connect data_t logic_analyzer/data_t + +ad_connect sys_cpu_clk clk_generator/clk +#ad_connect logic_analyzer/clk_out clk_generator/clk2 + +ad_connect logic_analyzer/clk clk_generator/clk_0 + +ad_connect pattern_generator_dmac/fifo_rd_clk clk_generator/clk_0 + +ad_connect clk_generator/clk_0 la_trigger_fifo/clk +ad_connect logic_analyzer_dmac/fifo_wr_clk clk_generator/clk_0 + +ad_connect la_trigger_fifo/data_in logic_analyzer/adc_data +ad_connect la_trigger_fifo/data_in_valid logic_analyzer/adc_valid + +ad_connect logic_analyzer_dmac/fifo_wr_din la_trigger_fifo/data_out +ad_connect logic_analyzer_dmac/fifo_wr_en la_trigger_fifo/data_out_valid + +ad_connect logic_analyzer/trigger_offset la_trigger_fifo/depth + +ad_connect logic_analyzer/trigger_out logic_analyzer_dmac/fifo_wr_sync + +ad_connect pattern_generator_dmac/fifo_rd_en logic_analyzer/dac_read +ad_connect pattern_generator_dmac/fifo_rd_dout logic_analyzer/dac_data +ad_connect pattern_generator_dmac/fifo_rd_valid logic_analyzer/dac_valid + + +ad_connect sys_cpu_clk logic_analyzer/s_axi_aclk +ad_connect sys_cpu_resetn logic_analyzer/s_axi_aresetn + +ad_connect sys_200m_clk axi_ad9963/delay_clk + +ad_connect axi_ad9963/l_clk adc_trigger_fifo/clk +ad_connect axi_ad9963/l_clk util_cpack_ad9963/adc_clk +ad_connect axi_adc_decimate/adc_clk axi_ad9963/l_clk +ad_connect adc_trigger_extract/clk axi_ad9963/l_clk +ad_connect ad9963_adc_dmac/fifo_wr_clk axi_ad9963/l_clk + +ad_connect axi_ad9963/rst util_cpack_ad9963/adc_rst +ad_connect axi_ad9963/rst adc_trigger_fifo/rst + +ad_connect axi_adc_decimate/adc_data_a axi_ad9963/adc_data_i +ad_connect axi_adc_decimate/adc_data_b axi_ad9963/adc_data_q +ad_connect axi_adc_decimate/adc_valid_a axi_ad9963/adc_valid_i +ad_connect axi_adc_decimate/adc_valid_b axi_ad9963/adc_valid_q + +ad_connect axi_ad9963/adc_enable_i util_cpack_ad9963/adc_enable_0 +ad_connect adc_trigger/data_valid_a_trig util_cpack_ad9963/adc_valid_0 +ad_connect adc_trigger/data_a_trig util_cpack_ad9963/adc_data_0 +ad_connect axi_ad9963/adc_enable_q util_cpack_ad9963/adc_enable_1 +ad_connect adc_trigger/data_valid_b_trig util_cpack_ad9963/adc_valid_1 +ad_connect adc_trigger/data_b_trig util_cpack_ad9963/adc_data_1 + +ad_connect adc_trigger_fifo/data_in util_cpack_ad9963/adc_data +ad_connect adc_trigger_fifo/data_in_valid util_cpack_ad9963/adc_valid +ad_connect adc_trigger_fifo/depth adc_trigger/trigger_offset + +ad_connect adc_trigger_fifo/data_out adc_trigger_extract/data_in +ad_connect adc_trigger_fifo/data_out_valid adc_trigger_extract/data_valid +ad_connect util_cpack_ad9963/adc_data adc_trigger_extract/data_in_trigger + +ad_connect adc_trigger_extract/data_out ad9963_adc_dmac/fifo_wr_din +ad_connect adc_trigger_extract/trigger_out ad9963_adc_dmac/fifo_wr_sync +ad_connect adc_trigger_fifo/data_out_valid ad9963_adc_dmac/fifo_wr_en + +ad_connect axi_dac_interpolate/dac_clk axi_ad9963/dac_clk + +ad_connect axi_dac_interpolate/dac_valid_a axi_ad9963/dac_valid_i +ad_connect axi_dac_interpolate/dac_valid_b axi_ad9963/dac_valid_q +ad_connect axi_dac_interpolate/dac_int_data_a axi_ad9963/dac_data_i +ad_connect axi_dac_interpolate/dac_int_data_b axi_ad9963/dac_data_q + +ad_connect ad9963_dac_dmac_a/fifo_rd_clk axi_ad9963/dac_clk +ad_connect ad9963_dac_dmac_b/fifo_rd_clk axi_ad9963/dac_clk + +ad_connect axi_dac_interpolate/dac_data_a ad9963_dac_dmac_a/fifo_rd_dout +ad_connect axi_dac_interpolate/dac_int_valid_a ad9963_dac_dmac_a/fifo_rd_en +ad_connect axi_dac_interpolate/dac_data_b ad9963_dac_dmac_b/fifo_rd_dout +ad_connect axi_dac_interpolate/dac_int_valid_b ad9963_dac_dmac_b/fifo_rd_en + +ad_connect /axi_ad9963/tx_data txd +ad_connect /axi_ad9963/tx_iq txiq +ad_connect /axi_ad9963/tx_clk tx_clk +ad_connect /axi_ad9963/trx_data rxd +ad_connect /axi_ad9963/trx_clk rx_clk +ad_connect /axi_ad9963/trx_iq rxiq + +ad_connect adc_trigger/data_a axi_adc_decimate/adc_dec_data_a +ad_connect adc_trigger/data_valid_a axi_adc_decimate/adc_dec_valid_a +ad_connect adc_trigger/data_b axi_adc_decimate/adc_dec_data_b +ad_connect adc_trigger/data_valid_b axi_adc_decimate/adc_dec_valid_b + +ad_connect adc_trigger/clk axi_ad9963/l_clk +ad_connect trigger_i adc_trigger/trigger_i +ad_connect trigger_o adc_trigger/trigger_o +ad_connect trigger_t adc_trigger/trigger_t + +ad_connect axi_ad9963/dac_sync_in axi_ad9963/dac_sync_out +ad_connect axi_ad9963/adc_dovf ad9963_adc_dmac/fifo_wr_overflow +ad_connect axi_ad9963/dac_dunf ad9963_dac_dmac_a/fifo_rd_underflow + +# interconnects + +ad_cpu_interconnect 0x70000000 clk_generator +ad_cpu_interconnect 0x70100000 logic_analyzer +ad_cpu_interconnect 0x70200000 axi_ad9963 +ad_cpu_interconnect 0x7C400000 logic_analyzer_dmac +ad_cpu_interconnect 0x7C420000 pattern_generator_dmac +ad_cpu_interconnect 0x7C440000 ad9963_adc_dmac +ad_cpu_interconnect 0x7C460000 ad9963_dac_dmac_b +ad_cpu_interconnect 0x7C480000 ad9963_dac_dmac_a +ad_cpu_interconnect 0x7C4c0000 adc_trigger +ad_cpu_interconnect 0x7C500000 axi_adc_decimate +ad_cpu_interconnect 0x7C5a0000 axi_dac_interpolate + +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk logic_analyzer_dmac/m_dest_axi +ad_mem_hp1_interconnect sys_cpu_clk pattern_generator_dmac/m_src_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk ad9963_adc_dmac/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk ad9963_dac_dmac_a/m_src_axi +ad_mem_hp2_interconnect sys_cpu_clk ad9963_dac_dmac_b/m_src_axi +ad_connect sys_cpu_resetn logic_analyzer_dmac/m_dest_axi_aresetn +ad_connect sys_cpu_resetn pattern_generator_dmac/m_src_axi_aresetn +ad_connect sys_cpu_resetn ad9963_adc_dmac/m_dest_axi_aresetn +ad_connect sys_cpu_resetn ad9963_dac_dmac_a/m_src_axi_aresetn +ad_connect sys_cpu_resetn ad9963_dac_dmac_b/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-12 logic_analyzer_dmac/irq +ad_cpu_interrupt ps-12 mb-13 pattern_generator_dmac/irq +ad_cpu_interrupt ps-10 mb-14 ad9963_adc_dmac/irq +ad_cpu_interrupt ps-9 mb-15 ad9963_dac_dmac_a/irq +ad_cpu_interrupt ps-8 mb-16 ad9963_dac_dmac_b/irq + diff --git a/projects/m2k/common/m2k_spi.v b/projects/m2k/common/m2k_spi.v new file mode 100644 index 000000000..d7bcc9280 --- /dev/null +++ b/projects/m2k/common/m2k_spi.v @@ -0,0 +1,92 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module m2k_spi ( + + // 4-wire + + input ad9963_csn, + input adf4360_cs, + input spi_clk, + input spi_mosi, + output spi_miso, + + // 3-wire + + inout spi_sdio); + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // check on rising edge and change on falling edge + + always @(posedge spi_clk or posedge ad9963_csn) begin + if (ad9963_csn == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= spi_count + 1'b1; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge ad9963_csn) begin + if (ad9963_csn == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if ((spi_count == 6'd16) && (ad9963_csn == 1'b0)) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io buffers + + assign spi_miso = spi_sdio; + assign spi_sdio = (spi_enable == 1'b1) ? 1'bz : spi_mosi; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/m2k/standalone/Makefile b/projects/m2k/standalone/Makefile new file mode 100644 index 000000000..3caeff064 --- /dev/null +++ b/projects/m2k/standalone/Makefile @@ -0,0 +1,86 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/m2k_spi.v +M_DEPS += ../common/m2k_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9963/axi_ad9963.xpr +M_DEPS += ../../../library/axi_adc_decimate/axi_adc_decimate.xpr +M_DEPS += ../../../library/axi_adc_trigger/axi_adc_trigger.xpr +M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/axi_dac_interpolate/axi_dac_interpolate.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_logic_analyzer/axi_logic_analyzer.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_extract/util_extract.xpr +M_DEPS += ../../../library/util_var_fifo/util_var_fifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib m2k.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9963 clean + make -C ../../../library/axi_adc_decimate clean + make -C ../../../library/axi_adc_trigger clean + make -C ../../../library/axi_clkgen clean + make -C ../../../library/axi_dac_interpolate clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_logic_analyzer clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_extract clean + make -C ../../../library/util_var_fifo clean + + +m2k.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> m2k_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9963 + make -C ../../../library/axi_adc_decimate + make -C ../../../library/axi_adc_trigger + make -C ../../../library/axi_clkgen + make -C ../../../library/axi_dac_interpolate + make -C ../../../library/axi_dmac + make -C ../../../library/axi_logic_analyzer + make -C ../../../library/util_cpack + make -C ../../../library/util_extract + make -C ../../../library/util_var_fifo + +#################################################################################### +#################################################################################### diff --git a/projects/m2k/standalone/system_bd.tcl b/projects/m2k/standalone/system_bd.tcl new file mode 100644 index 000000000..7dbeff4e3 --- /dev/null +++ b/projects/m2k/standalone/system_bd.tcl @@ -0,0 +1,142 @@ + +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir I -from 63 -to 0 gpio_i +create_bd_port -dir O -from 63 -to 0 gpio_o +create_bd_port -dir O -from 63 -to 0 gpio_t + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7] +set_property -dict [list CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 3.3V}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + +# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) + +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7 + +set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] +set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main +set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main + +set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc + +set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] +set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO +ad_connect iic_main axi_iic_main/iic + +# spi connections + +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# interconnects + +ad_cpu_interconnect 0x41600000 axi_iic_main + +source ../common/m2k_bd.tcl + +set_property -dict [list CONFIG.DAC_DATAPATH_DISABLE {1}] $axi_ad9963 +set_property -dict [list CONFIG.ADC_DATAPATH_DISABLE {1}] $axi_ad9963 diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc new file mode 100644 index 000000000..f0d01adc1 --- /dev/null +++ b/projects/m2k/standalone/system_constr.xdc @@ -0,0 +1,66 @@ + +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports iic_scl] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports iic_sda] + +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports ad9963_resetn] + +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports adf4360_cs] +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports ad9963_csn] +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports spi_sdio] + +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports en_power_analog] + +set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports trigger_bd[0]] +set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports trigger_bd[1]] + +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[0]] +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[1]] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[2]] +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[3]] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[4]] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[5]] +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[6]] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[7]] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[8]] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[9]] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[10]] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[11]] +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[12]] +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[13]] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[14]] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports data_bd[15]] + +set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rx_clk] +set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxiq] +set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[0]] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[1]] +set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[2]] +set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[3]] +set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[4]] +set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[5]] +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[6]] +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[7]] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[8]] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[9]] +set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[10]] +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS33 SLEW SLOW} [get_ports rxd[11]] + +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS33} [get_ports tx_clk] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports txiq] +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS33} [get_ports txd[0]] +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS33} [get_ports txd[1]] +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports txd[2]] +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS33} [get_ports txd[3]] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports txd[4]] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports txd[5]] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports txd[6]] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports txd[7]] +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports txd[8]] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports txd[9]] +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS33} [get_ports txd[10]] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports txd[11]] + +create_clock -period 10.000 -name rx_clk [get_ports rx_clk] +create_clock -period 12.500 -name trigger_clk [get_ports {trigger_bd[0]}] +create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}] diff --git a/projects/m2k/standalone/system_project.tcl b/projects/m2k/standalone/system_project.tcl new file mode 100644 index 000000000..38d329e96 --- /dev/null +++ b/projects/m2k/standalone/system_project.tcl @@ -0,0 +1,16 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z010clg225-1" +adi_project_create m2k + +adi_project_files m2k [list \ + "../common/m2k_spi.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +adi_project_run m2k + diff --git a/projects/m2k/standalone/system_top.v b/projects/m2k/standalone/system_top.v new file mode 100644 index 000000000..97153f6df --- /dev/null +++ b/projects/m2k/standalone/system_top.v @@ -0,0 +1,199 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 1:0] ddr_dm, + inout [15:0] ddr_dq, + inout [ 1:0] ddr_dqs_n, + inout [ 1:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [31:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [15:0] data_bd, + inout [ 1:0] trigger_bd, + + input rx_clk, + input rxiq, + input [11:0] rxd, + output tx_clk, + output txiq, + output [11:0] txd, + + output ad9963_resetn, + output ad9963_csn, + output adf4360_cs, + output spi_clk, + inout spi_sdio, + + output en_power_analog, + + inout iic_scl, + inout iic_sda); + + // internal signals + + wire [63:0] gpio_o; + + wire [15:0] data_i; + wire [15:0] data_o; + wire [15:0] data_t; + + wire [ 1:0] trigger_i; + wire [ 1:0] trigger_o; + wire [ 1:0] trigger_t; + + wire [ 1:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + + assign ad9963_resetn = gpio_o[32]; + assign en_power_analog = gpio_o[33]; + + assign ad9963_csn = spi0_csn[0]; + assign adf4360_cs = spi0_csn[1]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(16) + ) i_data_bd ( + .dio_t(data_t[15:0]), + .dio_i(data_o[15:0]), + .dio_o(data_i[15:0]), + .dio_p(data_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_trigger_bd ( + .dio_t(trigger_t[1:0]), + .dio_i(trigger_o[1:0]), + .dio_o(trigger_i[1:0]), + .dio_p(trigger_bd)); + + m2k_spi i_m2k_spi ( + .ad9963_csn (ad9963_csn), + .adf4360_cs (adf4360_cs), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (64'h0), + .gpio_o (gpio_o), + .gpio_t (), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .data_i(data_i), + .data_o(data_o), + .data_t(data_t), + .trigger_i(trigger_i), + .trigger_o(trigger_o), + .trigger_t(trigger_t), + .rx_clk(rx_clk), + .rxiq(rxiq), + .rxd(rxd), + .tx_clk(tx_clk), + .txiq(txiq), + .txd(txd), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_15 (1'b0), + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/m2k/zed/Makefile b/projects/m2k/zed/Makefile new file mode 100644 index 000000000..e249888ad --- /dev/null +++ b/projects/m2k/zed/Makefile @@ -0,0 +1,100 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/m2k_spi.v +M_DEPS += ../common/m2k_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/axi_ad9963/axi_ad9963.xpr +M_DEPS += ../../../library/axi_adc_decimate/axi_adc_decimate.xpr +M_DEPS += ../../../library/axi_adc_trigger/axi_adc_trigger.xpr +M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/axi_dac_interpolate/axi_dac_interpolate.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr +M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr +M_DEPS += ../../../library/axi_logic_analyzer/axi_logic_analyzer.xpr +M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_extract/util_extract.xpr +M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr +M_DEPS += ../../../library/util_var_fifo/util_var_fifo.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib m2k_fmc_zed.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9963 clean + make -C ../../../library/axi_adc_decimate clean + make -C ../../../library/axi_adc_trigger clean + make -C ../../../library/axi_clkgen clean + make -C ../../../library/axi_dac_interpolate clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_hdmi_tx clean + make -C ../../../library/axi_i2s_adi clean + make -C ../../../library/axi_logic_analyzer clean + make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_extract clean + make -C ../../../library/util_i2c_mixer clean + make -C ../../../library/util_var_fifo clean + + +m2k_fmc_zed.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> m2k_fmc_zed_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9963 + make -C ../../../library/axi_adc_decimate + make -C ../../../library/axi_adc_trigger + make -C ../../../library/axi_clkgen + make -C ../../../library/axi_dac_interpolate + make -C ../../../library/axi_dmac + make -C ../../../library/axi_hdmi_tx + make -C ../../../library/axi_i2s_adi + make -C ../../../library/axi_logic_analyzer + make -C ../../../library/axi_spdif_tx + make -C ../../../library/util_cpack + make -C ../../../library/util_extract + make -C ../../../library/util_i2c_mixer + make -C ../../../library/util_var_fifo + +#################################################################################### +#################################################################################### diff --git a/projects/m2k/zed/system_bd.tcl b/projects/m2k/zed/system_bd.tcl new file mode 100644 index 000000000..dc673a39d --- /dev/null +++ b/projects/m2k/zed/system_bd.tcl @@ -0,0 +1,4 @@ + +source ../../common/zed/zed_system_bd.tcl +source ../common/m2k_bd.tcl + diff --git a/projects/m2k/zed/system_constr.xdc b/projects/m2k/zed/system_constr.xdc new file mode 100644 index 000000000..5266b1090 --- /dev/null +++ b/projects/m2k/zed/system_constr.xdc @@ -0,0 +1,85 @@ +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports otg_vbusoc] + +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]] ; ## BTNC +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]] ; ## BTND +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]] ; ## BTNL +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]] ; ## BTNR +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]] ; ## BTNU + +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[11]] ; ## SW0 +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[12]] ; ## SW1 +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[13]] ; ## SW2 +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[14]] ; ## SW3 +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[15]] ; ## SW4 +set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[16]] ; ## SW5 +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[17]] ; ## SW6 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[18]] ; ## SW7 + +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[31]] ; ## OTG-RESETN + +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports en_power_analog] ; ## A16 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports ad9963_resetn] ; ## G33 FMC_LPC_LA31_P + +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports adf4360_cs] ; ## G36 FMC_LPC_LA33_P +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports ad9963_csn] ; ## G34 FMC_LPC_LA31_N +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports spi_clk] ; ## G30 FMC_LPC_LA29_P +set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports spi_sdio] ; ## G31 FMC_LPC_LA29_N + +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports trigger_bd[0]] ; ## C22 FMC_LPC_LA18_CC_P +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports trigger_bd[1]] ; ## C23 FMC_LPC_LA18_CC_N + +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports data_bd[0]] ; ## D20 FMC_LPC_LA17_CC_P +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports data_bd[1]] ; ## D21 FMC_LPC_LA17_CC_N +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports data_bd[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33 } [get_ports data_bd[3]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports data_bd[4]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports data_bd[5]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports data_bd[6]] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports data_bd[7]] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports data_bd[8]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33 } [get_ports data_bd[9]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports data_bd[10]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports data_bd[11]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports data_bd[12]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports data_bd[13]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33 } [get_ports data_bd[14]] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33 } [get_ports data_bd[15]] ; ## C27 FMC_LPC_LA27_P + +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports rx_clk] ; ## G07 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports rxiq] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports rxd[0]] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports rxd[1]] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports rxd[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports rxd[3]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports rxd[4]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports rxd[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports rxd[6]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports rxd[7]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33} [get_ports rxd[8]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports rxd[9]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS33} [get_ports rxd[10]] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS33} [get_ports rxd[11]] ; ## H23 FMC_LPC_LA19_N + +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports tx_clk] ; ## G06 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports txiq] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports txd[0]] ; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33} [get_ports txd[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports txd[2]] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports txd[3]] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports txd[4]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports txd[5]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS33} [get_ports txd[6]] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports txd[7]] ; ## G19 FMC_LPC_LA16_N +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports txd[8]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports txd[9]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports txd[10]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports txd[11]] ; ## G25 FMC_LPC_LA22_N + +create_clock -name rx_clk -period 10.00 [get_ports rx_clk] +create_clock -name trigger_clk -period 12.5 [get_ports trigger_bd[0]] +create_clock -name data_clk -period 12.5 [get_ports data_bd[0]] diff --git a/projects/m2k/zed/system_project.tcl b/projects/m2k/zed/system_project.tcl new file mode 100644 index 000000000..698017bb5 --- /dev/null +++ b/projects/m2k/zed/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_create m2k_fmc_zed +adi_project_files m2k_fmc_zed [list \ + "../common/m2k_spi.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +set_property PROCESSING_ORDER EARLY [get_files "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +adi_project_run m2k_fmc_zed + diff --git a/projects/m2k/zed/system_top.v b/projects/m2k/zed/system_top.v new file mode 100644 index 000000000..c3ac220f0 --- /dev/null +++ b/projects/m2k/zed/system_top.v @@ -0,0 +1,276 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + inout [15:0] data_bd, + inout [ 1:0] trigger_bd, + + input rx_clk, + input rxiq, + input [11:0] rxd, + output tx_clk, + output txiq, + output [11:0] txd, + + output ad9963_resetn, + output ad9963_csn, + output adf4360_cs, + output spi_clk, + inout spi_sdio, + + output en_power_analog, + + inout iic_scl, + inout iic_sda); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + wire [15:0] data_i; + wire [15:0] data_o; + wire [15:0] data_t; + + wire [ 1:0] trigger_i; + wire [ 1:0] trigger_o; + wire [ 1:0] trigger_t; + + wire [ 1:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + + assign ad9963_resetn = gpio_o[32]; + assign en_power_analog = gpio_o[33]; + + assign ad9963_csn = spi0_csn[0]; + assign adf4360_cs = spi0_csn[1]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + ad_iobuf #( + .DATA_WIDTH(16) + ) i_data_bd ( + .dio_t(data_t[15:0]), + .dio_i(data_o[15:0]), + .dio_o(data_i[15:0]), + .dio_p(data_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_trigger_bd ( + .dio_t(trigger_t[1:0]), + .dio_i(trigger_o[1:0]), + .dio_o(trigger_i[1:0]), + .dio_p(trigger_bd)); + + m2k_spi i_m2k_spi ( + .ad9963_csn (ad9963_csn), + .adf4360_cs (adf4360_cs), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .data_i(data_i), + .data_o(data_o), + .data_t(data_t), + .trigger_i(trigger_i), + .trigger_o(trigger_o), + .trigger_t(trigger_t), + .rx_clk(rx_clk), + .rxiq(rxiq), + .rxd(rxd), + .tx_clk(tx_clk), + .txiq(txiq), + .txd(txd), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// ***************************************************************************